From 5375dd3fdb67e3fa1854935115909bb07df02dc4 Mon Sep 17 00:00:00 2001
From: Huixian Ma <huixma@qti.qualcomm.com>
Date: Tue, 11 May 2021 19:01:21 +0800
Subject: [PATCH] ARM: dts: msm: Add jtag_mm nodes for monaco

Enable jtag_mm nodes to support cpu etm save/restore feature.

Change-Id: I840df2bd17547432123dac84b10b8b7bf32b324c
---
 qcom/monaco.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/qcom/monaco.dtsi b/qcom/monaco.dtsi
index a7419ddaa742..bdc3980efef1 100644
--- a/qcom/monaco.dtsi
+++ b/qcom/monaco.dtsi
@@ -1122,6 +1122,50 @@
 		};
 	};
 
+	jtag_mm0: jtagmm@9040000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9040000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU0>;
+	};
+
+	jtag_mm1: jtagmm@9140000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9140000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU1>;
+	};
+
+	jtag_mm2: jtagmm@9240000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9240000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU2>;
+	};
+
+	jtag_mm3: jtagmm@9340000 {
+		compatible = "qcom,jtagv8-mm";
+		reg = <0x9340000 0x1000>;
+		reg-names = "etm-base";
+
+		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+		clock-names = "core_clk";
+
+		qcom,coresight-jtagmm-cpu = <&CPU3>;
+	};
+
 	clk_virt: interconnect {
 		compatible = "qcom,monaco-clk_virt";
 		#interconnect-cells = <1>;