diff --git a/qcom/lahaina-regulators.dtsi b/qcom/lahaina-regulators.dtsi index 6c991a4842e5..f0bf7326cdb7 100644 --- a/qcom/lahaina-regulators.dtsi +++ b/qcom/lahaina-regulators.dtsi @@ -372,7 +372,7 @@ pm8350c_s8_level-parent-supply = <&VDD_MXA_LEVEL>; pm8350c_s8_level_ao-parent-supply = <&VDD_MXA_LEVEL_AO>; - VDD_MMCX_LEVEL: S8C_LEVEL: + VDD_MMCX_LEVEL: S8C_LEVEL: VDD_MM_LEVEL: pm8350c_s8_level: regulator-pm8350c-s8-level { regulator-name = "pm8350c_s8_level"; qcom,set = ; @@ -386,7 +386,7 @@ regulator-always-on; }; - VDD_MMCX_LEVEL_AO: S8C_LEVEL_AO: + VDD_MMCX_LEVEL_AO: S8C_LEVEL_AO: VDD_MM_LEVEL_AO: pm8350c_s8_level_ao: regulator-pm8350c-s8-level-ao { regulator-name = "pm8350c_s8_level_ao"; qcom,set = ; diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi index 6ab1732d13b5..8b7bca6dc028 100644 --- a/qcom/lahaina-rumi.dtsi +++ b/qcom/lahaina-rumi.dtsi @@ -15,6 +15,9 @@ limit-tx-hs-gear = <1>; limit-rx-hs-gear = <1>; + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8350_l7>; vcc-max-microamp = <800000>; @@ -80,3 +83,7 @@ dr_mode = "peripheral"; }; }; + +&gpu_cc_cx_gdsc { + qcom,gds-timeout = <5000>; +}; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 1c0e85337aaf..69816249ee74 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -548,6 +548,267 @@ #reset-cells = <1>; }; + /* CAM_CC GDSCs */ + cam_cc_bps_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + reg = <0xad07004 0x4>; + regulator-name = "cam_cc_bps_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; + }; + + cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + reg = <0xad0a004 0x4>; + regulator-name = "cam_cc_ife_0_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + + cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 { + compatible = "qcom,gdsc"; + reg = <0xad0b004 0x4>; + regulator-name = "cam_cc_ife_1_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + + cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 { + compatible = "qcom,gdsc"; + reg = <0xad0b070 0x4>; + regulator-name = "cam_cc_ife_2_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + + cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 { + compatible = "qcom,gdsc"; + reg = <0xad08004 0x4>; + regulator-name = "cam_cc_ipe_0_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; + }; + + cam_cc_sbi_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + reg = <0xad09004 0x4>; + regulator-name = "cam_cc_sbi_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + + cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 { + compatible = "qcom,gdsc"; + reg = <0xad0c120 0x4>; + regulator-name = "cam_cc_titan_top_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + + /* DISP_CC GDSCs */ + disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + reg = <0xaf03000 0x4>; + regulator-name = "disp_cc_mdss_core_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; + }; + + /* GCC GDSCs */ + gcc_pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + reg = <0x16b004 0x4>; + regulator-name = "gcc_pcie_0_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + gcc_pcie_1_gdsc: qcom,gdsc@18d004 { + compatible = "qcom,gdsc"; + reg = <0x18d004 0x4>; + regulator-name = "gcc_pcie_1_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + gcc_ufs_card_gdsc: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + reg = <0x175004 0x4>; + regulator-name = "gcc_ufs_card_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + gcc_ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + reg = <0x177004 0x4>; + regulator-name = "gcc_ufs_phy_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + gcc_usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + reg = <0x10f004 0x4>; + regulator-name = "gcc_usb30_prim_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + gcc_usb30_sec_gdsc: qcom,gdsc@110004 { + compatible = "qcom,gdsc"; + reg = <0x110004 0x4>; + regulator-name = "gcc_usb30_sec_gdsc"; + parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; + }; + + gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + reg = <0x17d050 0x4>; + regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + }; + + gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + reg = <0x17d058 0x4>; + regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + }; + + gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + reg = <0x17d054 0x4>; + regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + }; + + gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c { + compatible = "qcom,gdsc"; + reg = <0x17d06c 0x4>; + regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc"; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + }; + + /* GPU_CC GDSCs */ + gpu_cc_cx_hw_ctrl: syscon@3d91540 { + compatible = "syscon"; + reg = <0x3d91540 0x4>; + }; + + gpu_cc_cx_gdsc: qcom,gdsc@3d9106c { + compatible = "qcom,gdsc"; + reg = <0x3d9106c 0x4>; + regulator-name = "gpu_cc_cx_gdsc"; + hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>; + parent-supply = <&VDD_CX_LEVEL>; + qcom,no-status-check-on-disable; + qcom,clk-dis-wait-val = <8>; + qcom,gds-timeout = <500>; + qcom,retain-regs; + }; + + gpu_cc_gx_domain_addr: syscon@3d9158c { + compatible = "syscon"; + reg = <0x3d9158c 0x4>; + }; + + gpu_cc_gx_sw_reset: syscon@3d91008 { + compatible = "syscon"; + reg = <0x3d91008 0x4>; + }; + + gpu_cc_gx_gdsc: qcom,gdsc@3d9100c { + compatible = "qcom,gdsc"; + reg = <0x3d9100c 0x4>; + regulator-name = "gpu_cc_gx_gdsc"; + domain-addr = <&gpu_cc_gx_domain_addr>; + sw-reset = <&gpu_cc_gx_sw_reset>; + parent-supply = <&VDD_GFX_LEVEL>; + vdd_parent-supply = <&VDD_GFX_LEVEL>; + qcom,reset-aon-logic; + qcom,retain-regs; + }; + + /* VIDEO_CC GDSCs */ + video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 { + compatible = "qcom,gdsc"; + reg = <0xabf0d18 0x4>; + regulator-name = "video_cc_mvs0_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; + }; + + video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 { + compatible = "qcom,gdsc"; + reg = <0xabf0bf8 0x4>; + regulator-name = "video_cc_mvs0c_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + + video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 { + compatible = "qcom,gdsc"; + reg = <0xabf0d98 0x4>; + regulator-name = "video_cc_mvs1_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,support-hw-trigger; + qcom,retain-regs; + }; + + video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 { + compatible = "qcom,gdsc"; + reg = <0xabf0c98 0x4>; + regulator-name = "video_cc_mvs1c_gdsc"; + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MM_LEVEL>; + vdd_parent-supply = <&VDD_MM_LEVEL>; + qcom,retain-regs; + }; + cache-controller@9200000 { compatible = "qcom,lahaina-llcc", "qcom,llcc-v2"; reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;