diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 27bb483e2d35..bf46e4507e98 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -216,6 +216,42 @@ }; }; + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + i2c_1 { i2c_1_active: i2c_1_active { mux { diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 279d02c7ca5e..7ade3cdbd9a3 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -785,6 +785,249 @@ compatible = "qcom,msm_gsi"; }; + + pcie_ep: qcom,pcie@40002000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40002000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x01c03000 0x1000>, + <0x01fcb000 0x1000>, + <0xc2f1000 0x4>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio", "tcsr_pcie_perst_en", "aoss_cc_reset"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 140 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 56 0>; + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gcc_pcie_gdsc>; + vreg-1p8-supply = <&pmx65_l1>; + vreg-0p9-supply = <&pmx65_l4>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 3000>; + qcom,vreg-0p9-voltage-level = <912000 912000 132000>; + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_PIPE_CLK_SRC>, + <&pcie_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk", + "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_BCR>, + <&gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + interconnect-names = "icc_path"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0308>; + qcom,pcie-link-speed = <4>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg2 = <0x1214>; + qcom,mhi-soc-reset-offset = <0xb01b8>; + qcom,aoss-rst-clr; + + qcom,phy-init = <0x1240 0x01 0x0 + 0x100c 0x02 0x0 + 0x1044 0x14 0x0 + 0x104c 0x07 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x27 0x0 + 0x1078 0x0a 0x0 + 0x107c 0x17 0x0 + 0x1080 0x19 0x0 + 0x1084 0x00 0x0 + 0x1088 0x03 0x0 + 0x1094 0x00 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0xff 0x0 + 0x10b0 0x04 0x0 + 0x10b4 0xff 0x0 + 0x10b8 0x09 0x0 + 0x10bc 0x19 0x0 + 0x10c4 0x28 0x0 + 0x117c 0x06 0x0 + 0x10ec 0xfb 0x0 + 0x10f0 0x01 0x0 + 0x10f4 0xfb 0x0 + 0x10f8 0x01 0x0 + 0x110c 0x02 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x0a 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x1174 0x20 0x0 + 0x11a0 0x14 0x0 + 0x11a8 0x0f 0x0 + 0x0220 0x16 0x0 + 0x03c0 0x38 0x0 + 0x0a20 0x16 0x0 + 0x0bc0 0x38 0x0 + 0x0364 0xcc 0x0 + 0x0368 0x12 0x0 + 0x036c 0xcc 0x0 + 0x0374 0x4a 0x0 + 0x0378 0x29 0x0 + 0x037c 0xc5 0x0 + 0x0380 0xac 0x0 + 0x0384 0xb6 0x0 + 0x0388 0xc0 0x0 + 0x038c 0x07 0x0 + 0x0390 0xfb 0x0 + 0x0394 0x0d 0x0 + 0x0398 0xc5 0x0 + 0x039c 0xee 0x0 + 0x03a0 0xbf 0x0 + 0x03a4 0xa0 0x0 + 0x03a8 0x81 0x0 + 0x03ac 0xde 0x0 + 0x03b0 0x7f 0x0 + 0x0b64 0xcc 0x0 + 0x0b68 0x12 0x0 + 0x0b6c 0xcc 0x0 + 0x0b74 0x4a 0x0 + 0x0b78 0x29 0x0 + 0x0b7c 0xc5 0x0 + 0x0b80 0xac 0x0 + 0x0b84 0xb6 0x0 + 0x0b88 0xc0 0x0 + 0x0b8c 0x07 0x0 + 0x0b90 0xfb 0x0 + 0x0b94 0x0d 0x0 + 0x0b98 0xc5 0x0 + 0x0b9c 0xee 0x0 + 0x0ba0 0xbf 0x0 + 0x0ba4 0xa0 0x0 + 0x0ba8 0x81 0x0 + 0x0bac 0xde 0x0 + 0x0bb0 0x7f 0x0 + 0x03b4 0x20 0x0 + 0x022c 0x3f 0x0 + 0x0230 0x37 0x0 + 0x0bb4 0x20 0x0 + 0x0a2c 0x3f 0x0 + 0x0a30 0x37 0x0 + 0x0078 0x05 0x0 + 0x007c 0xf6 0x0 + 0x0878 0x05 0x0 + 0x087c 0xf6 0x0 + 0x0290 0x05 0x0 + 0x0a90 0x05 0x0 + 0x03f8 0x1f 0x0 + 0x0400 0x1f 0x0 + 0x0408 0x1f 0x0 + 0x0410 0x1f 0x0 + 0x0418 0x1f 0x0 + 0x0420 0x1f 0x0 + 0x03f4 0x1f 0x0 + 0x03fc 0x1f 0x0 + 0x0404 0x1f 0x0 + 0x0bf8 0x1f 0x0 + 0x0c00 0x1f 0x0 + 0x0c08 0x1f 0x0 + 0x0c10 0x1f 0x0 + 0x0c18 0x1f 0x0 + 0x0c20 0x1f 0x0 + 0x0bf4 0x1f 0x0 + 0x0bfc 0x1f 0x0 + 0x0c04 0x1f 0x0 + 0x0208 0x0c 0x0 + 0x0a08 0x0c 0x0 + 0x020c 0x0a 0x0 + 0x0a0c 0x0a 0x0 + 0x02dc 0x0a 0x0 + 0x0adc 0x0a 0x0 + 0x0308 0x0b 0x0 + 0x0b08 0x0b 0x0 + 0x027c 0x10 0x0 + 0x0a7c 0x10 0x0 + 0x02b4 0x00 0x0 + 0x0ab4 0x00 0x0 + 0x02ec 0x0f 0x0 + 0x0aec 0x0f 0x0 + 0x02c4 0x00 0x0 + 0x02c8 0x1f 0x0 + 0x0ac4 0x00 0x0 + 0x0ac8 0x1f 0x0 + 0x0030 0x1a 0x0 + 0x0034 0x0c 0x0 + 0x0830 0x1a 0x0 + 0x0834 0x0c 0x0 + 0x13e0 0x16 0x0 + 0x13e4 0x22 0x0 + 0x1508 0x02 0x0 + 0x14a0 0x16 0x0 + 0x1584 0x28 0x0 + 0x1370 0x2e 0x0 + 0x155c 0x2e 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + status = "disabled"; + }; + + mhi_device: mhi_dev@1c03000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c03000 0x1000>, + <0x3E28000 0x4>, + <0x3E28148 0x4>; + reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb", + "ipa_uc_mbox_erdb"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-ipa-software-channel; + interrupts = <0 145 0>; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x030817cb>; + qcom,mhi-interrupt; + status = "disabled"; + }; + + mhi_net_device: qcom,mhi_net_dev { + compatible = "qcom,msm-mhi-dev-net"; + status = "disabled"; + }; + qcom,rmnet-ipa { compatible = "qcom,rmnet-ipa3"; qcom,rmnet-ipa-ssr;