diff --git a/drivers/staging/fw-api/fw/htc.h b/drivers/staging/fw-api/fw/htc.h index 348c719a7231..8e7f13dc8b42 100644 --- a/drivers/staging/fw-api/fw/htc.h +++ b/drivers/staging/fw-api/fw/htc.h @@ -165,13 +165,17 @@ typedef PREPACK struct _HTC_FRAME_HDR{ /* base message ID header */ typedef PREPACK struct { - A_UINT32 MessageID : 16, - reserved : 16; + A_UINT32 MessageID: 16, + MetaData: 8, + reserved: 8; } POSTPACK HTC_UNKNOWN_MSG; #define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0 #define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff #define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_UNKNOWN_MSG_METADATA_LSB 16 +#define HTC_UNKNOWN_MSG_METADATA_MASK 0X00ff0000 +#define HTC_UNKNOWN_MSG_METADATA_OFFSET 0x00000000 /* HTC ready message * direction : target-to-host */ diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h index b27e7bbcf194..6089d196421b 100644 --- a/drivers/staging/fw-api/fw/htt.h +++ b/drivers/staging/fw-api/fw/htt.h @@ -243,9 +243,15 @@ * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. + * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. + * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. + * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. + * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. + * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg + * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 117 +#define HTT_CURRENT_VERSION_MINOR 123 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -558,10 +564,21 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * supported by the host. If the target doesn't provide a * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it * is implicitly understood that the V1 TCL metadata shall be used. + * + * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21 + * read as version 2.1. We added support for Dynamic AST Index Allocation + * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2 + * we will retain older behavior of making sure the AST Index for SAWF + * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1 + * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and + * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index + * in TCLV2 command and do the dynamic AST allocations. */ enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { HTT_OPTION_TLV_TCL_METADATA_V1 = 1, HTT_OPTION_TLV_TCL_METADATA_V2 = 2, + /* values 3-20 reserved */ + HTT_OPTION_TLV_TCL_METADATA_V21 = 21, }; PREPACK struct htt_option_tlv_tcl_metadata_ver_t { @@ -777,6 +794,14 @@ typedef enum { HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ + HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ + HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ + HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ HTT_STATS_MAX_TAG, @@ -848,6 +873,7 @@ enum htt_h2t_msg_type { HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, + HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, /* keep this last */ HTT_H2T_NUM_MSGS @@ -2563,7 +2589,8 @@ typedef struct { type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ svc_class_id: 8, - rsvd: 5, + ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */ + rsvd: 2, padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ } htt_tx_tcl_svc_class_id_metadata; @@ -5356,7 +5383,7 @@ enum htt_srng_ring_id { (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ - do { \ + do { \ HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ } while (0) @@ -7163,7 +7190,7 @@ PREPACK struct htt_tx_monitor_cfg_t { rsvd4: 10; A_UINT32 tx_queue_ext_v2_word_mask: 12, tx_peer_entry_v2_word_mask: 12, - rsvd5: 10; + rsvd5: 8; A_UINT32 fes_status_end_word_mask: 16, response_end_status_word_mask: 16; A_UINT32 fes_status_prot_word_mask: 11, @@ -9902,10 +9929,10 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { /** * @brief Format of shared memory between Host and Target - * for UMAC hang recovery feature messaging. + * for UMAC recovery feature messaging. * @details * This is shared memory between Host and Target allocated - * and used in chips where UMAC hang recovery feature is supported. + * and used in chips where UMAC recovery feature is supported. * This shared memory is allocated per SOC level by Host since each * SOC's target Q6FW needs to communicate independently to the Host * through its own shared memory. @@ -9923,11 +9950,12 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { * b'1 - do_post_reset_start * b'2 - do_post_reset_complete * b'3 - initiate_umac_recovery - * b'4:31 - rsvd_t2h + * b'4 - initiate_target_recovery_sync_using_umac + * b'5:31 - rsvd_t2h * dword2 - b'0 - pre_reset_done * b'1 - post_reset_start_done * b'2 - post_reset_complete_done - * b'3 - start_pre_reset + * b'3 - start_pre_reset (deprecated) * b'4:31 - rsvd_h2t */ PREPACK typedef struct { @@ -9938,18 +9966,23 @@ PREPACK typedef struct { * BIT [0] :- T2H msg to do pre-reset * BIT [1] :- T2H msg to do post-reset start * BIT [2] :- T2H msg to do post-reset complete - * BIT [3] :- T2H msg to initiate UMAC recovery sequence. - * This is needed to synchronize UMAC recovery - * across all SOCs. - * BIT [31 : 4] :- reserved + * BIT [3] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for UMAC hang. + * BIT [4] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for Mode-1 Target Recovery. + * BIT [31 : 5] :- reserved */ A_UINT32 t2h_msg; struct { - A_UINT32 do_pre_reset : 1, /* BIT [0] */ - do_post_reset_start : 1, /* BIT [1] */ - do_post_reset_complete : 1, /* BIT [2] */ - initiate_umac_recovery : 1, /* BIT [3] */ - rsvd_t2h : 28; /* BIT [31 : 4] */ + A_UINT32 + do_pre_reset: 1, /* BIT [0] */ + do_post_reset_start: 1, /* BIT [1] */ + do_post_reset_complete: 1, /* BIT [2] */ + initiate_umac_recovery: 1, /* BIT [3] */ + initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */ + rsvd_t2h: 27; /* BIT [31:5] */ }; }; @@ -9958,10 +9991,7 @@ PREPACK typedef struct { * BIT [0] :- H2T msg to send pre-reset done * BIT [1] :- H2T msg to send post-reset start done * BIT [2] :- H2T msg to send post-reset complete done - * BIT [3] :- H2T msg to start pre-reset. - * This is expected only after T2H - * initiate_umac_recovery was received by Host - * from one of the SOCs. + * BIT [3] :- H2T msg to start pre-reset. This is deprecated. * BIT [31 : 4] :- reserved */ A_UINT32 h2t_msg; @@ -10020,7 +10050,7 @@ PREPACK typedef struct { #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \ - (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ + (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S) #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \ do { \ @@ -10028,6 +10058,18 @@ PREPACK typedef struct { ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\ } while (0) +/* dword1 - b'4 - initiate_target_recovery_sync_using_umac */ +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010 +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4 +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \ + (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \ + HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S) +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \ + ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\ + } while (0) + /* dword2 - b'0 - pre_reset_done */ #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0 @@ -10191,12 +10233,13 @@ PREPACK typedef struct { * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent * beforehand. * - * |31 9|8|7 0| + * |31 10|9|8|7 0| * |-----------------------------------------------------------| - * | reserved |I| msg_type | + * | reserved |U|I| msg_type | * |-----------------------------------------------------------| * Where: * I = is_initiator + * U = is_umac_hang * * The message is interpreted as follows: * dword0 - b'0:7 - msg_type @@ -10205,13 +10248,16 @@ PREPACK typedef struct { * execute the UMAC-recovery in context of the Initiator or * Non-Initiator. * The value zero indicates this target is Non-Initiator. - * b'9:31 - reserved. + * b'9 - is_umac_hang: indicates whether MLO UMAC recovery + * executed in context of UMAC hang or Target recovery. + * b'10:31 - reserved. */ PREPACK typedef struct { A_UINT32 msg_type : 8, is_initiator : 1, - reserved : 23; + is_umac_hang : 1, + reserved : 22; } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t; #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \ @@ -10230,6 +10276,17 @@ PREPACK typedef struct { ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\ } while (0) +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200 +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9 +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \ + (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \ + HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S) +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \ + ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\ + } while (0) + /* * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message @@ -10245,7 +10302,7 @@ PREPACK typedef struct { * The message would appear as follows: * |31 24|23 16|15 8|7 0| * |-----------------+-----------------+-----------------+-----------------| - * | reserved | operation | vdev_id | msg_type | + * | reserved | operation | pdev_id | msg_type | * |-----------------------------------------------------------------------| * | cce_super_rule_param[0] | * |-----------------------------------------------------------------------| @@ -10255,7 +10312,7 @@ PREPACK typedef struct { * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) - * b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is for + * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for * b'16:23 - operation: Identify operation to be taken, * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST * 1: HTT_RX_CCE_SUPER_RULE_INSTALL @@ -10384,7 +10441,7 @@ typedef struct { PREPACK struct htt_rx_cce_super_rule_setup_t { A_UINT32 msg_type: 8, - vdev_id: 8, + pdev_id: 8, operation: 8, reserved: 8; htt_rx_cce_super_rule_param_t @@ -10394,15 +10451,15 @@ PREPACK struct htt_rx_cce_super_rule_setup_t { #define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ (sizeof(struct htt_rx_cce_super_rule_setup_t)) -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M 0x0000ff00 -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S 8 -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M) >> \ - HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S) -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_SET(_var, _val) \ +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S)); \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ } while (0) #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 @@ -10490,6 +10547,169 @@ PREPACK struct htt_rx_cce_super_rule_setup_t { } while (0) +/** + * htt_h2t_primary_link_peer_status_type - + * Unique number for each status or reasons + * The status reasons can go up to 255 max + */ +enum htt_h2t_primary_link_peer_status_type { + /* Host Primary Link Peer migration Success */ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0, + + + /* keep this last */ + /* Host Primary Link Peer migration Fail */ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254, + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255 +}; + + +/** + * @brief host -> Primary peer migration completion message from host + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP + * + * @details + * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to + * target Confirming that primary link peer migration has completed, + * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND + * message from the target. + * + * The message would appear as follows: + * + * |31 25|24|23 16|15 12|11 8|7 0| + * |----------------------------+----------+---------+--------------| + * | vdev ID | pdev ID | chip ID | msg type | + * |----------------------------+----------+---------+--------------| + * | ML peer ID | SW peer ID | + * |------------+--+------------+--------------------+--------------| + * | reserved |SV| src_info | status | + * |------------+--+---------------------------------+--------------| + * Where: + * SV = src_info_valid flag + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x24 + * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP) + * b'8:11 - chip_id: Indicate which chip has been chosen as primary + * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen + * as primary + * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen + * as primary + * + * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer + * chosen as primary + * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the + * primary peer belongs. + * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration + * b'8:23 - src_info: Indicates New Virtual port number through + * which Rx Pipe connects to the correct PPE. + * b'24 - src_info_valid: Indicates src_info is valid. + */ + +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + chip_id: 4, /* bits 11:8 */ + pdev_id: 4, /* bits 15:12 */ + vdev_id: 16; /* bits 31:16 */ + A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ + ml_peer_id: 16; /* bits 31:16 */ + A_UINT32 status: 8, /* bits 7:0 */ + src_info: 16, /* bits 23:8 */ + src_info_valid: 1, /* bit 24 */ + reserved: 7; /* bits 31:25 */ +} htt_h2t_primary_link_peer_migrate_resp_t; + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\ + } while (0) + + + /*=== target -> host messages ===============================================*/ @@ -10554,6 +10774,10 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, + HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, + HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, + HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, + HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, HTT_T2H_MSG_TYPE_TEST, @@ -14860,6 +15084,744 @@ PREPACK struct htt_tx_compl_ind_append_tx_tsf64 { (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S) +/** + * @brief target -> host software UMAC TX completion indication message + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND + * + * @details + * The following diagram shows the format of the soft UMAC TX completion + * indication sent from the target to the host + * + * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0| + * |-------------------------------------+----------------+------------| + * hdr: | rsvd | msdu_cnt | msg_type | + * pyld: |===================================================================| + * MSDU 0| buf addr low (bits 31:0) | + * |-----------------------------------------------+------+------------| + * | SW buffer cookie | RS | buf addr hi| + * |--------+--+--+-------------+--------+---------+------+------------| + * | rsvd0 | M| V| tx count | TID | SW peer ID | + * |--------+--+--+-------------+--------+----------------------+------| + * | frametype | TQM status number | RELR | + * |-----+-----+-----------------------------------+--+-+-+-----+------| + * |rsvd1| buffer timestamp | A|L|F| ACK RSSI | + * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-| + * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I| + * |--------+-------------------------+--+------+-----+--+-+-----+---+-| + * | PPDU transmission TSF | + * |-------------------------------------------------------------------| + * | rsvd3 | + * |===================================================================| + * MSDU 1| buf addr low (bits 31:0) | + * : ... : + * | rsvd3 | + * |===================================================================| + * etc. + * + * Where: + * RS = release source + * V = valid + * M = multicast + * RELR = release reason + * F = first MSDU + * L = last MSDU + * A = MSDU is part of A-MSDU + * I = rate info valid + * PKTYP = packet type + * S = STBC + * LC = LDPC + * OF = OFDMA transmission + */ +typedef enum { + /* 0 (REASON_FRAME_ACKED): + * Corresponds to tqm_release_reason = ; + * frame is removed because an ACK of BA for it was received. + */ + HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED, + + /* 1 (REASON_REMOVE_CMD_FW): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type "Remove_mpdus" + * initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW, + + /* 2 (REASON_REMOVE_CMD_TX): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type + * "Remove_transmitted_mpdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX, + + /* 3 (REASON_REMOVE_CMD_NOTX): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type + * "Remove_untransmitted_mpdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX, + + /* 4 (REASON_REMOVE_CMD_AGED): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type "Remove_aged_mpdus" + * or "Remove_aged_msdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED, + + /* 5 (RELEASE_FW_REASON1): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON1, + + /* 6 (RELEASE_FW_REASON2): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON2, + + /* 7 (RELEASE_FW_REASON3): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON3, + + /* 8 (REASON_REMOVE_CMD_DISABLEQ): + * Corresponds to tqm_release_reason = + * frame is removed because a remove command of type + * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow" + * initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ, + + /* 9 (REASON_DROP_MISC): + * Corresponds to sw_release_reason = Packet dropped by FW due to + * any discard reason that is not categorized as MSDU TTL expired. + * Examples: TXDE ENQ layer dropped the packet due to peer delete, + * tid delete, no resource credit available. + */ + HTT_TX_MSDU_RELEASE_REASON_DROP_MISC, + + /* 10 (REASON_DROP_TTL): + * Corresponds to sw_release_reason = Packet dropped by FW due to + * discard reason that frame is not transmitted due to MSDU TTL expired. + */ + HTT_TX_MSDU_RELEASE_REASON_DROP_TTL, + + /* 11 - available for use */ + /* 12 - available for use */ + /* 13 - available for use */ + /* 14 - available for use */ + /* 15 - available for use */ + + HTT_TX_MSDU_RELEASE_REASON_MAX = 16 +} htt_t2h_tx_msdu_release_reason_e; + +typedef enum { + /* 0 (RELEASE_SOURCE_FW): + * MSDU released by FW even before the frame was queued to TQM-L HW. + */ + HTT_TX_MSDU_RELEASE_SOURCE_FW, + + /* 1 (RELEASE_SOURCE_TQM_LITE): + * MSDU released by TQM-L HW. + */ + HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE, + + HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8 +} htt_t2h_tx_msdu_release_source_e; + +struct htt_t2h_tx_buffer_addr_info { /* 2 words */ + A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */ + A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */ + /* release_source: + * holds a htt_t2h_tx_msdu_release_source_e enum value + */ + release_source : 3, /* [10:8] */ + sw_buffer_cookie : 21; /* [31:11] */ + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_buffer_addr_info */ + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S) + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S) + +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700 +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8 + +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S) + +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800 +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11 + +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) + +struct htt_t2h_tx_rate_stats_info { /* 2 words */ + /* word 0 */ + A_UINT32 + /* tx_rate_stats_info_valid: + * Indicates if the tx rate stats below are valid. + */ + tx_rate_stats_info_valid : 1, /* [0] */ + /* transmit_bw: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Indicates the BW of the upcoming transmission that shall likely + * start in about 3 -4 us on the medium: + * + * + * + * + * + */ + transmit_bw : 3, /* [3:1] */ + /* transmit_pkt_type: + * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * The packet type + * + * Type: enum Definition Name: PKT_TYPE_ENUM + * enum number enum name Description + * ------------------------------------ + * 0 dot11a 802.11a PPDU type + * 1 dot11b 802.11b PPDU type + * 2 dot11n_mm 802.11n Mixed Mode PPDU type + * 3 dot11ac 802.11ac PPDU type + * 4 dot11ax 802.11ax PPDU type + * 5 dot11ba 802.11ba (WUR) PPDU type + * 6 dot11be 802.11be PPDU type + * 7 dot11az 802.11az (ranging) PPDU type + */ + transmit_pkt_type : 4, /* [7:4] */ + /* transmit_stbc: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * When set, STBC transmission rate was used. + */ + transmit_stbc : 1, /* [8] */ + /* transmit_ldpc: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * When set, use LDPC transmission rates + */ + transmit_ldpc : 1, /* [9] */ + /* transmit_sgi: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * Legacy normal GI. Can also be used for HE + * Legacy short GI. Can also be used for HE + * HE related GI + * HE related GI + * + */ + transmit_sgi : 2, /* [11:10] */ + /* transmit_mcs: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * + * For details, refer to MCS_TYPE description + * + * Pkt_type Related definition of MCS_TYPE + * dot11b This field is the rate: + * 0: CCK 11 Mbps Long + * 1: CCK 5.5 Mbps Long + * 2: CCK 2 Mbps Long + * 3: CCK 1 Mbps Long + * 4: CCK 11 Mbps Short + * 5: CCK 5.5 Mbps Short + * 6: CCK 2 Mbps Short + * NOTE: The numbering here is NOT the same as the as MAC gives + * in the "rate" field in the SIG given to the PHY. + * The MAC will do an internal translation. + * + * Dot11a This field is the rate: + * 0: OFDM 48 Mbps + * 1: OFDM 24 Mbps + * 2: OFDM 12 Mbps + * 3: OFDM 6 Mbps + * 4: OFDM 54 Mbps + * 5: OFDM 36 Mbps + * 6: OFDM 18 Mbps + * 7: OFDM 9 Mbps + * NOTE: The numbering here is NOT the same as the as MAC gives + * in the "rate" field in the SIG given to the PHY. + * The MAC will do an internal translation. + * + * Dot11n_mm (mixed mode) This field represends the MCS. + * 0: HT MCS 0 (BPSK 1/2) + * 1: HT MCS 1 (QPSK 1/2) + * 2: HT MCS 2 (QPSK 3/4) + * 3: HT MCS 3 (16-QAM 1/2) + * 4: HT MCS 4 (16-QAM 3/4) + * 5: HT MCS 5 (64-QAM 2/3) + * 6: HT MCS 6 (64-QAM 3/4) + * 7: HT MCS 7 (64-QAM 5/6) + * NOTE: To get higher MCS's use the nss field to indicate the + * number of spatial streams. + * + * Dot11ac This field represends the MCS. + * 0: VHT MCS 0 (BPSK 1/2) + * 1: VHT MCS 1 (QPSK 1/2) + * 2: VHT MCS 2 (QPSK 3/4) + * 3: VHT MCS 3 (16-QAM 1/2) + * 4: VHT MCS 4 (16-QAM 3/4) + * 5: VHT MCS 5 (64-QAM 2/3) + * 6: VHT MCS 6 (64-QAM 3/4) + * 7: VHT MCS 7 (64-QAM 5/6) + * 8: VHT MCS 8 (256-QAM 3/4) + * 9: VHT MCS 9 (256-QAM 5/6) + * 10: VHT MCS 10 (1024-QAM 3/4) + * 11: VHT MCS 11 (1024-QAM 5/6) + * NOTE: There are several illegal VHT rates due to fractional + * number of bits per symbol. + * Below are the illegal rates for 4 streams and lower: + * 20 MHz, 1 stream, MCS 9 + * 20 MHz, 2 stream, MCS 9 + * 20 MHz, 4 stream, MCS 9 + * 80 MHz, 3 stream, MCS 6 + * 160 MHz, 3 stream, MCS 9 (Unsupported) + * 160 MHz, 4 stream, MCS 7 (Unsupported) + * + * dot11ax This field represends the MCS. + * 0: HE MCS 0 (BPSK 1/2) + * 1: HE MCS 1 (QPSK 1/2) + * 2: HE MCS 2 (QPSK 3/4) + * 3: HE MCS 3 (16-QAM 1/2) + * 4: HE MCS 4 (16-QAM 3/4) + * 5: HE MCS 5 (64-QAM 2/3) + * 6: HE MCS 6 (64-QAM 3/4) + * 7: HE MCS 7 (64-QAM 5/6) + * 8: HE MCS 8 (256-QAM 3/4) + * 9: HE MCS 9 (256-QAM 5/6) + * 10: HE MCS 10 (1024-QAM 3/4) + * 11: HE MCS 11 (1024-QAM 5/6) + * 12: HE MCS 12 (4096-QAM 3/4) + * 13: HE MCS 13 (4096-QAM 5/6) + * + * dot11ba This field is the rate: + * 0: LDR + * 1: HDR + * 2: Exclusive rate + */ + transmit_mcs : 4, /* [15:12] */ + /* ofdma_transmission: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Set when the transmission was an OFDMA transmission (DL or UL). + * + */ + ofdma_transmission : 1, /* [16] */ + /* tones_in_ru: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * The number of tones in the RU used. + * + */ + tones_in_ru : 12, /* [28:17] */ + rsvd2 : 3; /* [31:29] */ + + /* word 1 */ + /* ppdu_transmission_tsf: + * Based on a HWSCH configuration register setting, + * this field either contains: + * Lower 32 bits of the TSF, snapshot of this value when transmission + * of the PPDU containing the frame finished. + * OR + * Lower 32 bits of the TSF, snapshot of this value when transmission + * of the PPDU containing the frame started. + * + */ + A_UINT32 ppdu_transmission_tsf; + + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_rate_stats_info */ + +#define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001 +#define HTT_TX_RATE_STATS_INFO_VALID_S 0 + +#define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S) + +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000 +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16 + +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S) + +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000 +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17 + +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S) + +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0 + +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S) + +struct htt_t2h_tx_msdu_info { /* 8 words */ + /* words 0 + 1 */ + struct htt_t2h_tx_buffer_addr_info addr_info; + + /* word 2 */ + A_UINT32 + sw_peer_id : 16, + tid : 4, + transmit_cnt : 7, + valid : 1, + mcast : 1, + rsvd0 : 3; + + /* word 3 */ + A_UINT32 + release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */ + tqm_status_number : 24, + frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */ + + /* word 4 */ + A_UINT32 + /* ack_frame_rssi: + * If this frame is removed as the result of the + * reception of an ACK or BA, this field indicates + * the RSSI of the received ACK or BA frame. + * When the frame is removed as result of a direct + * remove command from the SW, this field is set + * to 0x0 (which is never a valid value when real + * RSSI is available). + * Units: dB w.r.t noise floor + */ + ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + msdu_part_of_amsdu : 1, + buffer_timestamp : 19, /* units = TU = 1024 microseconds */ + rsvd1 : 2; + + /* words 5 + 6 */ + struct htt_t2h_tx_rate_stats_info tx_rate_stats; + + /* word 7 */ + /* rsvd3: + * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2] + * is not sufficient + */ + A_UINT32 rsvd3; + + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_msdu_info */ + +#define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF +#define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0 + +#define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S) + +#define HTT_TX_MSDU_INFO_TID_M 0x000F0000 +#define HTT_TX_MSDU_INFO_TID_S 16 + +#define HTT_TX_MSDU_INFO_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S) + +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000 +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20 + +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S) + +#define HTT_TX_MSDU_INFO_VALID_M 0x08000000 +#define HTT_TX_MSDU_INFO_VALID_S 27 + +#define HTT_TX_MSDU_INFO_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_VALID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S) + +#define HTT_TX_MSDU_INFO_MCAST_M 0x10000000 +#define HTT_TX_MSDU_INFO_MCAST_S 28 + +#define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_MCAST_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S) + +#define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F +#define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0 + +#define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S) + +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0 +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4 + +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S) + +#define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000 +#define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28 + +#define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S) + +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0 + +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S) + +#define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100 +#define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8 + +#define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S) + +#define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200 +#define HTT_TX_MSDU_INFO_LAST_MSDU_S 9 + +#define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S) + +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400 +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10 + +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S) + +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800 +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11 + +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S) + +struct htt_t2h_soft_umac_tx_compl_ind { + A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */ + msdu_cnt : 8, /* min: 0, max: 255 */ + rsvd0 : 16; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ + /* + * append here: + * struct htt_t2h_tx_msdu_info payload[1(or more)] + * for all the msdu's that are part of this completion. + */ +}; + +/* member definitions of htt_t2h_soft_umac_tx_compl_ind */ + +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00 +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8 + +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \ + (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \ + } while (0) +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \ + (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S) + + /** * @brief target -> host rate-control update indication message * @@ -16857,12 +17819,12 @@ enum htt_dbg_ext_stats_status { * to host ppdu stats indication message. * * - * |31 16|15 12|11 10|9 8|7 0 | - * |----------------------------------------------------------------------| + * |31 24|23 16|15 12|11 10|9 8|7 0 | + * |-----------------------------+-------+-------+--------+---------------| * | payload_size | rsvd |pdev_id|mac_id | msg type | - * |----------------------------------------------------------------------| - * | ppdu_id | - * |----------------------------------------------------------------------| + * |-------------+---------------+-------+-------+--------+---------------| + * | tgt_private | ppdu_id | + * |-------------+--------------------------------------------------------| * | Timestamp in us | * |----------------------------------------------------------------------| * | reserved | @@ -16902,8 +17864,9 @@ enum htt_dbg_ext_stats_status { #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16 -#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0xFFFFFFFF +#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0 +/* bits 31:24 are used by the target for internal purposes */ #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \ do { \ @@ -16934,7 +17897,7 @@ enum htt_dbg_ext_stats_status { #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \ do { \ - HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value); \ + /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \ (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \ } while (0) #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \ @@ -18113,9 +19076,11 @@ struct htt_ul_ofdma_user_info_v0 { }; #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \ - A_UINT32 w0_fw_rsvd:30; \ + A_UINT32 w0_fw_rsvd:29; \ + A_UINT32 w0_manual_ulofdma_trig:1; \ A_UINT32 w0_valid:1; \ A_UINT32 w0_version:1; + struct htt_ul_ofdma_user_info_v0_bitmap_w0 { HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 }; @@ -18136,9 +19101,9 @@ struct htt_ul_ofdma_user_info_v0_bitmap_w1 { #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \ A_UINT32 w0_fw_rsvd:27; \ - A_UINT32 w0_sub_version:3; /* set to a value of “0” on WKK/Beryllium targets (future expansion) */ \ + A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \ A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \ - A_UINT32 w0_version:1; /* set to a value of “1” to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ + A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ struct htt_ul_ofdma_user_info_v1_bitmap_w0 { HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 @@ -18205,6 +19170,9 @@ enum HTT_UL_OFDMA_TRIG_TYPE { #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0 +#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000 +#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29 + #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30 @@ -18848,6 +19816,195 @@ PREPACK struct htt_rx_peer_metadata_v1 { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \ } while (0) +/** + * @brief target -> RX PEER METADATA V1A format + * Host will know the peer metadata version from the wmi_service_ready_ext2 + * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, + * and will confirm to the target which peer metadata version to use in the + * wmi_init message. + * + * The following diagram shows the format of the RX PEER METADATA V1A format. + * + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |-------------------------------------------------------------------| + * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |-------------------------------------------------------------------| + */ +PREPACK struct htt_rx_peer_metadata_v1a { + A_UINT32 + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + logical_link_id: 4, + chip_id: 3, + reserved2: 3; +} POSTPACK; + +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13 +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000 +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S) + +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14 +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000 +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22 +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000 +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26 +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000 +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \ + } while (0) + + +/** + * @brief target -> RX PEER METADATA V1B format + * Host will know the peer metadata version from the wmi_service_ready_ext2 + * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, + * and will confirm to the target which peer metadata version to use in the + * wmi_init message. + * + * The following diagram shows the format of the RX PEER METADATA V1B format. + * + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |--------------------------------------------------------------| + * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |--------------------------------------------------------------| + */ +PREPACK struct htt_rx_peer_metadata_v1b { + A_UINT32 + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + hw_link_id: 4, + chip_id: 3, + reserved2: 3; +} POSTPACK; + +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13 +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000 +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S) + +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14 +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000 +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22 +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000 +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26 +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000 +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ + } while (0) + +/* generic variables for masks and shifts for various fields */ +extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; +extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; + +extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S; +extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M; + +/* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */ +extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); + + /* * In some systems, the host SW wants to specify priorities between * different MSDU / flow queues within the same peer-TID. @@ -19760,13 +20917,13 @@ typedef struct { * * |31 24|23 16|15 8|7 0| * |-----------------+-----------------+----------------+----------------| - * | result | response_type | vdev_id | msg_type | + * | result | response_type | pdev_id | msg_type | * |---------------------------------------------------------------------| * * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to 0x33 * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) - * b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is setup on + * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on * b'16:23 - response_type: Indicate the response type of this setup * done msg * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, @@ -19817,7 +20974,7 @@ enum htt_rx_cce_super_rule_setup_done_response_type { PREPACK struct htt_rx_cce_super_rule_setup_done_t { A_UINT8 msg_type; - A_UINT8 vdev_id; + A_UINT8 pdev_id; A_UINT8 response_type; union { struct { @@ -19839,15 +20996,15 @@ PREPACK struct htt_rx_cce_super_rule_setup_done_t { #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M 0x0000ff00 -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S 8 -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M) >> \ - HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S) -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_SET(_var, _val) \ +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S)); \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ } while (0) #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 @@ -19989,8 +21146,629 @@ typedef struct { * This CoDel MSDU queue latencies array whose location and number of * elements are specified by this HTT_T2H message consists of 16-bit elements * that each specify a statistical summary (min) of a MSDU queue's latency, - * using microseconds units. + * using milliseconds units. */ #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 + +/** + * @brief target -> host rx completion indication message definition + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND + * + * @details + * The following diagram shows the format of the Rx completion indication sent + * from the target to the host + * + * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0| + * |---------------+----------------------------+----------------| + * | vdev_id | peer_id | msg_type | + * hdr: |---------------+--------------------------+-+----------------| + * | rsvd0 |F| msdu_cnt | + * pyld: |==========================================+=+================| + * MSDU 0 | buf addr lo (bits 31:0) | + * |-----+--------------------------------------+----------------| + * |rsvd1| SW buffer cookie | buf addr hi | + * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-| + * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M| + * |-------------------------------------------------+---------+-| + * | rsvd3 | err info|E| + * |=================================================+=========+=| + * MSDU 1 | buf addr lo (bits 31:0) | + * : ... : + * | rsvd3 | err info|E| + * |-------------------------------------------------------------| + * Where: + * F = fragment + * M = MPDU retry bit + * R = raw MPDU frame + * F = first MSDU in MPDU + * L = last MSDU in MPDU + * C = MSDU continuation + * S = Souce Addr is valid + * D = Dest Addr is valid + * MC = Dest Addr is multicast / broadcast + * W = is first MSDU after WoW wakeup + * R2 = rsvd2 + * E = error valid + */ + +/* htt_t2h_rx_data_msdu_err: + * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field + * when FW forwards MSDU to host. + */ +typedef enum htt_t2h_rx_data_msdu_err { + /* ERR_DECRYPT: + * FW sets this when rxdma_error_code = . + * host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_DECRYPT = 0, + + /* ERR_TKIP_MIC: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer, sends notification to + * middleware. + */ + HTT_RXDATA_ERR_TKIP_MIC = 1, + + /* ERR_UNENCRYPTED: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_UNENCRYPTED = 2, + + /* ERR_MSDU_LIMIT: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_MSDU_LIMIT = 3, + + /* ERR_FLUSH_REQUEST: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_FLUSH_REQUEST = 4, + + /* ERR_OOR: + * FW full reorder layer maps this error to . + * Host maintains error stats, recycles buffer mainly for low + * TCP KPI debugging. + */ + HTT_RXDATA_ERR_OOR = 5, + + /* ERR_2K_JUMP: + * FW full reorder layer maps this error to . + * Host maintains error stats, recycles buffer mainly for low + * TCP KPI debugging. + */ + HTT_RXDATA_ERR_2K_JUMP = 6, + + /* ERR_ZERO_LEN_MSDU: + * FW sets this error flag for a 0 length MSDU. + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, + + /* add new error codes here */ + + HTT_RXDATA_ERR_MAX = 32 +} htt_t2h_rx_data_msdu_err_e; + +struct htt_t2h_rx_data_ind_t +{ + A_UINT32 /* word 0 */ + /* msg_type: + * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND. + */ + msg_type: 8, + peer_id: 16, /* This will provide peer data */ + vdev_id: 8; /* This will provide vdev id info */ + A_UINT32 /* word 1 */ + /* msdu_cnt: + * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message. + */ + msdu_cnt: 8, + frag: 1, /* this bit will be set for 802.11 frag MPDU */ + rsvd0: 23; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +struct htt_t2h_rx_data_msdu_info +{ + A_UINT32 /* word 0 */ + buffer_addr_low : 32; + A_UINT32 /* word 1 */ + buffer_addr_high : 8, + sw_buffer_cookie : 21, + rsvd1 : 3; + A_UINT32 /* word 2 */ + mpdu_retry_bit : 1, /* used for stats maintenance */ + raw_mpdu_frame : 1, /* used for pkt drop and processing */ + first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ + last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ + msdu_continuation : 1, /* used for MSDU scatter/gather support */ + sa_is_valid : 1, /* used for HW issue check in + * is_sa_da_idx_valid() */ + da_is_valid : 1, /* used for HW issue check and + * intra-BSS forwarding */ + da_is_mcbc : 1, + tid_info : 8, /* used for stats maintenance */ + msdu_length : 14, + is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU + * provided by fw after WoW exit */ + rsvd2 : 1; + A_UINT32 /* word 3 */ + error_valid : 1, /* Set if the MSDU has any error */ + error_info : 5, /* If error_valid is TRUE, then refer to + * "htt_t2h_rx_data_msdu_err_e" for + * checking error reason. */ + rsvd3 : 26; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words + * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead + * for every Rx DATA IND sent by FW to host. + */ +#define HTT_RX_DATA_IND_HDR_SIZE (2*4) +/* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words + * This is the size of each MSDU detail that will be piggybacked with the + * RX IND header. + */ +#define HTT_RX_DATA_MSDU_INFO_SIZE (4*4) + +/* member definitions of htt_t2h_rx_data_ind_t */ + +#define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00 +#define HTT_RX_DATA_IND_PEER_ID_S 8 + +#define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \ + (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \ + } while (0) +#define HTT_RX_DATA_IND_PEER_ID_GET(word) \ + (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S) + +#define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000 +#define HTT_RX_DATA_IND_VDEV_ID_S 24 + +#define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \ + } while (0) +#define HTT_RX_DATA_IND_VDEV_ID_GET(word) \ + (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S) + +#define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff +#define HTT_RX_DATA_IND_MSDU_CNT_S 0 + +#define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \ + (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \ + } while (0) +#define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \ + (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S) + +#define HTT_RX_DATA_IND_FRAG_M 0x00000100 +#define HTT_RX_DATA_IND_FRAG_S 8 + +#define HTT_RX_DATA_IND_FRAG_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \ + (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \ + } while (0) +#define HTT_RX_DATA_IND_FRAG_GET(word) \ + (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S) + +/* member definitions of htt_t2h_rx_data_msdu_info */ + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0 + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0 + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S) + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S) + +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00 +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8 + +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) + +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 + +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S) + +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002 +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1 + +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S) + +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004 +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2 + +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S) + +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008 +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3 + +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S) + +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010 +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4 + +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S) + +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020 +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5 + +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040 +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6 + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080 +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7 + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S) + +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00 +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8 + +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S) + +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000 +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16 + +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S) + +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000 +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30 + +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S) + +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001 +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0 + +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1 + +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) + + +/** + * @brief target -> Primary peer migration message to host + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND + * + * @details + * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target + * to host to flush & set-up the RX rings to new primary peer + * + * The message would appear as follows: + * + * |31 16|15 12|11 8|7 0| + * |-------------------------------+---------+---------+--------------| + * | vdev ID | pdev ID | chip ID | msg type | + * |-------------------------------+---------+---------+--------------| + * | ML peer ID | SW peer ID | + * |-------------------------------+----------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x37 + * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND) + * b'8:11 - chip_id: Indicate which chip has been chosen as primary + * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen + * as primary + * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen + * as primary + * + * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer + * chosen as primary + * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the + * primary peer belongs. + */ +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + chip_id: 4, /* bits 11:8 */ + pdev_id: 4, /* bits 15:12 */ + vdev_id: 16; /* bits 31:16 */ + A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ + ml_peer_id: 16; /* bits 31:16 */ +} htt_t2h_primary_link_peer_migrate_ind_t; + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + } while (0) + +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + } while (0) + +/** + * @brief target -> host rx peer AST override message defenition + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND + * + * @details + * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above + * where in the dummy ast index is provided to the host. + * This new message below is sent to the host at run time from the TX_DE + * exception path when a SAWF flow is detected for a peer. + * This is sent up once per SAWF peer. + * This layout assumes the target operates as little-endian. + * + * |31 24|23 16|15 8|7 0| + * |--------------------------------------+-----------------+-----------------| + * | SW peer ID | vdev ID | msg type | + * |-----------------+--------------------+-----------------+-----------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |-----------------+--------------------+-----------------+-----------------| + * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 | + * |--------------------------------------+-----------------+-----------------| + * | reserved | dummy AST Index #2 | + * |--------------------------------------+-----------------------------------| + * + * The following field definitions describe the format of the peer ast override + * index messages sent from the target to the host. + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as a peer map v3 message + * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND) + * - VDEV_ID + * Bits 15:8 + * Purpose: Indicates which virtual device the peer is associated with. + * - SW_PEER_ID + * Bits 31:16 + * Purpose: The peer ID (index) that WAL has allocated for this peer. + * - MAC_ADDR_L32 + * Bits 31:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: lower 4 bytes of peer node's MAC address + * - MAC_ADDR_U16 + * Bits 15:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: upper 2 bytes of peer node's MAC address + * - AST_INDEX1 + * Bits 31:16 + * Purpose: The 1st extra AST index used to identify user defined MSDUQ + * - AST_INDEX2 + * Bits 15:0 + * Purpose: The 2nd extra AST index used to identify user defined MSDUQ +*/ + +/* dword 0 */ +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000 +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16 +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00 +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8 +/* dword 1 */ +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0 +/* dword 2 */ +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0 +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000 +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16 +/* dword 3 */ +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0 + +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S) + +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S) + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S) + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S) + +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S) + + +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S) + + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */ +#define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */ +#define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */ + +#define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 + + + #endif diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h index e93a5b802876..54dd0b67c1fd 100644 --- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h +++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h @@ -876,6 +876,16 @@ typedef struct { reserved3: 31; }; }; + /* is_manual_ulofdma_trigger: + * Flag to indicate if a given UL OFDMA trigger is manually triggered + * from the Host + */ + A_UINT32 is_manual_ulofdma_trigger; + /* is_combined_ul_bsrp_trigger: + * Flag to indicate if a given UL BSRP trigger is sent combined as + * part of existing DL/UL data sequence + */ + A_UINT32 is_combined_ul_bsrp_trigger; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff @@ -2442,7 +2452,7 @@ typedef struct { /* * Max rates configured per BW: - * for BW supported by Smart Antenna - 20MHZ, 40MHZ and 80MHZ and 160MHZ + * for BW supported by Smart Antenna - 20MHZ, 40MHZ, 80MHZ and 160MHZ * (Note: 160 MHz is currently not supported by Smart Antenna) */ A_UINT32 max_rates[HTT_STATS_NUM_SUPPORTED_BW_SMART_ANTENNA]; @@ -2463,6 +2473,12 @@ typedef struct { sw_rts_failure: 1, cts_rcvd_diff_bw: 1, reserved2: 28; + + /* + * Max rates configured per BW: + * for BW supported by Smart Antenna - 320 MHZ + */ + A_UINT32 max_rates_ext; } htt_ppdu_stats_user_cmpltn_common_tlv; #define HTT_PPDU_STATS_USER_CMPLTN_BA_BITMAP_TLV_TID_NUM_M 0x000000ff diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h index f487f8550590..9db7ed503cfc 100644 --- a/drivers/staging/fw-api/fw/htt_stats.h +++ b/drivers/staging/fw-api/fw/htt_stats.h @@ -148,6 +148,7 @@ enum htt_dbg_ext_stats_type { * 6 bit htt_msdu_flow_stats_tlv * 7 bit htt_peer_sched_stats_tlv * 8 bit htt_peer_ax_ofdma_stats_tlv + * 9 bit htt_peer_be_ofdma_stats_tlv * - config_param2: [Bit31 : Bit0] mac_addr31to0 * - config_param3: [Bit15 : Bit0] mac_addr47to32 * [Bit 16] If this bit is set, reset per peer stats @@ -519,6 +520,24 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, + /** HTT_DBG_SOC_SSR_STATS + * Used for non-MLO UMAC recovery stats. + * PARAMS: + * - No Params + * RESP MSG: + * - htt_umac_ssr_stats_tlv + */ + HTT_DBG_SOC_SSR_STATS = 55, + + /** HTT_DBG_MLO_UMAC_SSR_STATS + * Used for MLO UMAC recovery stats. + * PARAMS: + * - No Params + * RESP MSG: + * - htt_mlo_umac_ssr_stats_tlv + */ + HTT_DBG_MLO_UMAC_SSR_STATS = 56, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -1858,6 +1877,7 @@ typedef enum { HTT_MSDU_FLOW_STATS_TLV = 6, HTT_PEER_SCHED_STATS_TLV = 7, HTT_PEER_AX_OFDMA_STATS_TLV = 8, + HTT_PEER_BE_OFDMA_STATS_TLV = 9, HTT_PEER_STATS_MAX_TLV = 31, } htt_peer_stats_tlv_enum; @@ -1901,8 +1921,20 @@ typedef struct { /* Last updated value of DL and UL queue depths for each peer per AC */ A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; + /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ + A_UINT32 ax_manual_ulofdma_trig_count; + A_UINT32 ax_manual_ulofdma_trig_err_count; } htt_peer_ax_ofdma_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 peer_id; + /* Per peer Manual 11be UL OFDMA trigger and trigger error counts */ + A_UINT32 be_manual_ulofdma_trig_count; + A_UINT32 be_manual_ulofdma_trig_err_count; +} htt_peer_be_ofdma_stats_tlv; + + /* config_param0 */ #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001 @@ -1992,6 +2024,7 @@ typedef struct _htt_peer_stats { htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1]; htt_peer_sched_stats_tlv peer_sched_stats; htt_peer_ax_ofdma_stats_tlv ax_ofdma_stats; + htt_peer_be_ofdma_stats_tlv be_ofdma_stats; } htt_peer_stats_t; /* =========== ACTIVE PEER LIST ========== */ @@ -2510,6 +2543,14 @@ typedef struct { A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Single-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_ax_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Single-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_ax_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Multi-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; } htt_tx_selfgen_ax_stats_tlv; typedef struct { @@ -2557,6 +2598,14 @@ typedef struct { A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; /** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Single-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_be_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Single-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_be_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Multi-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; } htt_tx_selfgen_be_stats_tlv; typedef struct { /* DEPRECATED */ @@ -6245,9 +6294,12 @@ typedef struct { */ } htt_pdev_cca_stats_hist_v1_tlv; -#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000ffff +#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000000f #define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0 +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M 0x0000fff0 +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S 4 + #define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16 @@ -6267,6 +6319,16 @@ typedef struct { ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \ } while (0) +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_GET(_var) \ + (((_var) & HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M) >> \ + HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S) + +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT, _val); \ + ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S)); \ + } while (0) + #define HTT_TWT_SESSION_FLAG_BCAST_TWT_GET(_var) \ (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \ HTT_TWT_SESSION_FLAG_BCAST_TWT_S) @@ -6972,6 +7034,7 @@ typedef enum { HTT_STATS_RC_MODE_DLMUMIMO = 1, HTT_STATS_RC_MODE_DLOFDMA = 2, HTT_STATS_RC_MODE_ULMUMIMO = 3, + HTT_STATS_RC_MODE_ULOFDMA = 4, } htt_stats_rc_mode; typedef struct { @@ -8821,4 +8884,614 @@ typedef struct { } htt_pdev_bw_mgr_stats_t; +/*============= start MLO UMAC SSR stats ============= { */ + +typedef enum { + HTT_MLO_UMAC_SSR_DBG_POINT_INVALID = 0, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_DISABLE_RXDMA_PREFETCH, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_HWMLOS, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_GLOBAL_WSI, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_DMAC, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TCL, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TQM, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_WBM, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_REO, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_HOST, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PREREQUISITES, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PRE_RING_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_APPLY_SOFT_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_POST_RING_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_FW_TQM_CMDQS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_UMAC_INTERRUPTS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_WBM, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_REO, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_DMAC, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM_SYNC_CMD, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_GLOBAL_WSI, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_HWMLOS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_ENABLE_RXDMA_PREFETCH, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TCL, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST_ENQ, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_VERIFY_UMAC_RECOVERED, + /* The below debug point values are reserved for future expansion. */ + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED28, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED29, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED30, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED31, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED32, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED33, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED34, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED35, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED36, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED37, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED38, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED39, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED40, + /* + * Due to backwards compatibility requirements, no futher DBG_POINT values + * can be added (but the above reserved values can be repurposed). + */ + HTT_MLO_UMAC_SSR_DBG_POINT_MAX, +} HTT_MLO_UMAC_SSR_DBG_POINTS; + +typedef enum { + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_INVALID = 0, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_PRE_RESET, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_START, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_COMPLETE, + /* The below recovery handshake values are reserved for future expansion. */ + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED4, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED5, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED6, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED7, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED8, + /* + * Due to backwards compatibility requirements, no futher + * RECOVERY_HANDSHAKE values can be added (but the above + * reserved values can be repurposed). + */ + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT, +} HTT_MLO_UMAC_RECOVERY_HANDSHAKES; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 start_ms; + A_UINT32 end_ms; + A_UINT32 delta_ms; + A_UINT32 reserved; + A_UINT32 footprint; /* holds a HTT_MLO_UMAC_SSR_DBG_POINTS value */ + A_UINT32 tqm_hw_tstamp; +} htt_mlo_umac_ssr_dbg_tlv; + +typedef struct { + A_UINT32 last_mlo_htt_handshake_delta_ms; + A_UINT32 max_mlo_htt_handshake_delta_ms; + union { + A_UINT32 umac_recovery_done_mask; + struct { + A_UINT32 pre_reset_disable_rxdma_prefetch : 1, + pre_reset_pmacs_hwmlos : 1, + pre_reset_global_wsi : 1, + pre_reset_pmacs_dmac : 1, + pre_reset_tcl : 1, + pre_reset_tqm : 1, + pre_reset_wbm : 1, + pre_reset_reo : 1, + pre_reset_host : 1, + reset_prerequisites : 1, + reset_pre_ring_reset : 1, + reset_apply_soft_reset : 1, + reset_post_ring_reset : 1, + reset_fw_tqm_cmdqs : 1, + post_reset_host : 1, + post_reset_umac_interrupts : 1, + post_reset_wbm : 1, + post_reset_reo : 1, + post_reset_tqm : 1, + post_reset_pmacs_dmac : 1, + post_reset_tqm_sync_cmd : 1, + post_reset_global_wsi : 1, + post_reset_pmacs_hwmlos : 1, + post_reset_enable_rxdma_prefetch : 1, + post_reset_tcl : 1, + post_reset_host_enq : 1, + post_reset_verify_umac_recovered : 1, + reserved : 5; + } done_mask; + }; +} htt_mlo_umac_ssr_mlo_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_mlo_stats_t mlo; +} htt_mlo_umac_ssr_mlo_stats_tlv; + +/* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S));\ + } while (0) + +/* dword0 - b'1 - PRE_RESET_PMACS_HWMLOS */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M 0x2 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S 1 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S));\ + } while (0) + +/* dword0 - b'2 - PRE_RESET_GLOBAL_WSI */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M 0x4 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S 2 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S));\ + } while (0) + +/* dword0 - b'3 - PRE_RESET_PMACS_DMAC */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M 0x8 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S 3 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S));\ + } while (0) + +/* dword0 - b'4 - PRE_RESET_TCL */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M 0x10 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S 4 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S));\ + } while (0) + +/* dword0 - b'5 - PRE_RESET_TQM */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M 0x20 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S 5 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S));\ + } while (0) + +/* dword0 - b'6 - PRE_RESET_WBM */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M 0x40 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S 6 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S));\ + } while (0) + +/* dword0 - b'7 - PRE_RESET_REO */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M 0x80 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S 7 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S));\ + } while (0) + +/* dword0 - b'8 - PRE_RESET_HOST */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M 0x100 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S 8 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S));\ + } while (0) + +/* dword0 - b'9 - RESET_PREREQUISITES */ +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M 0x200 +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S 9 +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S));\ + } while (0) + +/* dword0 - b'10 - RESET_PRE_RING_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M 0x400 +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S 10 +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S));\ + } while (0) + +/* dword0 - b'11 - RESET_APPLY_SOFT_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M 0x800 +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S 11 +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S));\ + } while (0) + +/* dword0 - b'12 - RESET_POST_RING_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M 0x1000 +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S 12 +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S));\ + } while (0) + +/* dword0 - b'13 - RESET_FW_TQM_CMDQS */ +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M 0x2000 +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S 13 +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S));\ + } while (0) + +/* dword0 - b'14 - POST_RESET_HOST */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M 0x4000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S 14 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S));\ + } while (0) + +/* dword0 - b'15 - POST_RESET_UMAC_INTERRUPTS */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M 0x8000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S 15 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S));\ + } while (0) + +/* dword0 - b'16 - POST_RESET_WBM */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M 0x10000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S 16 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S));\ + } while (0) + +/* dword0 - b'17 - POST_RESET_REO */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M 0x20000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S 17 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S));\ + } while (0) + +/* dword0 - b'18 - POST_RESET_TQM */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M 0x40000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S 18 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S));\ + } while (0) + +/* dword0 - b'19 - POST_RESET_PMACS_DMAC */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M 0x80000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S 19 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S));\ + } while (0) + +/* dword0 - b'20 - POST_RESET_TQM_SYNC_CMD */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M 0x100000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S 20 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S));\ + } while (0) + +/* dword0 - b'21 - POST_RESET_GLOBAL_WSI */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M 0x200000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S 21 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S));\ + } while (0) + +/* dword0 - b'22 - POST_RESET_PMACS_HWMLOS */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M 0x400000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S 22 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S));\ + } while (0) + +/* dword0 - b'23 - POST_RESET_ENABLE_RXDMA_PREFETCH */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M 0x800000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S 23 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S));\ + } while (0) + +/* dword0 - b'24 - POST_RESET_TCL */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M 0x1000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S 24 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S));\ + } while (0) + +/* dword0 - b'25 - POST_RESET_HOST_ENQ */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M 0x2000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S 25 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S));\ + } while (0) + +/* dword0 - b'26 - POST_RESET_VERIFY_UMAC_RECOVERED */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M 0x4000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S 26 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S));\ + } while (0) + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 last_trigger_request_ms; + A_UINT32 last_start_ms; + A_UINT32 last_start_disengage_umac_ms; + A_UINT32 last_enter_ssr_platform_thread_ms; + A_UINT32 last_exit_ssr_platform_thread_ms; + A_UINT32 last_start_engage_umac_ms; + A_UINT32 last_done_successful_ms; + A_UINT32 post_reset_tqm_sync_cmd_completion_ms; + A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; + A_UINT32 htt_sync_do_pre_reset_ms; + A_UINT32 htt_sync_do_post_reset_start_ms; + A_UINT32 htt_sync_do_post_reset_complete_ms; +} htt_mlo_umac_ssr_kpi_tstamp_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 htt_sync_start_ms; + A_UINT32 htt_sync_delta_ms; + A_UINT32 post_t2h_start_ms; + A_UINT32 post_t2h_delta_ms; + A_UINT32 post_t2h_msg_read_shmem_ms; + A_UINT32 post_t2h_msg_write_shmem_ms; + A_UINT32 post_t2h_msg_send_msg_to_host_ms; +} htt_mlo_umac_htt_handshake_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element of each of the arrays in + * this struct to determine where the subsequent item resides. + */ + htt_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX]; + htt_mlo_umac_htt_handshake_stats_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT]; +} htt_mlo_umac_ssr_kpi_delta_stats_t; + +typedef struct { + /* + * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own + * TLV header, and since no additional fields are added in this struct + * beyond the htt_mlo_umac_ssr_kpi_delta_stats_t info, no additional + * TLV header is needed. + * + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each item inside the + * htt_mlo_umac_ssr_kpi_delta_stats_t to determine where the subsequent + * item resides. + */ + htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta; +} htt_mlo_umac_ssr_kpi_delta_stats_tlv; + +typedef struct { + A_UINT32 last_e2e_delta_ms; + A_UINT32 max_e2e_delta_ms; + A_UINT32 per_handshake_max_allowed_delta_ms; + /* Total done count */ + A_UINT32 total_success_runs_cnt; + A_UINT32 umac_recovery_in_progress; + /* Count of Disengaged in Pre reset */ + A_UINT32 umac_disengaged_count; + /* Count of UMAC Soft/Control Reset */ + A_UINT32 umac_soft_reset_count; + /* Count of Engaged in Post reset */ + A_UINT32 umac_engaged_count; +} htt_mlo_umac_ssr_common_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_common_stats_t cmn; +} htt_mlo_umac_ssr_common_stats_tlv; + +typedef struct { + A_UINT32 trigger_requests_count; + A_UINT32 trigger_count_for_umac_hang; + A_UINT32 trigger_count_for_mlo_target_recovery_mode1; + A_UINT32 trigger_count_for_unknown_signature; + A_UINT32 total_trig_dropped; + A_UINT32 trigger_count_for_unit_test_direct_trigger; + A_UINT32 trigger_count_for_tx_de_wdg_dummy_frame_tout; + A_UINT32 trigger_count_for_peer_delete_wdg_dummy_frame_tout; + A_UINT32 trigger_count_for_reo_hang; + A_UINT32 trigger_count_for_tqm_hang; + A_UINT32 trigger_count_for_tcl_hang; + A_UINT32 trigger_count_for_wbm_hang; +} htt_mlo_umac_ssr_trigger_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_trigger_stats_t trigger; +} htt_mlo_umac_ssr_trigger_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element to determine where the + * subsequent element resides. + */ + htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv; + htt_mlo_umac_ssr_kpi_tstamp_stats_tlv kpi_tstamp_tlv; +} htt_mlo_umac_ssr_kpi_stats_t; + +typedef struct { + /* + * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv + * has its own TLV header, and since no additional fields are added in + * this struct beyond the htt_mlo_umac_ssr_kpi_stats_t info, no additional + * TLV header is needed. + * + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within the htt_mlo_umac_ssr_kpi_stats_t sub-struct + * to determine how much data is present for this struct. + */ + htt_mlo_umac_ssr_kpi_stats_t kpi; +} htt_mlo_umac_ssr_kpi_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element to determine where the + * subsequent element resides. + */ + htt_mlo_umac_ssr_trigger_stats_tlv trigger_tlv; + htt_mlo_umac_ssr_kpi_stats_tlv kpi_tlv; + htt_mlo_umac_ssr_mlo_stats_tlv mlo_tlv; + htt_mlo_umac_ssr_common_stats_tlv cmn_tlv; +} htt_mlo_umac_ssr_stats_tlv; + +/*============= end MLO UMAC SSR stats ============= } */ + +typedef struct { + A_UINT32 total_done; + A_UINT32 trigger_requests_count; + A_UINT32 total_trig_dropped; + A_UINT32 umac_disengaged_count; + A_UINT32 umac_soft_reset_count; + A_UINT32 umac_engaged_count; + A_UINT32 last_trigger_request_ms; + A_UINT32 last_start_ms; + A_UINT32 last_start_disengage_umac_ms; + A_UINT32 last_enter_ssr_platform_thread_ms; + A_UINT32 last_exit_ssr_platform_thread_ms; + A_UINT32 last_start_engage_umac_ms; + A_UINT32 last_done_successful_ms; + A_UINT32 last_e2e_delta_ms; + A_UINT32 max_e2e_delta_ms; + A_UINT32 trigger_count_for_umac_hang; + A_UINT32 trigger_count_for_mlo_quick_ssr; + A_UINT32 trigger_count_for_unknown_signature; + A_UINT32 post_reset_tqm_sync_cmd_completion_ms; + A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; + A_UINT32 htt_sync_do_pre_reset_ms; + A_UINT32 htt_sync_do_post_reset_start_ms; + A_UINT32 htt_sync_do_post_reset_complete_ms; +} htt_umac_ssr_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_umac_ssr_stats_t stats; +} htt_umac_ssr_stats_tlv; + + #endif /* __HTT_STATS_H__ */ diff --git a/drivers/staging/fw-api/fw/wlan_defs.h b/drivers/staging/fw-api/fw/wlan_defs.h index 35018ed69bbf..20657baf496e 100755 --- a/drivers/staging/fw-api/fw/wlan_defs.h +++ b/drivers/staging/fw-api/fw/wlan_defs.h @@ -149,7 +149,7 @@ typedef enum { MODE_11AX_HE80_2G = 23, #endif -#if defined(SUPPORT_11BE) && SUPPORT_11BE +#if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) MODE_11BE_EHT20 = 24, MODE_11BE_EHT40 = 25, MODE_11BE_EHT80 = 26, @@ -248,7 +248,7 @@ typedef enum { ((mode) == MODE_11AX_HE80_2G)) #endif /* SUPPORT_11AX */ -#if defined(SUPPORT_11BE) && SUPPORT_11BE +#if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) #define IS_MODE_EHT(mode) (((mode) == MODE_11BE_EHT20) || \ ((mode) == MODE_11BE_EHT40) || \ ((mode) == MODE_11BE_EHT80) || \ @@ -1763,11 +1763,17 @@ A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, (((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); /** Helper macro for params GET/SET of mlo_glb_chip_crash_info */ -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 0, 2) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 0, 2, value) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) \ + (MLO_SHMEM_GET_BITS(chip_info, 0, 2) + \ + (MLO_SHMEM_GET_BITS(chip_info, 12, 4) << 2)) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) \ + do { \ + MLO_SHMEM_SET_BITS(chip_info, 0, 2, ((value) & 0x03)); \ + MLO_SHMEM_SET_BITS(chip_info, 12, 4, ((value) >> 2)); \ +} while (0) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 3) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 3, value) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 8) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 8, value) typedef struct { /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ @@ -1778,7 +1784,18 @@ typedef struct { * * [1:0]: no_of_chips * [4:2]: valid_chip_bmap - * [31:6]: reserved + * For number of chips beyond 3, extension fields are added. + * To maintain backward compatibility, with 3 chip board and + * old host driver, valid chip bmap is extended in continuation from + * existing bit 4 onwards, while extending no_of_chips information + * would overlap with old valid_chip_bmap, hence extended from + * bit 12:15. Now no_of_chip will have two parts, lower 2 bits from 0-1 and + * upper 4 bits from 12-15. SET-GET macros are modified accordingly. + * This helps in no change in respective processing files and don't need + * to maintain two copy of information for backward compatibility. + * [9:5]: valid_chip_bmap_ext + * [15:12]: no_of_chips_ext + * [31:16]: reserved */ A_UINT32 chip_info; /* This TLV is followed by array of mlo_glb_per_chip_crash_info: diff --git a/drivers/staging/fw-api/fw/wlan_module_ids.h b/drivers/staging/fw-api/fw/wlan_module_ids.h index 188b0b0bb6b5..255a656be795 100644 --- a/drivers/staging/fw-api/fw/wlan_module_ids.h +++ b/drivers/staging/fw-api/fw/wlan_module_ids.h @@ -151,6 +151,7 @@ typedef enum { WLAN_MODULE_SCHED_ALGO_SAWF, /* 0x6f */ WLAN_MODULE_BAR, /* 0x70 */ WLAN_MODULE_SMART_TX, /* 0x71 */ + WLAN_MODULE_BRIDGE_PEER, /* 0x72 */ WLAN_MODULE_ID_MAX, diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h index 64e88aab7a7b..ae770417017e 100644 --- a/drivers/staging/fw-api/fw/wmi_services.h +++ b/drivers/staging/fw-api/fw/wmi_services.h @@ -611,6 +611,23 @@ typedef enum { WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */ WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */ WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */ + WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ + WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */ + WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */ + WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS = 364, /* Suppport roam between DBS(2G+5G/6G) to HBS(5G+6G) with self AP MLD. */ + WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ + WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */ + WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */ + WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */ + WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */ + WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */ + WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */ + WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */ + WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */ + WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */ + WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */ + WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */ + WMI_SERVICE_AUX_MAC_SUPPORT = 377, WMI_MAX_EXT2_SERVICE diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h index e7b0b5fe53cc..f880d7ca08d3 100644 --- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h +++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h @@ -1120,11 +1120,23 @@ typedef enum { WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_complete_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param = + WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param = + WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param = + WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_roam_msg_info_tlv_param, WMITLV_TAG_STRUC_wmi_vdev_set_tpc_power_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_ch_power_info, @@ -1342,8 +1354,28 @@ typedef enum { WMITLV_TAG_STRUC_wmi_peer_preferred_link_map, WMITLV_TAG_STRUC_wmi_scan_blanking_params_info, WMITLV_TAG_STRUC_wmi_peer_list, + WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct, + WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info, + WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_peer_link_control_param, + WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data, + WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_blanking_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_cca_busy_subband_info, + WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct, + WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, } WMITLV_TAG_ID; - /* * IMPORTANT: Please add _ALL_ WMI Commands Here. * Otherwise, these WMI TLV Functions will be process them. @@ -1862,6 +1894,16 @@ typedef enum { OP(WMI_HPA_CMDID) \ OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \ OP(WMI_PEER_BULK_SET_CMDID) \ + OP(WMI_MLO_VDEV_GET_LINK_INFO_CMDID) \ + OP(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID) \ + OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \ + OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \ + OP(WMI_PDEV_SET_RF_PATH_CMDID) \ + OP(WMI_VDEV_PAUSE_CMDID) \ + OP(WMI_GPIO_STATE_REQ_CMDID) \ + OP(WMI_VENDOR_PDEV_CMDID) \ + OP(WMI_VENDOR_VDEV_CMDID) \ + OP(WMI_VENDOR_PEER_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2162,6 +2204,16 @@ typedef enum { OP(WMI_TAS_POWER_HISTORY_EVENTID) \ OP(WMI_HPA_EVENTID) \ OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \ + OP(WMI_CSA_IE_RECEIVED_EVENTID) \ + OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \ + OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \ + OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \ + OP(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID) \ + OP(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID) \ + OP(WMI_GPIO_STATE_RES_EVENTID) \ + OP(WMI_VENDOR_PDEV_EVENTID) \ + OP(WMI_VENDOR_VDEV_EVENTID) \ + OP(WMI_VENDOR_PEER_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -2997,6 +3049,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_CONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, wmi_gpio_output_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_OUTPUT_CMDID); +/* GPIO State Req Cmd */ +#define WMITLV_TABLE_WMI_GPIO_STATE_REQ_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, wmi_gpio_state_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_REQ_CMDID); + /* Antenna Controller config Cmd */ #define WMITLV_TABLE_WMI_ANT_CONTROLLER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param, wmi_ant_controller_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -3518,7 +3575,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_PEER_UPDATE_CMDID); /* Enable/Disable TDLS Offchannel Cmd */ #define WMITLV_TABLE_WMI_TDLS_SET_OFFCHAN_MODE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, \ - wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, peer_chan_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_SET_OFFCHAN_MODE_CMDID); @@ -4530,7 +4588,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_PEER_STATS_INFO_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, twt_dialog_ids, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, peer_ids, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID); /* Request Halphy Stats through Ctrl Path */ @@ -5081,7 +5140,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_TEARDOWN_CMDID); #define WMITLV_TABLE_WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param, wmi_peer_tid_to_link_map_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_link_control_param, mlo_peer_link_control_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID); /** WMI cmd used to setup Tid to Link Mapping for a vdev */ @@ -5292,6 +5352,48 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HPA_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, r2p_array, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); +#define WMITLV_TABLE_WMI_MLO_VDEV_GET_LINK_INFO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, wmi_mlo_vdev_get_link_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); + +/* WMI command to set Manual SU UL OFDMA Trigger params */ +#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, wmi_vdev_set_manual_su_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); + +/* WMI command to set Manual MU UL OFDMA Trigger params */ +#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, wmi_vdev_set_manual_mu_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); + +/* Standalone Sound Cmd */ +#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, wmi_standalone_sounding_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_list, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_CMDID); + +/* WMI cmd to set RF path for PHY */ +#define WMITLV_TABLE_WMI_PDEV_SET_RF_PATH_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, wmi_pdev_set_rf_path_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_CMDID); + +/* VDEV PAUSE cmd */ +#define WMITLV_TABLE_WMI_VDEV_PAUSE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, wmi_vdev_pause_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PAUSE_CMDID); + +/* pdev,vdev,peer cmd messages for tunneling vendor-specific contents */ +#define WMITLV_TABLE_WMI_VENDOR_PDEV_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, wmi_pdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_CMDID); +#define WMITLV_TABLE_WMI_VENDOR_VDEV_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, wmi_vdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_CMDID); +#define WMITLV_TABLE_WMI_VENDOR_PEER_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -5473,7 +5575,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TX_POWER_EVENTID); /* Channel Info Event */ #define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cca_busy_subband_info, cca_busy_subband_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID); /* RSSI dB to dBm conversion params info event to host */ @@ -5709,6 +5812,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MUEDCA_PARAMS_CONFIG_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_INPUT_EVENTID); +/* GPIO State Res Event */ +#define WMITLV_TABLE_WMI_GPIO_STATE_RES_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, wmi_gpio_state_res_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_RES_EVENTID); + /* CSA Handling Event */ #define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -6727,7 +6835,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* @@ -6802,7 +6913,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID); #define WMITLV_TABLE_WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID); /* ctl failsafe check event */ @@ -7175,6 +7287,49 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HPA_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, wmi_pdev_set_tgtr2p_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID); +/* CSA IE Received Event */ +#define WMITLV_TABLE_WMI_CSA_IE_RECEIVED_EVENTID(id,op,buf,len)\ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CSA_IE_RECEIVED_EVENTID); + +#define WMITLV_TABLE_WMI_MLO_VDEV_LINK_INFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, wmi_mlo_vdev_link_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_vdev_link_info, mlo_vdev_link_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_LINK_INFO_EVENTID); + +/* Manual UL OFDMA Trigger Feedback Event */ +#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID); + +/* WMI standalone sound complete event */ +#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, wmi_standalone_sounding_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snd_failed, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID); + +/* Manual UL OFDMA Trigger RX PPDU Per user info Event */ +#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_manual_ul_ofdma_trig_rx_peer_userinfo, rx_peer_userinfo, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID); + +/* MLO_LINK_DISABLE_REQUEST Event */ +#define WMITLV_TABLE_WMI_MLO_LINK_DISABLE_REQUEST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, wmi_mlo_link_disable_request_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID); + +/* pdev,vdev,peer event messages for tunneling vendor-specific contents */ +#define WMITLV_TABLE_WMI_VENDOR_PDEV_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, wmi_pdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_EVENTID); +#define WMITLV_TABLE_WMI_VENDOR_VDEV_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, wmi_vdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID); +#define WMITLV_TABLE_WMI_VENDOR_PEER_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); #ifdef __cplusplus diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h index 72344c72d419..536fdfd966ec 100644 --- a/drivers/staging/fw-api/fw/wmi_unified.h +++ b/drivers/staging/fw-api/fw/wmi_unified.h @@ -316,6 +316,7 @@ typedef enum { WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */ WMI_GRP_ODD, /* 0x4b ODD */ WMI_GRP_TDMA, /* 0x4c TDMA */ + WMI_GRP_MANUAL_UL_TRIG /* 0x4d Manual UL OFDMA Trigger */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -517,6 +518,9 @@ typedef enum { WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID, /* WMI cmd to set Target rate to power table */ WMI_PDEV_SET_TGTR2P_TABLE_CMDID, + /* WMI cmd to set RF path for PHY */ + WMI_PDEV_SET_RF_PATH_CMDID, + /* VDEV (virtual device) specific commands */ /** vdev create */ @@ -624,6 +628,9 @@ typedef enum { /** Enable SR prohibit feature for TIDs of vdev */ WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID, + /** pause vdev's Tx, Rx, or both for a specific duration */ + WMI_VDEV_PAUSE_CMDID, + /* peer specific commands */ /** create a peer */ @@ -1229,6 +1236,9 @@ typedef enum { /* H2T HPA message */ WMI_HPA_CMDID, + /* WMI comamnd for standalone sounding */ + WMI_VDEV_STANDALONE_SOUND_CMDID, + /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), /* invoke neighbor report from FW */ @@ -1244,6 +1254,8 @@ typedef enum { /* Antenna Controller, connected to wlan debug uart/GPIO. */ WMI_ANT_CONTROLLER_CMDID, + WMI_GPIO_STATE_REQ_CMDID, + /* FWTEST Commands */ WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_FWTEST), /** set NoA descs **/ @@ -1549,6 +1561,8 @@ typedef enum { WMI_MLO_LINK_REMOVAL_CMDID, /** WMI cmd used to setup Tid to Link Mapping for a MLO VAP */ WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID, + /** WMI cmd used to get mlo link information */ + WMI_MLO_VDEV_GET_LINK_INFO_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -1561,6 +1575,13 @@ typedef enum { /* WMI commands specific to TDMA */ WMI_TDMA_SCHEDULE_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDMA), + + /* WMI commands specific to manually-triggered UL */ + /** WMI Command to set Manual SU UL OFDMA trigger parameters */ + WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), + + /** WMI Command to set Manual MU UL OFDMA trigger parameters */ + WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID, } WMI_CMD_ID; typedef enum { @@ -2071,8 +2092,11 @@ typedef enum { /** GTK offload failed to rekey event */ WMI_GTK_REKEY_FAIL_EVENTID, - /* CSA IE received event */ + + /* CSA handling event */ WMI_CSA_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL), + /* CSA IE received event */ + WMI_CSA_IE_RECEIVED_EVENTID, /*chatter query reply event*/ WMI_CHATTER_PC_QUERY_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHATTER), @@ -2194,6 +2218,9 @@ typedef enum { /* T2H HPA message */ WMI_HPA_EVENTID, + /* WMI standalone command complete Event */ + WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID, + /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), @@ -2212,6 +2239,8 @@ typedef enum { /* Smart Antenna Controller status */ WMI_SMARTANT_STATE_CHANGE_EVENTID, + WMI_GPIO_STATE_RES_EVENTID, + /* TDLS Event */ WMI_TDLS_PEER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TDLS), @@ -2362,12 +2391,26 @@ typedef enum { WMI_MLO_LINK_REMOVAL_EVENTID, /* Response event for WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID */ WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID, + /* Response event for WMI_MLO_VDEV_GET_LINK_INFO_CMDID */ + WMI_MLO_VDEV_LINK_INFO_EVENTID, + /** request host to do T2LM neg to the un-disabled link */ + WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), /* ODD events */ WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ODD), + + /** WMI events specific to manually-triggered UL */ + /** + * WMI Event to send Manual UL OFDMA Trigger frame status feedback to Host + */ + WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), + /** + * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host + */ + WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID, } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -4398,8 +4441,20 @@ typedef struct { * 1 -> disable wds_mec_intrabss offload * Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_GET / * SET macros. + * Bit 16 - latency_flowq_support + * Flag to indicate whether host supports latency tolerant queue. + * By default, it is disabled. + * 0 -> disable latency_flowq_support + * 1 -> enable latency_flowq_support + * Refer to WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET/SET macros. + * Bit 17 - rf_path_mode + * Flag to indicate overlapping_freq_mode + * By default, it will be primary mode (0) + * 0 - Primary + * 1 - Secondary + * Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros. * - * Bits 31:16 - Reserved + * Bits 31:18 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -4843,6 +4898,16 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_SET(flags2, value) \ WMI_SET_BITS(flags2, 15, 1, value) +#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET(flags2) \ + WMI_GET_BITS(flags2, 16, 1) +#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_SET(flags2, value) \ + WMI_SET_BITS(flags2, 16, 1, value) + +#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET(flags2) \ + WMI_GET_BITS(flags2, 17, 1) +#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \ + WMI_SET_BITS(flags2, 17, 1, value) + #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) @@ -5633,6 +5698,12 @@ typedef struct { #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 +/** pause home channel when scan channel is same as home channel */ +#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x200000 +/** + * report CCA busy for each possible 20Mhz subbands of the wideband scan channel + */ +#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x400000 /** for adaptive scan mode using 3 bits (21 - 23 bits) */ #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 @@ -5741,6 +5812,11 @@ typedef enum { /* Include MLO IE in Probe req */ #define WMI_SCAN_FLAG_EXT_INCL_MLIE_PRB_REQ 0x00004000 +#define WMI_SCAN_FLAG_EXT_LOW_LATENCY_SCAN 0x00008000 +#define WMI_SCAN_FLAG_EXT_RELIABLE_SCAN 0x00010000 +#define WMI_SCAN_FLAG_EXT_FAST_SCAN 0x00020000 +#define WMI_SCAN_FLAG_EXT_LOW_POWER_SCAN 0x00040000 + /** * new 6 GHz flags per chan (short ssid or bssid) in struct @@ -7144,6 +7220,13 @@ typedef struct { A_UINT32 value; } wmi_echo_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag would be equivalent to WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param */ + /** AP MLD address request to be disabled some set of link */ + wmi_mac_addr mld_addr; + /** Request link id set to disable */ + A_UINT32 linkid_bitmap; +} wmi_mlo_link_disable_request_event_fixed_param; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param */ @@ -9020,6 +9103,24 @@ typedef enum { * Based on the received input, the scan blanking feature will be carried out as explained in the enum WMI_SCAN_BLANKING_MODE */ WMI_PDEV_PARAM_SET_SCAN_BLANKING_MODE, + + /* + * Parameter to enable/disable Multi-Channel Concurrency low latency mode + * bit | config_mode + * ----------------- + * 0 | 0:disable, 1:enable. + * 1-31 | Reserved. + */ + WMI_PDEV_PARAM_SET_CONC_LOW_LATENCY_MODE, + + /* + * Parameter to enable/disable low power listen mode + * bit | config_mode + * ----------------- + * 0 | 0:disable, 1:enable. + * 1-31 | Reserved. + */ + WMI_PDEV_PARAM_LPL_SETTING, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -9220,6 +9321,7 @@ typedef enum { WMI_HALPHY_TPC_STATS_SUPPORT_AX_EXTRA_MCS, WMI_HALPHY_TPC_STATS_SUPPORT_BE, WMI_HALPHY_TPC_STATS_SUPPORT_BE_PUNC, + WMI_HALPHY_TPC_STATS_SUPPORT_CTL_DESIGN_1, } WMI_HALPHY_TPC_STATS_SUPPORT_BITF; /* support bit fields */ typedef struct { @@ -9270,6 +9372,7 @@ typedef struct { * Refer to enum WMI_HALPHY_TPC_STATS_SUPPORT_BITF. */ A_UINT32 support_bits; + A_UINT32 nss; /* target specific NUM_SPATIAL_STREAM flag */ } wmi_tpc_configs; typedef struct { @@ -10450,6 +10553,35 @@ typedef struct { #define WMI_VDEV_ID_INFO_GET_VALIDATE(vdev_id_info) WMI_GET_BITS(vdev_id_info, 31, 1) #define WMI_VDEV_ID_INFO_SET_VALIDATE(vdev_id_info, value) WMI_SET_BITS(vdev_id_info, 31, 1, value) +typedef struct { + union { + struct { + A_UINT32 + id: 8, /* the vdev ID */ + /* validate: + * validate bit, the vdev ID (id and link_status) is only valid + * if this bit set as 1. + */ + validate: 1, + /* link_status: + * 0 -> link inactive + * 1 -> link active + */ + link_status: 1, + reserved:22; + }; + A_UINT32 vdev_info_word0; + }; +} wmi_vdev_id_info_v2; + +#define WMI_VDEV_ID_INFO_V2_GET_VDEV_ID(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 0, 8) +#define WMI_VDEV_ID_INFO_V2_SET_VDEV_ID(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 0, 8, value) +#define WMI_VDEV_ID_INFO_V2_GET_VALIDATE(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 8, 1) +#define WMI_VDEV_ID_INFO_V2_SET_VALIDATE(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 8, 1, value) +#define WMI_VDEV_ID_INFO_V2_GET_LINK_STATUS(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 9, 1) +#define WMI_VDEV_ID_INFO_V2_SET_LINK_STATUS(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 9, 1, value) + + /* * Each step represents 0.5 dB. The starting value is 0 dBm. * Thus the TPC levels cover 0 dBm to 31.5 dBm inclusive in 0.5 dB steps. @@ -11013,6 +11145,8 @@ typedef struct { A_UINT32 num_mib_extd_stats; /** Indicates the vdev id of the stats for MLO stats query */ wmi_vdev_id_info vdev_id_info; + /** Indicates the vdev id of the stats for MLO stats query v2 */ + wmi_vdev_id_info_v2 vdev_id_info_v2; /* This TLV is followed by another TLV of array of bytes * A_UINT8 data[]; @@ -11687,8 +11821,539 @@ typedef struct { A_UINT32 qos_null_tx_send_compl_over_wmi; /** total event alloc failure count for qos null tx send */ A_UINT32 qos_null_tx_send_event_alloc_failed; + + /** wlan_pdev fields num_macs, vdev_up_count and vdev_active_count + * num_macs_phy_vdev_up_active: + * This word contains the following bitfields: + * number of macs from wlan_pdev + * (WMI_PDEV_STATS_NUM_MACS_SET,GET) + * number of vdev up count + * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) + * number of vdev active count + * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) + */ + A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; + /** refer wlan_pdev ic flags */ + A_UINT32 opaque_debug_ic_flags; + /** vdev_id that are paused per pdev */ + A_UINT32 opaque_debug_paused_ap_vdev_bitmap; + /** opaque_debug_flags: + * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT + */ + A_UINT32 opaque_debug_flags; + /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G + * remote_peer_cnt_max_rf_chains_2G_5G: + * This word contains the following bitfields: + * max chains supported in the 2.4 GHz band + * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) + * max chains supported in the 5 GHz band, + * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) + * number of remote peers + * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) + */ + A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; + /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ + A_UINT32 opaque_debug_max_ht_cap_info; + /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ + A_UINT32 opaque_debug_max_vht_cap_info; + /** opaque_debug_max_vht_supp_mcs: + * wlan_pdev max VHT Supported MCS which is + * vht_supp_mcs_2G or vht_supp_mcs_5G + */ + A_UINT32 opaque_debug_max_vht_supp_mcs; + /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ + A_UINT32 opaque_debug_max_he_cap_info; + A_UINT32 opaque_debug_max_he_cap_info_ext; + /** the nominal chain mask for transmit */ + A_UINT32 opaque_debug_tx_chain_mask; + /** the nominal chain mask for receive */ + A_UINT32 opaque_debug_rx_chain_mask; + /** opaque_debug_ema_flags: + * This word contains the following bitfields: + * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev + * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both + * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) + * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) + * ema_max_profile_period - maximum profile periodicity + * (maximum number of beacons after which VAP profiles repeat) + * for any EMA VAP on any pdev. + * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) + */ + A_UINT32 opaque_debug_ema_flags; + /** wlan_pdev - maximum ML peers supported */ + A_UINT32 opaque_debug_num_ml_peer_entries; + /** This word contains the following bitfields: + * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips + * (related to MLO) + * Max number of HW links + * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) + * Current Chip Id + * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) + * Max number of chips + * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) + */ + A_UINT32 opaque_debug_mlo_flags; + /** Indicate beacon size in bytes */ + A_UINT32 opaque_debug_large_bcn_size; + /** proposed by the host value of MSDUQs per each LinkView peer's TID */ + A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; + /** bcn_filter_context variables */ + A_UINT32 opaque_debug_bcns_dropped; + A_UINT32 opaque_debug_bcns_recvd; + A_UINT32 opaque_debug_bcns_delivered; + /** Tids that are paused/unpaused based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; + /** Tids that are blocked/unblocked based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; + /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ + A_UINT32 opaque_debug_rx_filter; + /** This word contains the following bitfields: + * aggr_nonaggr_retry_th: + * wal_pdev fields - agg_retry_th and non_agg_retry_th + * This value holds max retry threshold up to which a Data packet + * will be retried when ack is not received. + * agg_retry_th - Threshold value used when aggregation is enabled + * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) + * non_agg_retry_th - Threshold value used for non-aggregation. + * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) + */ + A_UINT32 opaque_debug_aggr_nonaggr_retry_th; + /** This word contains the following bitfields: + * num_max_rx_ba_sessions: + * Number of rx BA session establised + * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) + * Max number of rx BA session from wal_pdev + * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) + */ + A_UINT32 opaque_debug_num_max_rx_ba_sessions; + /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ + A_UINT32 opaque_debug_chan_switch_flags; + /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ + A_UINT32 opaque_debug_consecutive_failure_reset_cause; + /** PPDU duration limit, in us */ + A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; + /** pdev reset in progress */ + A_UINT32 opaque_debug_reset_in_progress; + /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ + A_UINT32 opaque_debug_vdev_migrate_state; + /** opaque_debug_rts_rc_flag: + * wal_pdev rts ratecode - this value reflects whatever + * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. + */ + A_UINT32 opaque_debug_rts_rc_flag; + /* Num of peer delete in progress */ + A_UINT32 opaque_debug_num_of_peer_delete_in_progress; + /** wal_pdev total number of active vdev count */ + A_UINT32 opaque_debug_total_active_vdev_cnt; + /** wal_pdev - max number of vdevs per pdev */ + A_UINT32 opaque_debug_max_vdevs; + /* NonOccupancyList(NOL) context */ + A_UINT32 opaque_debug_dfs_nol_count; + /** NOL timeout in seconds */ + A_UINT32 opaque_debug_dfs_nol_timeout; + A_UINT32 opaque_debug_dfs_use_nol; + /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ + A_UINT32 opaque_debug_cac_mode; + A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ + /** This word contains the following bitfields: + * wal_pdev home channel info + * home_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) + */ + A_UINT32 opaque_debug_home_chan_mhz_flags; + /** home channel center frequency in MHz */ + A_UINT32 opaque_debug_home_band_center_freq; + /** home channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_home_phy_mode; + /** This word contains the following bitfields: + * wal_pdev current channel info + * cur_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) + */ + A_UINT32 opaque_debug_cur_chan_mhz_flags; + /** current channel center frequency in MHz */ + A_UINT32 opaque_debug_cur_band_center_freq; + /** current channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_cur_phy_mode; + /* Beacon context info */ + A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; + /** beacon queue AIFS */ + A_UINT32 opaque_debug_aifs; + /** beacon queue cwmin */ + A_UINT32 opaque_debug_cwmin; + /** beacon queue cwmax */ + A_UINT32 opaque_debug_cwmax; + /** FILS discovery period in TU */ + A_UINT32 opaque_debug_fils_period; + /** Beacon interval in TU */ + A_UINT32 opaque_debug_beacon_period; + A_UINT32 opaque_debug_staggered_beacon_intvl; + /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ + A_UINT32 opaque_debug_tx_ctxt_flags; + /** opaque_debug_burst_mode_pending_isr + * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE + * and pending_isr_status count + */ + A_UINT32 opaque_debug_burst_mode_pending_isr; + /** max burst duration from ppdu duration in us */ + A_UINT32 opaque_debug_burst_dur; + /** counter for tx hw stuck */ + A_UINT32 opaque_debug_tx_hw_stuck_cnt; + /** counter for tx consecutive lifetime expiry */ + A_UINT32 opaque_debug_consecutive_lifetime_expiries; + /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ + A_UINT32 opaque_debug_rx_ctxt_flags; + /** wal_pdev fields in rx context for rx_suspend or resume count */ + A_UINT32 opaque_debug_rx_suspend_cnt; + A_UINT32 opaque_debug_rx_resume_cnt; + A_UINT32 opaque_debug_rx_pcie_suspend_cnt; + A_UINT32 opaque_debug_rx_pcie_resume_cnt; + /** This word contains the following bitfields: + * wal_pdev fields + * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET + * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET + * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET + * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET + * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET + * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET + * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET + * sched_algo_resume_needed - + * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET + * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET + * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET + * Green AP TX chainmask valid - WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET + * Green AP RX chainmask valid - WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET + * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET + * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET + */ + A_UINT32 opaque_debug_wal_pdev_bitfield; + /** This word contains the following bitfields: + * gap_phy_mode_freq: + * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) + * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) + * in GAP context is displayed + */ + A_UINT32 opaque_debug_gap_phy_mode_freq; + /** + * The following 5 opaque_debug_reserved_field variables are provided + * purely for debugging by technicians who have outside knowledge of + * what kind of values the target has placed into these fields. + */ + A_UINT32 opaque_debug_reserved_field_1; + A_UINT32 opaque_debug_reserved_field_2; + A_UINT32 opaque_debug_reserved_field_3; + A_UINT32 opaque_debug_reserved_field_4; + A_UINT32 opaque_debug_reserved_field_5; } wmi_ctrl_path_pdev_stats_struct; +#define WMI_PDEV_STATS_NUM_MACS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_NUM_MACS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NUM_PHY_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NUM_PHY_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_VDEV_UP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_VDEV_UP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_REMOTE_PEER_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8 ) +#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8 , val) +#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_NUM_SELF_PEERS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_NUM_SELF_PEERS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_CURRENT_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_CURRENT_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_MAX_NUM_CHIPS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_NUM_CHIPS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_NUM_HOME_CHANS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_HOME_CHANS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_AGG_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_AGG_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_RTS_RC_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_RTS_RC_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_RTS_RC_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_RTS_RC_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_GAP_PHY_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_GAP_PHY_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_HOME_CHAN_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_HOME_CHAN_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_SET(flag,val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_CUR_CHAN_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_SET(flag,val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_BURST_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_BURST_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_PENDING_ISR_STATUS_GET(flag) \ + WMI_GET_BITS(flag, 8, 16) +#define WMI_PDEV_STATS_PENDING_ISR_STATUS_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 16, val) +#define WMI_PDEV_STATS_BCN_Q_NUM_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_BCN_Q_NUM_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_SWFDA_VDEV_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_SWFDA_VDEV_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) + +#define WMI_PDEV_STATS_ABORT_RESULT_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PDEV_STATS_ABORT_RESULT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PDEV_STATS_ABORT_REASON_GET(flag) \ + WMI_GET_BITS(flag, 2, 3) +#define WMI_PDEV_STATS_ABORT_REASON_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 3, val) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_GET(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_PDEV_STATS_CAC_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_PDEV_STATS_CAC_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_PDEV_STATS_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_PDEV_STATS_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_PDEV_STATS_SUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_PDEV_STATS_SUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_PDEV_STATS_MAC_COLD_RESET_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_PDEV_STATS_MAC_COLD_RESET_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_PDEV_STATS_ATF_CONFIG_GET(flag) \ + WMI_GET_BITS(flag, 18, 1) +#define WMI_PDEV_STATS_ATF_CONFIG_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 1, val) +#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_GET(flag) \ + WMI_GET_BITS(flag, 19, 1) +#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 1, val) +#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_PDEV_STATS_ATF_STRICT_SCH_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_PDEV_STATS_ATF_STRICT_SCH_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_PDEV_STATS_BCN_TX_MODE_GET(flag) \ + WMI_GET_BITS(flag, 22, 2) +#define WMI_PDEV_STATS_BCN_TX_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 2, val) +#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_PDEV_STATS_DYN_BW_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_PDEV_STATS_DYN_BW_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_PDEV_STATS_BURST_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) +#define WMI_PDEV_STATS_BURST_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_btcoex_stats_struct*/ A_UINT32 tlv_header; @@ -11756,6 +12421,11 @@ typedef enum { WMI_CTRL_PATH_STATS_ARENA_DBG_SRAM_AUX, WMI_CTRL_PATH_STATS_ARENA_SRAM_AUX_OVERFLOW, WMI_CTRL_PATH_STATS_ARENA_AMSS, + WMI_CTRL_PATH_STATS_ARENA_MLO_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_MLO_H_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_MLO_HC_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_RRI_CMD, + WMI_CTRL_PATH_STATS_ARENA_SRAM_CLADE, WMI_CTRL_PATH_STATS_ARENA_MAX, } wmi_ctrl_path_fw_arena_ids; @@ -11788,6 +12458,11 @@ static INLINE A_UINT8 *wmi_ctrl_path_fw_arena_id_to_name(A_UINT32 arena_id) WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_DBG_SRAM_AUX); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_SRAM_AUX_OVERFLOW); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_AMSS); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_H_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_HC_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_RRI_CMD); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_SRAM_CLADE); } return (A_UINT8 *) "WMI_CTRL_PATH_STATS_ARENA_UNKNOWN"; @@ -12487,6 +13162,924 @@ typedef struct { A_UINT32 cfr_resp_failure_count; } wmi_ctrl_path_cfr_stats_struct; + +#define WMI_MAX_MLO_LINKS 5 +#define WMI_HE_MAP_COUNT 3 +#define WMI_EHT_MAP_COUNT 3 + +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct + */ + A_UINT32 tlv_header; + /* mac address - part of wlan_peer */ + wmi_mac_addr mac_addr; + /* wlan_peer flags - refer to IEEE80211_NODE_* flags in wlan_peer.h */ + A_UINT32 opaque_debug_flags; + /* opaque_debug_vht_caps: + * Negotiated VHT capabilities in the wlan_peer struct + * Refer to ieee80211_defs.h. + */ + A_UINT32 opaque_debug_vht_caps; + /* opaque_debug_flags_ext: + * Extended flags in the wlan_peer struct + * Refer to IEEE80211_NODE_* flags in wlan_peer.h. + */ + A_UINT32 opaque_debug_flags_ext; + /* TID queues marked for TWT flush, present in wlan_peer */ + A_UINT32 opaque_debug_twt_flush_tidmap; + /* Number of TWT SPs to be expired, present in wlan_peer */ + A_UINT32 opaque_debug_n_TWT_SPs_to_expire; + /* opaque_debug_rc_flags: + * Peer rate information, part of struct rate_node + * Refer to whal_rate_api.h for complete RC_FLAGS details. + */ + A_UINT32 opaque_debug_rc_flags; + /* opaque_debug_sm_event_mask_eosp_cnt: + * This word contains the following bitfields: + * - Power save state machine event mask, + * part of wal_ps_buf_peer_handle_t. + * Refer to enum wal_ps_buf_peer_reg_ev_handlers. + * Use WMI_PEER_STATS_SM_MASK_SET,GET macros. + * - End of service period (EOSP) sent retry counter, + * part of wal_ps_buf_peer_handle_t. + * Use WMI_PEER_STATS_EOSP_RETRY_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_sm_event_mask_eosp_cnt; + /* opaque_debug_ps_buf_peer_flag1: + * Power save related send_n, ps_poll, unscheduled service period + * related fields; + * Part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag1; + /* opaque_debug_ps_buf_peer_flag2: + * Power save related trigger/delivery tid related fields. + * part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag2; + /* opaque_debug_ps_buf_peer_flag3: + * Power save related last trigger related information, + * part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag3; + /* opaque_debug_last_rx_trigger_time: + * Time of the most recently received uplink trigger frame, + * part of wal_ps_buf_peer_handle_t - in microseconds units. + */ + A_UINT32 opaque_debug_last_rx_trigger_time; + /* opaque_debug_last_poll_time: + * TSF of the most recently received uplink PS-Poll, + * part of wal_ps_buf_peer_handle_t - in TU + */ + A_UINT32 opaque_debug_last_poll_time; + /* opaque_debug_oldest_tx_buffered_waiting_ms: + * Enqueue time of most recent MSDU that AP has buffered for + * sleeping station, part of wal_ps_buf_peer_handle_t, in ms units. + */ + A_UINT32 opaque_debug_oldest_tx_buffered_waiting_ms; + /* opaque_debug_last_rxtx_activity: + * The last time when there was a rx or tx traffic from a client, + * part of wal_ps_buf_peer_handle_t, in ms units. + */ + A_UINT32 opaque_debug_last_rxtx_activity; + /* opaque_debug_twt_flush_expiry_timestamp: + * Peer's TWT flush expiry timestamp in us, + * part of peer_twt_flush struct. + */ + A_UINT32 opaque_debug_twt_flush_expiry_timestamp; + /* opaque_debug_hw_link_id: + * Unique link id across SOCs, determined during QMI handshake, + * part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_hw_link_id; + /* opaque_debug_ml_partner_hw_link_id_bitmap: + * Hardware link id of the of partner links that are to be cleaned up. + * This is filled by host during peer delete cmd. + * It it part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_ml_partner_hw_link_id_bitmap; + /* opaque_debug_link_flags: + * MLO link flags: related to assoc, anchor, master and primary UMAC links. + * Refer to resmgr_mlo_link_flags. + * Part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_link_flags; + /* MLO peer id - part of wlan_ml_peer_t */ + A_UINT32 opaque_debug_ml_peer_id; + /* MLD mac address - part of wlan_ml_peer_t */ + wmi_mac_addr opaque_debug_mld_mac_addr; + /* opaque_debug_assoc_id_usage_cnt: + * Part of wlan_peer. + * This word contains the following bitfields: + * - assoc id of the peer + * Use WMI_PEER_STATS_ASSOCIATE_ID_SET,GET macros. + * - peer usage count to track if peer alloc command is sent + * for new or existing peer, + * Use WMI_PEER_STATS_USAGE_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_assoc_id_usage_cnt; + /* opaque_debug_default_ht_caps: + * Part of wlan_peer. + * This word contains the following bitfields: + * - default peer capabilities of the peer - refer ieee80211_defs.h + * Use WMI_PEER_STATS_DEF_CAPS_SET,GET macros. + * - HT capabilities of the peer - refer ieee80211_defs.h + * Use WMI_PEER_STATS_HT_CAPS_SET,GET macros. + */ + A_UINT32 opaque_debug_default_ht_caps; + /* opaque_debug_inact_gen: + * Part of wlan_peer. + * This word contains the following bitfields: + * - Overall tx/rx inactivity time of the peer in seconds + * Use WMI_PEER_STATS_INACT_GEN_SET,GET macros. + * - Data tx/rx inactivity time of the peer in seconds. + * Use WMI_PEER_STATS_DATA_INACT_GEN_SET,GET macros. + */ + A_UINT32 opaque_debug_inact_gen; + /* opaque_debug_id_type: + * Part of wlan_peer. + * This word contains the following bitfields: + * - Type of peer whether it is bss,self or remote peer. + * Refer to enum wmi_peer_type. + * Use WMI_PEER_STATS_TYPE_SET,GET macros. + * - MAC ID that the peer belongs to + * Use WMI_PEER_STATS_MAC_ID_SET,GET macros. + * - sw peer id of the peer + * Use WMI_PEER_STATS_ID_SET,GET macros. + */ + A_UINT32 opaque_debug_id_type; + /* Deleted tids bitmask within the peer - part of wal_peer */ + A_UINT32 opaque_debug_deleted_tidmask; + /* number of local pending frames for completions - part of wal_peer */ + A_UINT32 opaque_debug_num_of_local_frames_pending; + /* flags part of wal_peer - refer to wal_peer_flags_t */ + A_UINT32 opaque_debug_wal_peer_flags; + /* opaque_debug_keyid0_ast_index: + * The AST index for key id 0 which is always allocated, + * part of wal_peer. + */ + A_UINT32 opaque_debug_keyid0_ast_index; + /* opaque_debug_all_tids_block_module_bitmap: + * Bitmap of block IDs requesting block of all TIDs, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_all_tids_block_module_bitmap; + /* opaque_debug_all_tids_pause_module_bitmap: + * Bitmap of pause IDs requesting block of all TIDs, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_all_tids_pause_module_bitmap; + /* opaque_debug_data_tids_block_module_bitmap: + * Bitmap of block ids requesting block of data tids, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_data_tids_block_module_bitmap; + /* opaque_debug_data_tids_pause_module_bitmap: + * Bitmap of pause ids requesting block of data tids, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_data_tids_pause_module_bitmap; + /* The time stamp when first ppdu fails in us, part of wal_peer */ + A_UINT32 opaque_debug_ppdu_fail_time; + /* opaque_debug_rate_params: + * This word contains the following bitfields: + * - Non data rate code of the peer - part of wal_peer + * Use WMI_PEER_STATS_BSS_NON_DATA_RC_SET,GET macros. + * - channel bandwidth supported by the peer, part of wal_peer. + * The mapping is as follows: + * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz + * Use WMI_PEER_STATS_CH_WIDTH_SET,GET macros. + * - MCS used for the last PPDU received from the peer, part of wal_peer + * Use WMI_PEER_STATS_RX_MCS_SET,GET macros. + */ + A_UINT32 opaque_debug_rate_params; + /* consecutive QOS null frame tx fail count, part of wal_peer */ + A_UINT32 opaque_debug_consecutive_null_failure; + /* peer delete state refer enum PEER_DELETE_SM_STATE, part of wal_peer */ + A_UINT32 opaque_debug_peer_delete_sm_state; + /* opaque_debug_cache_rate_info_low32,_high32: + * Lower/upper 32 bits respectively of cached rate info variable + * updated by the HTT metadata. + * This rate_info is based on the values from struct + * htt_tx_msdu_desc_ext2_t . + * If htt_tx_desc_ext2->update_peer_cache is set to 1 and + * HTT_TX_TCL_METADATA_PEER_ID_GET(tcl_cmd_num) returns valid peer ID + * then rate_info cache of the peer is updated. + * Part of wal_peer. + */ + A_UINT32 opaque_debug_cache_rate_info_low32; + A_UINT32 opaque_debug_cache_rate_info_high32; + /* opaque_debug_peer_delete_rc4_rekey: + * This word contains the following bitfields: + * - Flag that denotes if Peer delete all is in progress or not, + * part of wal_peer. + * Use WMI_PEER_STATS_DELETE_ALL_FLAG_SET,GET macros. + * - RC4 rekey counter, part of wal_peer. + * Use WMI_PEER_STATS_RC4_REKEY_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_peer_delete_rc4_rekey; + /* opaque_debug_mcbc_tids_pause_bitmap: + * Bitmap containing Multicast and broadcast tids that are paused, + * part of wal_peer. + */ + A_UINT32 opaque_debug_mcbc_tids_pause_bitmap; + /* opaque_debug_next_to_last_pn_low32,_high32: + * Lower/upper 32 bits respectively of last used PN value received, + * part of wal_peer. + */ + A_UINT32 opaque_debug_next_to_last_pn_low32; + A_UINT32 opaque_debug_next_to_last_pn_high32; + /* opaque_debug_last_pn_low32,_high32: + * Lower/upper 32 bits respectively of current PN value received, + * part of wal_peer. + */ + A_UINT32 opaque_debug_last_pn_low32; + A_UINT32 opaque_debug_last_pn_high32; + /* opaque_debug_twt_ap_peer_ctx_flags: + * This word contains the following bitfields: + * - TWT AP peer's context flags, part of twt_ap_peer_handle_t struct. + * Refer twt_ap_twt_session_t definition. + * Use WMI_PEER_STATS_TWT_AP_FLAGS_SET,GET macros. + * - TWT session counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET,GET macros. + * - TWT frame retry counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_FRM_RETRY_SET,GET macros. + */ + A_UINT32 opaque_debug_twt_ap_peer_ctx_flags; + /* opaque_debug_twt_ap_counters: + * This word contains the following bitfields: + * - TWT UL trigger counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_UL_TRIGGER_SET,GET macros. + * - TWT Broadcast session counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_BC_SESSION_SET,GET macros. + * - TWT pending report counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_PENDING_REPORT_SET,GET macros. + * - TWT flow IDs, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_FLOW_IDS_SET,GET macros. + */ + A_UINT32 opaque_debug_twt_ap_counters; + /* opaque_debug_tx_state_bmap_low32,_high32: + * Lower/upper 32 bits respectively of list of currently running + * BA Tx states for tids in this peer, part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_state_bmap_low32; + A_UINT32 opaque_debug_tx_state_bmap_high32; + /* opaque_debug_addba_mode: + * This word contains the following bitfields: + * - ADDBA mode whether its automatic or manual, + * WAL_BA_ADDBA_MODE_AUTO = 0 and WAL_BA_ADDBA_MODE_MANUAL = 1 + * Part of wal_ba_peer_handle_t. + * Use WMI_PEER_STATS_ADDBBA_TX_MODE_SET,GET macros. + * - ADDBA request's response code, part of wal_ba_peer_handle_t. + * Use WMI_PEER_STATS_ADDBBA_RESP_MODE_SET,GET macros. + */ + A_UINT32 opaque_debug_addba_mode; + /* opaque_debug_tx_retry_bmap: + * Bitmap of tids and their TX BlockAck retry counters. + * Each TID uses 2 bits for its BA retry counter. + * Part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_retry_bmap; + /* opaque_debug_rx_state_bmap: + * Bitmap of tids and their RX BlockAck retry counters. + * 00 - BA not setup + * 01 - BA in progress + * 10 - reserved + * 11 - BA setup. + * Each TID uses 2 bits for its BA RX state; + * for instance TID 0's BA info occupies bits 1:0 and so on. + * Part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_rx_state_bmap; + /* opaque_debug_tx_pending_delba_tid_bmap: + * TID bitmap containaing information DELBA tx pending, + * part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_pending_delba_tid_bmap; + /* opaque_debug_link_monitor_tid_num: + * link monitor tid num in bss_peer ba_peer_handle, + * part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_link_monitor_tid_num; + /* opaque_debug_rc4_eapol_key_complete: + * Flag that denotes rc4 eapol key exchange is complete, + * part of wal_peer_ext. + */ + A_UINT32 opaque_debug_rc4_eapol_key_complete; + /* qcache peer flags, refer to qpeer_flags_t */ + A_UINT32 opaque_debug_qpeer_flags; + /* bitmap of TIDs requested for flush, part of wal_qcache_peer */ + A_UINT32 opaque_debug_delete_requested_tidmask; + /* bitmap of created TIDs, part of wal_qcache_peer */ + A_UINT32 opaque_debug_tid_created_tidmask; + /* opaque_debug_qpeer_rt_flags0,_flags1,_flags2: + * RT thread related fields in qpeer, refer to _wal_qcache_peer. + */ + A_UINT32 opaque_debug_qpeer_rt_flags0; + A_UINT32 opaque_debug_qpeer_rt_flags1; + A_UINT32 opaque_debug_qpeer_rt_flags2; + /* opaque_debug_qpeer_sa_flags0,_flags1: + * SA thread related fields in qpeer, refer to _wal_qcache_peer. + */ + A_UINT32 opaque_debug_qpeer_sa_flags0; + A_UINT32 opaque_debug_qpeer_sa_flags1; + /* BE thread related fields in qpeer, refer to _wal_qcache_peer */ + A_UINT32 opaque_debug_qpeer_be_flags; + /* qpeer event bitmap, refer to wal_peer_event_type */ + A_UINT32 opaque_debug_event_bitmap; + /* tx fail count for a peer, part of dcache peer */ + A_UINT32 opaque_debug_seq_no_tx_fail_cnt; + /* Last transmission rate in kbps for a peer, part of dcache peer */ + A_UINT32 opaque_debug_last_tx_rate_kbps; + /* opaque_debug_amsdu_size: + * This word contains the following bitfields: + * - MAX AMSDU size of the peer, part of dcache peer. + * Use WMI_PEER_STATS_MAX_AMSDU_SIZE_SET,GET macros. + */ + A_UINT32 opaque_debug_amsdu_size; + /* opaque_debug_fake_sleep_time: + * Time elapsed in ms after entering into fake sleep after xretry failure, + * part of dcache peer. + */ + A_UINT32 opaque_debug_fake_sleep_time; + /* opaque_debug_tx_frame_qos_ctrl: + * This word contains the following bitfields: + * - Tx frame control FC flags in ieee80211_defs.h, part of dcache peer. + * Use WMI_PEER_STATS_TX_FRAME_CTRL_SET,GET macros. + * - Tx QOS control FC flags in ieee80211_defs.h, part of dcache peer. + * Use WMI_PEER_STATS_TX_QOS_CTRL_SET,GET macros. + */ + A_UINT32 opaque_debug_tx_frame_qos_ctrl; + /* opaque_debug_consec_fail_subfrm_sz: + * This word contains the following bitfields: + * - Consecutive tx fail count for the peer, part of dcache peer. + * Use WMI_PEER_STATS_CONSEC_FAIL_SET,GET macros. + * - subframe size configured for the peer, part of dcache peer. + * Use WMI_PEER_STATS_SUBFRAME_SIZE_SET,GET macros. + */ + A_UINT32 opaque_debug_consec_fail_subfrm_sz; + /* opaque_debug_tx_fail_partial_aid: + * This word contains the following bitfields: + * - tx fail count for the peer, part of dcache peer. + * Use WMI_PEER_STATS_TX_FAIL_CNT_SET,GET macros. + * - Partial AID of the peer, part of dcache peer. + * Use WMI_PEER_STATS_TX_PARTIAL_AID_SET,GET macros. + */ + A_UINT32 opaque_debug_tx_fail_partial_aid; + /* opaque_debug_max_nss: + * Part of dcache peer. + * This word contains the following bitfields: + * - Peer NSS value sent by host during WMI_PEER_ASSOC cmd. + * Use WMI_PEER_STATS_MAX_NSS_SET,GET macros. + */ + A_UINT32 opaque_debug_max_nss; + /* opaque_debug_he_cap_info: + * Peer HE capabilities info sent during peer assoc cmd. + * Refer to WMI_HECAP_* macros in wmi_unified.h. + * Part of dcache peer. + */ + A_UINT32 opaque_debug_he_cap_info; + /* opaque_debug_he_cap_info_ext: + * Peer extended HE capabilities info sent during peer assoc cmd. + * Refer to WMI_HECAP_* macros in wmi_unified.h. + * Part of dcache peer. + */ + A_UINT32 opaque_debug_he_cap_info_ext; + /* opaque_debug_eht_cap_info: + * Peer EHT capabilities info. + * Refer to ieee80211_defs.h, part of dcache peer. + */ + A_UINT32 opaque_debug_eht_cap_info; + /* TAC thread related fields in dcache peer refer wal_dcache_peer_t */ + A_UINT32 opaque_debug_dcache_tac_flags; + /* RT thread related fields in dcache peer refer wal_dcache_peer_t */ + A_UINT32 opaque_debug_dcache_rt_flags; + /* Supported RC modes for the peer refer enum RC_MODE, part of dcache */ + A_UINT32 opaque_debug_rc_mode_supported_mask; + /* opaque_debug_wlan_peer_bitfield_mask: + * Part of wlan peer. This word contains the following bitfields: + * - Flag that denotes whether peer delete response is being sent + * to host or not. + * Use WMI_PEER_STATS_DEL_RESP_TO_HOST_SET,GET macros. + * - Flag that denotes if peer delete is in progress or not. + * Use WMI_PEER_STATS_DELETE_IN_PROGRESS_SET,GET macros. + * - Flag that denotes if peer migration is in progress or not. + * Use WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET,GET macros. + * - Flag that denotes peer's connection/authorized state. + * Refer WAL_PEER_STATE_* macros in wal_peer.h. + * Use WMI_PEER_STATS_CONN_STATE_SET,GET macros. + * - TX chain mask at 160MHz of the peer set during peer assoc command. + * Use WMI_PEER_STATS_TX_CHAIN_MASK_160_SET,GET macros. + * - Tx chain mask set during peer assoc command. + * Use WMI_PEER_STATS_TX_CHAIN_MASK_SET,GET macros. + * - copy of tx chain mask of peer saved for AP MIMO PS. + * Use WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET,GET macros. + */ + A_UINT32 opaque_debug_wlan_peer_bitfield_mask; + /* opaque_debug_wal_peer_bitfields: + * Part of wal_peer. This word contains the following bitfields: + * - Flag that denotes if QOS null is sent over WMI or not. + * Use WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET,GET macros. + * - Flag that denotes whether peer assoc is received + * for the first time or not. + * Use WMI_PEER_STATS_NEW_ASSOC_SET,GET macros. + * - Flag that denotes whether TWT filter is enabled or not. + * Use WMI_PEER_STATS_TWT_FILT_FLAG_SET,GET macros. + * - Flag that denotes whether TWT is registered or not. + * Use WMI_PEER_STATS_TWT_REG_FLAG_SET,GET macros. + * - Flag that denotes whether WMM txQ uplink trigger is disabled or not. + * Use WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET,GET macros. + * - Number of active TIDs that do not have BA setup. + * Use WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET,GET macros. + */ + A_UINT32 opaque_debug_wal_peer_bitfields; + /* flags in RT context refer wal_peer_ext_t */ + A_UINT32 opaque_debug_wal_peer_rt_flags; + /* opaque_debug_ml_attributes: + * Part of wal_ml_peer. This word contains the following bitfields: + * - Num of MLO links + * Use WMI_PEER_STATS_NUM_LINKS_SET,GET macros. + * - ML peer id + * Use WMI_PEER_STATS_ML_PEER_ID_SET,GET macros. + * - Primary link ID + * Use WMI_PEER_STATS_PRI_LINK_ID_SET,GET macros. + * - Primary chip ID + * Use WMI_PEER_STATS_PRI_CHIP_ID_SET,GET macros. + * - Initial link count + * Use WMI_PEER_STATS_LINK_INIT_CNT_SET,GET macros. + * - Number of local links + * Use WMI_PEER_STATS_NUM_LOCAL_LINKS_SET,GET macros. + * - Bitmap of participating chips + * Use WMI_PEER_STATS_CHIPS_BITMAP_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_attributes; + /* wal peer MLO flags refer ml_peer_flags_t */ + A_UINT32 opaque_debug_ml_flags; + /* opaque_debug_ml_link_info_flags: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - flag denoting if MLO-link is valid or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET,GET macros. + * - flag denoting if MLO-link is active or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET,GET macros. + * - flag denoting if MLO-link is primary or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET,GET macros. + * - flag denoting if MLO-link is assoc link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET,GET macros. + * - Chip ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET,GET macros. + * - IEEE link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET,GET macros. + * - HW link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET,GET macros. + * - logical link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET,GET macros. + * - flag denoting if MLO-link is master link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET,GET macros. + * - flag denoting if MLO-link is anchor link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET,GET macros. + * - flag denoting if MLO-link is initialized or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_link_info_flags[WMI_MAX_MLO_LINKS]; + /* opaque_debug_ml_link_info_id: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - sw_peer_id corresponding to the link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET,GET macros. + * - vdev id corresponding to the link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_link_info_id[WMI_MAX_MLO_LINKS]; + /* MLO link info primary tid mask, part of link_info in wlan_peer_ml_info_t */ + A_UINT32 opaque_debug_ml_link_info_pri_tidmask[WMI_MAX_MLO_LINKS]; + /* opaque_debug_rc_node_params: + * Part of struct TX_PEER_PARAMS. + * This word contains the following bitfields: + * - NSS of the peer in 160MHZ + * Use WMI_PEER_STATS_NSS_160_SET,GET macros. + * - phymode of the peer - refer enum WLAN_PHY_MODE + * Use WMI_PEER_STATS_RC_PHYMODE_SET,GET macros. + * - legacy rate set for the peer + * Use WMI_PEER_STATS_LEGACY_RATE_SET,GET macros. + */ + A_UINT32 opaque_debug_rc_node_params; + /* opaque_debug_rc_vht_mcs_set: + * Rate node param - negotiated VHT MCS map, + * part of struct TX_PEER_PARAMS + */ + A_UINT32 opaque_debug_rc_vht_mcs_set; + /* opaque_debug_rc_node_params1: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - Minimum data rate set for the peer in Mbps + * Use WMI_PEER_STATS_MIN_DATA_RATE_SET,GET macros. + * - Max VHT rate set for the peer + * Use WMI_PEER_STATS_VHT_MAX_RATE_SET,GET macros. + * - Max VHT streams set for the peer + * Use WMI_PEER_STATS_VHT_MAX_STREAMS_SET,GET macros. + * - BSS - Channel frequency set for the peer in MHz + * Use WMI_PEER_STATS_RC_CHAN_FREQ_SET,GET macros. + */ + A_UINT32 opaque_debug_rc_node_params1; + /* opaque_debug_he_mcs_nss_set_tx,_rx: + * Rate node param - negotiated HE MCS tx+rx maps, + * part of struct TX_PEER_PARAMS. + * The lower 8 bits (bits 23:16) within the upper 16 bits indicate + * MCS 12/13 enablement for BW <= 80MHz; the upper 8 bits (bits 31:24) + * within the 16 bits indicate MCS 12/13 enablement for BW > 80MHz. + * The 16 bits for the index values are within the upper bits (bits 31:16) + * of a 32-bit word. and WMI_HE_MAP_COUNT is based on HE_MCS_MAP_CNT + * in ieee80211_defs.h. + */ + A_UINT32 opaque_debug_he_mcs_nss_set_tx[WMI_HE_MAP_COUNT]; + A_UINT32 opaque_debug_he_mcs_nss_set_rx[WMI_HE_MAP_COUNT]; + /* opaque_debug_eht_mcs_nss_set_tx,_rx: + * Rate node param - negotiated EHT MCS tx+rx maps, + * part of struct TX_PEER_PARAMS. + * B0-B3 indicates max NSS that supports mcs 0-7 + * B4-B7 indicates max NSS that supports mcs 8-9 + * B8-B11 indicates max NSS that supports mcs 10-11 + * B12-B15 indicates max NSS that supports mcs 12-13 + * B16-B31 reserved. + * WMI_EHT_MAP_COUNT is based on EHT_MCS_MAP_CNT in ieee80211_defs.h. + */ + A_UINT32 opaque_debug_eht_mcs_nss_set_tx[WMI_EHT_MAP_COUNT]; + A_UINT32 opaque_debug_eht_mcs_nss_set_rx[WMI_EHT_MAP_COUNT]; + /* opaque_debug_rc_user_start_mcs_rate: + * Rate node user_start_rate is MCS value set based on phymode. + * For possible values refer "INITIAL_" macros in ratectrl.h. + * Part of struct TX_PEER_PARAMS. + * This is the starting value of MCS that was used by rate control + * for the first transmissions to the peer, until PER information + * from the peer allowed the rate control algorithm to determine + * the suitable MCS. + */ + A_UINT32 opaque_debug_rc_user_start_mcs_rate; + /* + * The following 4 opaque_debug_field variables are provided purely + * for debugging by technicians who have outside knowledge of what + * kind of values the target has placed into these fields. + * They are not to be interpreted by the host driver in any manner. + */ + A_UINT32 opaque_debug_field_1; + A_UINT32 opaque_debug_field_2; + A_UINT32 opaque_debug_field_3; + A_UINT32 opaque_debug_field_4; +} wmi_ctrl_path_peer_stats_struct; + +#define WMI_PEER_STATS_SM_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_SM_MASK_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_EOSP_RETRY_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_EOSP_RETRY_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_ASSOCIATE_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ASSOCIATE_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_USAGE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_USAGE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_DEF_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_DEF_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_HT_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_HT_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_INACT_GEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_INACT_GEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_DATA_INACT_GEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_DATA_INACT_GEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_PEER_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_PEER_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_MAC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_MAC_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_BSS_NON_DATA_RC_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_BSS_NON_DATA_RC_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_CH_WIDTH_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_CH_WIDTH_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_RX_MCS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_RX_MCS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_DELETE_ALL_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_DELETE_ALL_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_RC4_REKEY_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_RC4_REKEY_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +/* bits 31:16 unused/reserved */ + +#define WMI_PEER_STATS_TWT_AP_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TWT_AP_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_TWT_FRM_RETRY_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_TWT_FRM_RETRY_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_TWT_UL_TRIGGER_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_TWT_UL_TRIGGER_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_TWT_BC_SESSION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_TWT_BC_SESSION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_TWT_PENDING_REPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TWT_PENDING_REPORT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_TWT_FLOW_IDS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_TWT_FLOW_IDS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_ADDBBA_TX_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ADDBBA_TX_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_ADDBBA_RESP_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_ADDBBA_RESP_MODE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MAX_AMSDU_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_MAX_AMSDU_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +/* bits 31:16 unused/reserved */ + +#define WMI_PEER_STATS_TX_FRAME_CTRL_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TX_FRAME_CTRL_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TX_QOS_CTRL_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_TX_QOS_CTRL_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_CONSEC_FAIL_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_CONSEC_FAIL_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_SUBFRAME_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_SUBFRAME_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_TX_FAIL_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TX_FAIL_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TX_PARTIAL_AID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_TX_PARTIAL_AID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MAX_NSS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_MAX_NSS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +/* bits 31:8 unused/reserved */ + +#define WMI_PEER_STATS_DEL_RESP_TO_HOST_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_DEL_RESP_TO_HOST_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_DELETE_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_DELETE_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_CONN_STATE_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 4, val) +#define WMI_PEER_STATS_CONN_STATE_GET(flag) \ + WMI_GET_BITS(flag, 3, 4) +#define WMI_PEER_STATS_TX_CHAIN_MASK_160_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_TX_CHAIN_MASK_160_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_TX_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TX_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_NEW_ASSOC_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_NEW_ASSOC_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_TWT_FILT_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_TWT_FILT_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_TWT_REG_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_PEER_STATS_TWT_REG_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 4, val) +#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_GET(flag) \ + WMI_GET_BITS(flag, 5, 4) +/* bits 31:10 unused/reserved */ + +#define WMI_PEER_STATS_NUM_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 2, val) +#define WMI_PEER_STATS_NUM_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 0, 2) +#define WMI_PEER_STATS_ML_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 12, val) +#define WMI_PEER_STATS_ML_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 2, 12) +#define WMI_PEER_STATS_PRI_LINK_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 3, val) +#define WMI_PEER_STATS_PRI_LINK_ID_GET(flag) \ + WMI_GET_BITS(flag, 14, 3) +#define WMI_PEER_STATS_PRI_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 2, val) +#define WMI_PEER_STATS_PRI_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 17, 2) +#define WMI_PEER_STATS_LINK_INIT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 3, val) +#define WMI_PEER_STATS_LINK_INIT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 19, 3) +#define WMI_PEER_STATS_NUM_LOCAL_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 2, val) +#define WMI_PEER_STATS_NUM_LOCAL_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 22, 2) +#define WMI_PEER_STATS_CHIPS_BITMAP_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_CHIPS_BITMAP_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 3, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 4, 3) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 8, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_GET(flag) \ + WMI_GET_BITS(flag, 7, 8) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 3, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_GET(flag) \ + WMI_GET_BITS(flag, 15, 3) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 2, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_GET(flag) \ + WMI_GET_BITS(flag, 18, 2) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +/* bits 31:23 unused/reserved */ + +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_NSS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_NSS_160_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_RC_PHYMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_RC_PHYMODE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_LEGACY_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_LEGACY_RATE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MIN_DATA_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_MIN_DATA_RATE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_VHT_MAX_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 4, val) +#define WMI_PEER_STATS_VHT_MAX_RATE_GET(flag) \ + WMI_GET_BITS(flag, 8, 4) +#define WMI_PEER_STATS_VHT_MAX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 4, val) +#define WMI_PEER_STATS_VHT_MAX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 12, 4) +#define WMI_PEER_STATS_RC_CHAN_FREQ_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_RC_CHAN_FREQ_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */ + A_UINT32 tlv_header; + /* blanking_mode: + * blanking configuration. Refer to WMI_SCAN_BLANKING_MODE + */ + A_UINT32 blanking_mode; + /* is_blanking_enabled: + * current blanking status. 0 = disabled, 1 = enabled + */ + A_UINT32 is_blanking_enabled; + A_UINT32 gate_2g_enabled; /* 2.4GHZ gate pin state */ + A_UINT32 gate_5g_enabled; /* 5GHz gate pin state */ + A_UINT32 gate_6g_enabled; /* 6GHz gate pin state */ + A_UINT32 blanking_count; /* scan radio blanking count */ + A_UINT32 blanking_duration; /* scan radio blanking duration in us */ +} wmi_ctrl_path_blanking_stats_struct; + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_ctrl_path_stats_event_fixed_param */ @@ -12732,10 +14325,19 @@ typedef struct { A_UINT32 tx_bcn_outage_cnt; /* Total number of failed beacons */ } wmi_bcn_stats; +#define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT 0 +#define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_MASK \ + (1 << WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT) + +#define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT 1 +#define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_MASK \ + (1 << WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT) + /** * vdev extension statistics */ typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_vdev_extd_stats */ A_UINT32 tlv_header; /* vdev id */ A_UINT32 vdev_id; @@ -12747,8 +14349,1187 @@ typedef struct { A_UINT32 unsolicited_prb_succ_cnt; /* Total number of unsolicited probe response frames failed */ A_UINT32 unsolicited_prb_fail_cnt; + /* vdev info flags: + * bit 0: WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID, + * 0: the "is link active" flag is not valid + * 1: the "is link active" flag is valid + * bit 1: WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE, + * 1:link_active; 0:link_inactive + * Refer to WMI_VDEV_STATS_FLAGS_ defs. + */ + A_UINT32 flags; + + /** opaque_debug_wal_vdev_flags: + * This will contain the value from wal_vdev wal vdev flags for vdev state + */ + A_UINT32 opaque_debug_wal_vdev_flags; + /** control flags for this vdev */ + A_UINT32 opaque_debug_vdev_flags; + /** vdevid of transmitted AP (mbssid case) */ + A_UINT32 opaque_debug_vdevid_trans; + /** opaque_debug_profile_idx: + * the profile index of the connected non-trans ap (mbssid case). + * 0 means invalid. + */ + A_UINT32 opaque_debug_profile_idx; + /** opaque_debug_profile_num: + * the total profile numbers of non-trans aps (mbssid case). + * 0 means legacy AP. + */ + A_UINT32 opaque_debug_profile_num; + /* Contains the value of multi_vdev_restart status */ + A_UINT32 opaque_debug_multi_vdev_restart; + /* Contains the value of created mac_id from wal_vdev */ + A_UINT32 opaque_debug_created_mac_id; + /* Contains the value of consecutive count of the leaky AP */ + A_UINT32 opaque_debug_consec_detect_leaky_ap_cnt; + /* Contains the value of Vdev manager debug flags */ + A_UINT32 opaque_debug_vdev_mgr_dbg_flags; + /* Contains the value of max vdev pause delay in microseconds */ + A_UINT32 opaque_debug_max_pause_delay_us; + /* opaque_debug_sta_offset: + * Contains the value of the offset of vdev TSF with BI (vdev_tsf%BI) + * for STA vdev. + */ + A_UINT32 opaque_debug_sta_offset; + /* Contains the value of vdev pn sequence receive filter */ + A_UINT32 opaque_debug_vdev_pn_rx_filter; + /* Contains the value of config params */ + A_UINT32 opaque_debug_traffic_config; + /* opaque_debug_he_bss_rts_thld_tu: + * Contains Period of time in units for a non-AP STA to reserve the medium. + */ + A_UINT32 opaque_debug_he_bss_rts_thld_tu; + /* opaque_debug_rts_threshold: + * Contains the value of Request to Send (RTS) Threshold of the packet size. + */ + A_UINT32 opaque_debug_rts_threshold; /* dot11RTSThreshold */ + /* Contains the value of Tx failure count threshold */ + A_UINT32 opaque_debug_tx_fail_cnt_thres; + /* Contains the value of ratio = HI_WORD/LO_WORD */ + A_UINT32 opaque_debug_mu_edca_sifs_ratio; + /* opaque_debug_kickout_th: + * Contains the value of kickout threshold that denotes units of + * lost block acks of consecutive tx failure threshold. + */ + A_UINT32 opaque_debug_kickout_th; + /* opaque_debug_rate_dd_bmap: + * Contains the value of per vap config related to VAP aggregation + * of ratectrl drop-down limits. + */ + A_UINT32 opaque_debug_rate_dd_bmap; + /* Contains the value of Maximum Transmission Unit frame size */ + A_UINT32 opaque_debug_mtu_size; + /* Contains the value of vdev event bitmap from wal_vdev */ + A_UINT32 opaque_debug_event_bitmap; + /* Contains the value of peer event bitmap from wal_vdev */ + A_UINT32 opaque_debug_peer_event_bitmap; + /* Contains the value of Sched config of vdev allowed time during ATF */ + A_UINT32 opaque_debug_atf_vdev_allowed_time; + /* opaque_debug_atf_vdev_used_unallocated_time: + * Contains the value of Sched config of vdev used unallocated time + * during ATF. + */ + A_UINT32 opaque_debug_atf_vdev_used_unallocated_time; + /* Contains the value of Sched config of vdev unused time during ATF */ + A_UINT32 opaque_debug_atf_vdev_unused_time; + /* Contains the value of Carrier frequency offset last programmed time */ + A_UINT32 opaque_debug_last_prog_time; + /* Contains the value of Carrier frequency offset last receive time */ + A_UINT32 opaque_debug_last_recv_time; + /* Contains the value of Packet count of received frames on the channel */ + A_UINT32 opaque_debug_rx_pkt_on_channel; + /* Contains the value of Target beacon transmission time offset value */ + A_UINT32 opaque_debug_tbtt_offset; + /* Contains the value of tid pause bitmap of the peer from wal_vdev */ + A_UINT32 opaque_debug_peer_all_tid_pause_bitmap; + /* Contains the value of tid block bitmap of the peer from wal_vdev */ + A_UINT32 opaque_debug_peer_all_tid_block_bitmap; + /* Contains the value of tdls peer kickout threshold */ + A_UINT32 opaque_debug_tdls_peer_kickout_th; + /* opaque_debug_num_of_remote_peers_connected: + * Contains the value of num_of_remote_peers_connected; + * Below field is valid only for AP vap. + */ + A_UINT32 opaque_debug_num_of_remote_peers_connected; + /* Contains the value of num of Multi group key support */ + A_UINT32 opaque_debug_num_group_key_enabled; + /* Contains the value of delete all peer command flags */ + A_UINT32 opaque_debug_delete_all_peer_flags; + /* Contains the value of Keepalive ARP sender address time */ + A_UINT32 opaque_debug_keepalive_arp_sender_ipv4; + /* Contains the value of Keepalive ARP Target address time */ + A_UINT32 opaque_debug_keepalive_arp_target_ipv4; + /* Contains the value of Keepalive interval duration time */ + A_UINT32 opaque_debug_keepalive_interval; + /* Contains the value of Keepalive start timer timestamp */ + A_UINT32 opaque_debug_keepalive_timer_start_timestamp; + /* Contains the value of max idle interval and status of STA */ + A_UINT32 opaque_debug_sta_maxidle_interval; + A_UINT32 opaque_debug_sta_maxidle_method; + /* Contains the value of Timing synchronization function (TSF) time diff */ + A_UINT32 opaque_debug_tsf_curr_time_diff; + /* opaque_debug_sleep_duration_us: + * Contains the value of Time in microsends to detect sleep duration + * of the client. + */ + A_UINT32 opaque_debug_sleep_duration_us; + /* Contains the value of pause start time and to calculate pause delay */ + A_UINT32 opaque_debug_pause_start_time_us; + A_UINT32 opaque_debug_pause_delay_us; + /* Contains the value of number of supported group key */ + A_UINT32 opaque_debug_num_supported_group_key; + /* opaque_debug_avg_data_null_tx_delay: + * Contains the value of Average time taken to calculate data frame + * tx delay. + */ + A_UINT32 opaque_debug_avg_data_null_tx_delay; + /* opaque_debug_avg_rx_leak_window: + * Contains the value of Average time taken to calculate data frame + * in receive window. + */ + A_UINT32 opaque_debug_avg_rx_leak_window; + /* Contains the value of count for number of received deauth frames */ + A_UINT32 opaque_debug_num_recv_deauth; + /* Contains the value of Beacon interval in microseconds */ + A_UINT32 opaque_debug_bcn_intval_us; + /* opaque_debug_fils_period + * Contains the value of us, period configured through + * WMI_ENABLE_FILS_CMDID. + */ + A_UINT32 opaque_debug_fils_period; + /* Contains the value of previous Timing synchronization function (TSF) */ + A_UINT32 opaque_debug_prev_tsf; + /* Contains the value of time taken during client sleep */ + A_UINT32 opaque_debug_sleep_entry_time; + /* Contains the value of Total sleep duration from wal_vdev */ + A_UINT32 opaque_debug_tot_sleep_dur; + /* Contains the value of Vdev pause bitmap from wal_vdev */ + A_UINT32 opaque_debug_pause_bitmap; + /* opaque_debug_last_send_to_host_deauth_tsf: + * Contains the value of Last TSF time last_send_to_host_deauth_tsf + * from wlan_vdev. + */ + A_UINT32 opaque_debug_last_send_to_host_deauth_tsf; + /* Contains the value of debug_short_ssid from wlan_vdev */ + A_UINT32 opaque_debug_short_ssid; + /* Bitfield macro's expansion variables */ + /* opaque_debug_vdev_amsdu_bitfield: + * bit 7:0 - Contains the value of dis_dyn_bw_rts from wlan_vdev, + * 15:8 - max_amsdu, + * 23:16 - def_amsdu, + * 31:24 - he_bss_color + */ + A_UINT32 opaque_debug_vdev_amsdu_bitfield; + /* opaque_debug_vdev_ac_failure_configs: + * bit 7:0 - Contains the value of dhe_def_pe_duratio from wal_vdev, + * 15:8 - minimum_allowed_mcs, + * 23:16 - max_11ac_to_leg_rts_fallback_th, + * 31:24 - max_11ac_rts_consec_failure_th + */ + A_UINT32 opaque_debug_vdev_ac_failure_configs; + /* opaque_debug_vdev_pkt_type_info: + * bit 7:0 - Contains the value of input_pkt_type from wal_vdev, + * 15:8 - recv_pkt_type, + * 23:16 - disable_intra_fwd, + * 31:24 - ps_awake + */ + A_UINT32 opaque_debug_vdev_pkt_type_info; + /* opaque_debug_vdev_ba_param_bitfield: + * bit 7:0 - Contains the value of snr_cal_count from wal_vdev, + * 15:8 - amsdu_auto_enable, + * 23:16 - param_ba_timeout, + * 31:24 - param_ba_buffer_size + */ + A_UINT32 opaque_debug_vdev_ba_param_bitfield; + /* opaque_debug_vdev_aggr_bitfield: + * bit 7:0 - Contains the value of param_amsdu_support from wal_vdev, + * 15:8 - param_ba_retry_max, + * 23:16 - tx_aggr_size, + * 31:24 - rx_aggr_size + */ + A_UINT32 opaque_debug_vdev_aggr_bitfield; + /* opaque_debug_vdev_event_delivery: + * bit 7:0 - Contains the value of tqm_bypass_enabled from wal_vdev, + * 15:8 - wmmac_timer_vote_cnt, + * 23:16 - peer_event_delivery_in_progress, + * 31:24 - vdev_event_delivery_in_progress + */ + A_UINT32 opaque_debug_vdev_event_delivery; + /* opaque_debug_vdev_cap_slot_bitfield: + * bit 7:0 - Contains the value of bcn_max_slot from wal_vdev, + * 15:8 - bcn_curr_slot, + * 23:16 - mgmt_tx_power, + * 31:24 - mbssid_capable_association + */ + A_UINT32 opaque_debug_vdev_cap_slot_bitfield; + /* opaque_debug_vdev_bcn_configs: + * bit 7:0 - Contains the value of mbssid_txbssid_association from + * wal_vdev, + * 15:8 - consec_beacon_skip, + * 23:16 - consec_beacon_skip_cnt, + * 31:24 - max_consec_beacon_skip + */ + A_UINT32 opaque_debug_vdev_bcn_configs; + /* Contains the value of opaque_debug_vdev_cmd_info */ + A_UINT32 opaque_debug_vdev_cmd_info; + /* opaque_debug_vdev_mac_configs: + * bit 7:0 - Contains the value of pause_cnt from wlan_vdev, + * 15:8 - e_mac_id, + * 23:16 - is_transmit_bssid, + * 31:24 - rts_rc_flag + */ + A_UINT32 opaque_debug_vdev_mac_configs; + /* opaque_debug_vdev_mode_configs: + * bit 7:0 - Contains the value of ic_opmode from wlan_vdev, + * 15:8 - ic_subopmode, + * 23:16 - ic_curmode, + * 31:24 - vdev_up_cmd_cnt + */ + A_UINT32 opaque_debug_vdev_mode_configs; + /* opaque_debug_vdev_keepalive_bitfields: + * bit 7:0 - keepalive_method + * 15:8 - keepalive_prohibit_data_mgmt + * 23:16 - resp_type + * 31:24 - ap_detect_out_of_sync_sleeping_sta_time_secs + */ + A_UINT32 opaque_debug_vdev_keepalive_bitfields; + /* opaque_debug_vdev_bcn_drift_info: + * bit 7:0 - bcn_drift_cnt + * 15:8 - bcn_drift_calibration + * 23:16 - rts_cts_default + * 31:24 - vdev_down_cmd_cnt + */ + A_UINT32 opaque_debug_vdev_bcn_drift_info; + /* opaque_debug_vdev_arp_configs: + * bit 7:0 - Contains the value of tbtt_link_type from wlan_vdev, + * 15:8 - is_arp_in_air, + * 23:16 - is_ns_in_air, + * 31:24 - num_of_keepalive_attempts + */ + A_UINT32 opaque_debug_vdev_arp_configs; + /* opaque_debug_vdev_streams_configs: + * bit 7:0 - n_beacons_since_last_rssi_report + * 15:8 - num_ofld_peer_alloced + * 23:16 - preferred_tx_streams + * 31:24 - preferred_rx_streams + */ + A_UINT32 opaque_debug_vdev_streams_configs; + /* opaque_debug_vdev_chains_configs: + * bit 7:0 - Contains the value of preferred_tx_streams_160 from + * wlan_vdev, + * 15:8 - preferred_rx_streams_160, + * 23:16 - tx_chains_num_11b, + * 31:24 - tx_chains_num_11ag + */ + A_UINT32 opaque_debug_vdev_chains_configs; + /* opaque_debug_vdev_power_cap_configs: + * bit 7:0 - Contains the value of supp_op_cls_ie_len from wlan_vdev, + * 15:8 - rm_en_cap_ie_len, + * 23:16 - power_cap_ie_len, + * 31:24 - supp_channel_ie_len + */ + A_UINT32 opaque_debug_vdev_power_cap_configs; + /* opaque_debug_vdev_wmm_mbo_configs: + * bit 7:0 - Contains the value of wmm_tspec_ie_len from wlan_vdev, + * 15:8 - ccx_version_ie_len, + * 23:16 - extn_dh_ie_len, + * 31:24 - mbo_ie_len + */ + A_UINT32 opaque_debug_vdev_wmm_mbo_configs; + /* opaque_debug_vdev_remote_configs: + * bit 7:0 - Contains the value of rsnxe_ie_len from wlan_vdev, + * 15:8 - remote_peer_cnt + * 23:16 - p2p_cli_pause_type + * 31:24 - mu_edca_update_count + */ + A_UINT32 opaque_debug_vdev_remote_configs; + /* opaque_debug_vdev_stats_id_configs: + * bit 7:0 - vdev_stats_id + * 15:8 - vdev_stats_id_valid + * 23:16 - preferred_tx_streams_320 + * 31:24 - preferred_rx_streams_320 + */ + A_UINT32 opaque_debug_vdev_stats_id_configs; + /* opaque_debug_vdev_assoc_peer_configs: + * bit 7:0 - unused / reserved + * 15:8 - group_cipher + * 31:16 - assoc_id + */ + A_UINT32 opaque_debug_vdev_assoc_peer_configs; + /* opaque_debug_vdev_mhz_fils_configs: + * bit 15:0 - Contains the value of bss_channel_mhz from wal_vdev, + * 31:16 - config_fils_period + */ + A_UINT32 opaque_debug_vdev_mhz_fils_configs; + /* opaque_debug_vdev_fils_period: + * bit 15:0 - Contains the value of calc_fils_period from wal_vdev, + * 31:16 - ic_txseqs_cmn + */ + A_UINT32 opaque_debug_vdev_fils_period; + /* opaque_debug_vdev_inactive_time: + * bit 15:0 - Contains the value of + * ap_keepalive_min_idle_inactive_time_secs from wlan_vdev, + * 31:16 - ap_keepalive_max_idle_inactive_time_secs + */ + A_UINT32 opaque_debug_vdev_inactive_time; + /* opaque_debug_vdev_chain_mask_configs: + * bit 15:0 - Contains the value of + * ap_keepalive_max_unresponsive_time_secs from wlan_vdev, + * 31:16 - chain_mask + */ + A_UINT32 opaque_debug_vdev_chain_mask_configs; + /* opaque_debug_vdev_ie_len_configs: + * bit 15:0 - num_mcast_filters + * 31:16 - ext_cap_ie_len + */ + A_UINT32 opaque_debug_vdev_ie_len_configs; + /* opaque_debug_vdev_fils_configs: + * bit 15:0 - Contains the value of fils_channel_guard_time from wlan_vdev, + * 31:16 - fd_tmpl_len + */ + A_UINT32 opaque_debug_vdev_fils_configs; + /* opaque_debug_vdev_chan_configs: + * bit 15:0 - Contains the value of common_rsn_caps from wlan_vdev, + * 31:16 - off_ch_active_dwell_time + */ + A_UINT32 opaque_debug_vdev_chan_configs; + /* opaque_debug_vdev_dwell_configs: + * bit 15:0 - Contains the value of off_ch_passive_dwell_time from + * wlan_vdev, + * 31:16 - current_pause_request_id + */ + A_UINT32 opaque_debug_vdev_dwell_configs; + /* opaque_debug_vdev_wmi_configs: + * bit 0 - Contains the value of hide_ssid_enable from wlan_vdev, + * 1 - b_none_protocol_paused + * 2 - dpd_cal_state + * 4 - req_bcn_q_unpause + * 5 - bt_coex_enable_cts2s + * 6 - dpd_delay_n_beacon + * 8 - b_need_check_first_beacon + * 9 - ap_peer_keepalive_max_idle_time_reached + * 10 - leakyap_cts2s_enable + * 11 - stasapscc_in_mcc + * 12 - stasapscc_in_mcc_cts2s_enable + * 13 - is_vdev_stopping + * 14 - is_wmi_vdev_down + * 15 - is_vdev_down_pending + * 16 - vdev_delete_in_progress + * 17 - cac_enabled + * 18 - is_quaterrate + * 19 - is_halfrate + * 20 - stop_resp_event_blocked + * 21 - use_enhanced_mcast_filter + * 22 - is_start_pending_on_asm + * 23 - no_null_to_ap_for_roaming + * 24 - is_loopback_cal_pending + * 25 - vdev_delete_acked + * 26 - bc_proberesp_enable + * 27 - is_wmm_param + * 28 - is_connect_in_progress + * 29 - is_mu_edca_param + * 30 - send_del_resp_tohost + * 31 - is_restart_different_ch + */ + A_UINT32 opaque_debug_vdev_wmi_configs; + /* opaque_debug_vdev_hu_mu_configs: + * bit 0 - Contains the value of proto_ps_status from wlan_vdev, + * 1 - smps_intolerant + * 2 - is_offload_registered_for_connection + * 3 - is_bss_beacon_offload_registered + * 4 - is_prob_resp_offload_registered + * 5 - is_ibss_beacon_offload_registered + * 6 - is_keepalive_attempts_exhausted + * 7 - is_bcn_tx_ie_changed_log + * 8 - he_su_bfee + * 9 - he_su_bfer + * 10 - he_mu_bfee + * 11 - he_mu_bfer + * 12 - he_dl_ofdma + * 13 - he_ul_ofdma + * 14 - he_ul_mumimo + * 15 - ul_mu_resp + * 23:16 - alt_rssi_non_srg + * 31:24 - alt_rssi_srg + */ + A_UINT32 opaque_debug_vdev_hu_mu_configs; + /* opaque_debug_vdev_sm_chan_configs: + * bit 0 - Contains the value of he_bss_color_en from wlan_vdev, + * 1 - he_txbf_ofdma + * 2 - non_srg_enable + * 3 - srg_enable + * 4 - srp_enable + * 5 - sr_initialized + * 6 - sr_rings_initialized + * 10:7 - per_ac_obss_pd_enable + * 11 - ifup + * 12 - ifactive + * 13 - ifpaused + * 14 - ifoutofsync + * 15 - is_free + * 16 - is_nawds + * 17 - hw_flag + * 18 - ch_req_flag + * 20 - restart_resp + * 21 - first_beacon_recv_wait + * 22 - erpenabled + * 23 - start_responded + * 24 - bcn_sync_crit_req_act + * 25 - recal_notif_registered + * 26 - bcn_tx_paused + * 27 - he_bss_color_en_bypass + * 28 - default_ba_mode + * 29 - ba_256_bitmap_enable + * 30 - ba_256_bitmap_tx_disable + * 31 - is_multi_group_key_enabled + */ + A_UINT32 opaque_debug_vdev_sm_chan_configs; + /* + * The following 4 opaque_debug variables are provided purely for + * debugging by technicians who have outside knowledge of what kind of + * values the target has placed into these fields. + * The host must not interpret the values of these fields, since the + * meaning of the values provided in these fields may change without + * regard for backwards compatibility or interoperability. + */ + A_UINT32 opaque_debug_field_1; + A_UINT32 opaque_debug_field_2; + A_UINT32 opaque_debug_field_3; + A_UINT32 opaque_debug_field_4; } wmi_vdev_extd_stats; + +#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_MAX_AMSDU_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_MAX_AMSDU_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_DEF_AMSDU_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_DEF_AMSDU_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_HW_BSS_COLOR_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_HW_BSS_COLOR_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_INPUT_PKT_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_INPUT_PKT_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_RECV_PKT_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_RECV_PKT_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PS_AWAKE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PS_AWAKE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_SNR_CAL_COUNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_SNR_CAL_COUNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_TX_AGGR_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_TX_AGGR_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RX_AGGR_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RX_AGGR_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_MAX_SLOT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_MAX_SLOT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_CURR_SLOT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_CURR_SLOT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_MGMT_TX_POWER_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_MGMT_TX_POWER_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PAUSE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PAUSE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_E_MAC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_E_MAC_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_RC_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_RC_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_IC_OPMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_IC_OPMODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_IC_SUBOPMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_IC_SUBOPMODE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IC_CURMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IC_CURMODE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_KEEPALIVE_METHOD_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_KEEPALIVE_METHOD_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_RESP_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_RESP_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_TBTT_LINK_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_TBTT_LINK_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_IS_ARP_IN_AIR_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_IS_ARP_IN_AIR_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IS_NS_IN_AIR_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IS_NS_IN_AIR_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MBO_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MBO_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_RSNXE_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_RSNXE_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_REMOTE_PEER_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_ID_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_ID_VALID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +/* bits 7:0 unused / reserved */ +#define WMI_VDEV_STATS_GROUP_CIPHER_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_GROUP_CIPHER_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_ASSOC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_ASSOC_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_CALC_FILS_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_CALC_FILS_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_IC_TXSEQS_CMN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_IC_TXSEQS_CMN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_FD_TMPL_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_FD_TMPL_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_COMMON_RSN_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_COMMON_RSN_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_DPD_CAL_STATE_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 2, val) +#define WMI_VDEV_STATS_DPD_CAL_STATE_GET(flag) \ + WMI_GET_BITS(flag, 2, 2) +#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 2, val) +#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_GET(flag) \ + WMI_GET_BITS(flag, 6, 2) +#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_IS_VDEV_STOPPING_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_IS_VDEV_STOPPING_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_VDEV_STATS_CAC_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_VDEV_STATS_CAC_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_VDEV_STATS_IS_QUATERRATE_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 1, val) +#define WMI_VDEV_STATS_IS_QUATERRATE_GET(flag) \ + WMI_GET_BITS(flag, 18, 1) +#define WMI_VDEV_STATS_IS_HALFRATE_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 1, val) +#define WMI_VDEV_STATS_IS_HALFRATE_GET(flag) \ + WMI_GET_BITS(flag, 19, 1) +#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_SET(flag, val) \ + WMI_SET_BITS(flag, 23, 1, val) +#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_GET(flag) \ + WMI_GET_BITS(flag, 23, 1) +#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) +#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) + +#define WMI_VDEV_STATS_PROTO_PS_STATUS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_PROTO_PS_STATUS_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_SMPS_INTOLERANT_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_SMPS_INTOLERANT_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) +#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_GET(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define WMI_VDEV_STATS_HE_SU_BFEE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_VDEV_STATS_HE_SU_BFEE_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_VDEV_STATS_HE_SU_BFER_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_VDEV_STATS_HE_SU_BFER_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_VDEV_STATS_HE_MU_BFEE_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_VDEV_STATS_HE_MU_BFEE_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_VDEV_STATS_HE_MU_BFER_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_HE_MU_BFER_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_HE_DL_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_HE_DL_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_HE_UL_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_HE_UL_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_HE_UL_MUMIMO_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_HE_UL_MUMIMO_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_UL_MU_RESP_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_UL_MU_RESP_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_ALT_RSSI_SRG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_ALT_RSSI_SRG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_HE_TXBF_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_HE_TXBF_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_NON_SRG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_VDEV_STATS_NON_SRG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_VDEV_STATS_SRG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_VDEV_STATS_SRG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_VDEV_STATS_SRP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_SRP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_SR_INITIALIZED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_SR_INITIALIZED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 4, val) +#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 7, 4) +#define WMI_VDEV_STATS_IFUP_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_IFUP_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_IFACTIVE_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_IFACTIVE_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_IFPAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_IFPAUSED_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_IFOUTOFSYNC_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_IFOUTOFSYNC_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_IS_FREE_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_IS_FREE_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_IS_NAWDS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_VDEV_STATS_IS_NAWDS_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_VDEV_STATS_HW_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_VDEV_STATS_HW_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_VDEV_STATS_CH_REQ_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 2, val) +#define WMI_VDEV_STATS_CH_REQ_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 18, 2) +#define WMI_VDEV_STATS_RESTART_RESP_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_VDEV_STATS_RESTART_RESP_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_VDEV_STATS_ERPENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_VDEV_STATS_ERPENABLED_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +#define WMI_VDEV_STATS_START_RESPONDED_SET(flag, val) \ + WMI_SET_BITS(flag, 23, 1, val) +#define WMI_VDEV_STATS_START_RESPONDED_GET(flag) \ + WMI_GET_BITS(flag, 23, 1) +#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_VDEV_STATS_BCN_TX_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_VDEV_STATS_BCN_TX_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_VDEV_STATS_DEFAULT_BA_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_VDEV_STATS_DEFAULT_BA_MODE_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) +#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) + + /** * peer statistics. */ @@ -13044,6 +15825,8 @@ typedef struct { #define WMI_MLO_FLAGS_SET_LINK_ADD(mlo_flags, value) WMI_SET_BITS(mlo_flags, 8, 1, value) #define WMI_MLO_FLAGS_GET_LINK_DEL(mlo_flags) WMI_GET_BITS(mlo_flags, 9, 1) #define WMI_MLO_FLAGS_SET_LINK_DEL(mlo_flags, value) WMI_SET_BITS(mlo_flags, 9, 1, value) +#define WMI_MLO_FLAGS_GET_BRIDGE_PEER(mlo_flags) WMI_GET_BITS(mlo_flags, 10, 1) +#define WMI_MLO_FLAGS_SET_BRIDGE_PEER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 10, 1, value) /* this structure used for pass mlo flags*/ typedef struct { @@ -13059,7 +15842,8 @@ typedef struct { mlo_force_link_inactive:1, /* indicate this link is forced inactive */ mlo_link_add:1, /* Indicate dynamic link addition in an MLD VAP */ mlo_link_del:1, /* Indicate dynamic link deletion in an MLD VAP */ - unused: 22; + mlo_bridge_peer:1, /* Indicate if this link has bridge_peer */ + unused: 21; }; A_UINT32 mlo_flags; }; @@ -15095,6 +17879,17 @@ typedef enum { */ WMI_VDEV_PARAM_DISABLE_LPI_ANT_OPTIMIZATION, /* 0xB9 */ + /* + * Param to update connected VDEV channel bandwidth. + * Target firmware should take care of notifying associated peers + * (except TDLS) about change in bandwidth, through OMN/OMI notification + * before performing bandwidth update internally. + * Please note incase of STA VDEV only BSS peer gets updated, + * associated TDLS peer bandwidth wont be impacted. + * + * The the updated bandwith is specified with a wmi_channel_width value. + */ + WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */ /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === @@ -15204,17 +17999,19 @@ typedef enum { WMI_VDEV_PARAM_MCAST_STEERING, /* 0x800E */ /* - * 0 - XPAN disabled - * 1 - XPAN Lossless audio profile - * 2 - XPAN Gaming profile + * bit 0: 0 - XR SAP profile disabled + * 1 - XR SAP profile enabled + * bit 1: 0 - XPAN profile disabled + * 1 - XPAN profile enabled + * bits 31:2 - reserved */ - WMI_VDEV_PARAM_XPAN_PROFILE, /* 0x800F */ + WMI_VDEV_PARAM_SET_PROFILE, /* 0x800F */ /* * for valid vdev id * for vdev offload stats */ - WMI_VDEV_PARAM_VDEV_STATS_ID_UPDATE, /* 0x8010 */ + WMI_VDEV_PARAM_VDEV_STATS_ID_UPDATE, /* 0x8010 */ /* * Enable or disable Extra LTF capability in Auto rate and @@ -15253,6 +18050,13 @@ typedef enum { */ WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES, /* 0x8012 */ + /* + * SAP Power save with TWT vdev param command + * 0 - Disable SAP Power save TWT + * 1 - Enable SAP Power save TWT + */ + WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT, /* 0x8013 */ + /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; @@ -16649,6 +19453,7 @@ enum wmi_peer_type { WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */ WMI_PEER_TYPE_PASN = 6, /* Peer is used for Pre-Association Security Negotiation */ + WMI_PEER_TYPE_BRIDGE = 7, /* For creating Dummy Peer in case of 4 Link MLO */ WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ /* Reserved from 128 - 255 for target internal use.*/ WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ @@ -17124,7 +19929,8 @@ typedef struct { #define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_CHWIDTH(value32) WMI_GET_BITS(value32, 0x0, 8) #define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_PUNCTURE_BMAP(value32) WMI_GET_BITS(value32, 0x8, 16) -/* peer channel bandwidth and puncture_bitmap +/* + * peer channel bandwidth and puncture_bitmap * BIT 0-7 - Peer channel width * This bitfield holds a wmi_channel_width enum value. * BIT 8-23 - Peer Puncture bitmap where each bit indicates whether @@ -17137,7 +19943,6 @@ typedef struct { #define WMI_PEER_SET_TX_POWER 0x28 - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -17409,6 +20214,8 @@ typedef struct { A_UINT32 tlv_header; /** TLV tag (MITLV_TAG_STRUC_wmi_peer_assoc_mlo_partner_link_params) and len */ A_UINT32 vdev_id; /** unique id identifying the VDEV, generated by the caller */ A_UINT32 hw_mld_link_id; /** Unique link id across SOCs, got as part of QMI handshake. */ + wmi_mlo_flags mlo_flags; /** MLO flags */ + A_UINT32 logical_link_index; /** Unique index for links of the mlo. Starts with Zero */ } wmi_peer_assoc_mlo_partner_link_params; /* This TLV structure used to pass mlo Parameters on peer assoc, only apply for mlo-peers */ @@ -17433,8 +20240,13 @@ typedef struct { A_UINT32 emlsr_trans_delay_us; /** eMLSR padding delay in microseconds */ A_UINT32 emlsr_padding_delay_us; - /** Medium Synchronization Duration in microseconds */ - A_UINT32 msd_dur_us; + union { + /** Medium Synchronization Duration field in units of 32 microseconds */ + A_UINT32 msd_dur_subfield; + /** DEPRECATED - DO NOT USE. + * Medium Synchronization Duration in microseconds */ + A_UINT32 msd_dur_us; + }; /** Medium Synchronization OFDM ED Threshold */ A_UINT32 msd_ofdm_ed_thr; /** Medium Synchronization Max Num of TXOPs */ @@ -17727,9 +20539,18 @@ typedef struct { /** * Following this structure is the optional TLV: * struct wmi_scan_blanking_params_info[0/1]; + * struct wmi_cca_busy_subband_info[]; + * Reporting subband CCA busy info in host requested manner. */ } wmi_chan_info_event_fixed_param; +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cca_busy_subband_info */ + A_UINT32 tlv_header; + /** rx clear count */ + A_UINT32 rx_clear_count; +} wmi_cca_busy_subband_info; + /** * The below structure contains parameters related to the scan radio * blanking feature @@ -19170,6 +21991,12 @@ typedef struct { A_UINT32 timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 original_timeout; + /* + * If disallow_linkid_bitmap is not 0, then means current entity + * is for MLD AP and bssid field is standing for MLD address. + * If all links for MLD AP is disallow, then the value shall be 0xffffffff + */ + A_UINT32 disallow_linkid_bitmap; } wmi_roam_blacklist_with_timeout_tlv_param; /** WMI_ROAM_BLACKLIST_EVENT: generated whenever STA needs to move AP to blacklist for a particluar time @@ -20143,6 +22970,8 @@ typedef enum wake_reason_e { WOW_REASON_SCHED_PM_TERMINATED, /* XGAP entry/exit response */ WOW_REASON_XGAP, + /* COEX channel avoid event */ + WOW_REASON_COEX_CHAVD, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, @@ -20199,6 +23028,48 @@ typedef enum { WMI_WOW_RESUME_FLAG_TX_DATA = 0x00000001, /* TX data pending to be sent in resume */ } WMI_WOW_RESUME_FLAG_ENUM; +/* wow nack reason codes */ +typedef enum { + /* WoW error due to unnkown reason */ + WMI_WOW_NON_ACK_REASON_UNKNOWN = 0, + + /* WoW error due to TX failure */ + WMI_WOW_NON_ACK_REASON_TX = 1, + + /* WoW error due to some data blocked */ + WMI_WOW_NON_ACK_REASON_IS_BLOCK = 2, + + /* WoW error in WFA mode */ + WMI_WOW_NON_ACK_REASON_NOT_ALLOW = 3, + + /* WoW error mac operation fail */ + WMI_WOW_NON_ACK_REASON_HW_FAIL = 4, + + /* WoW error due to timeout */ + WMI_WOW_NON_ACK_REASON_TIMEOUT = 5, + + /* WoW error due to RTT or CFR capture active */ + WMI_WOW_NON_ACK_REASON_RTT_DMA = 6, + + /* WoW error due to roam module holding lock */ + WMI_WOW_NON_ACK_REASON_ROAM = 7, + + /* WoW error remote peer not sleeping */ + WMI_WOW_NON_ACK_REASON_PEER_ACTIVE = 8, + + /* WoW error due to WoW entry defer failed */ + WMI_WOW_NON_ACK_REASON_DEFER_FAILURE = 9, + + /* WoW error due to WoW entry defer timeout */ + WMI_WOW_NON_ACK_REASON_DEFER_TIMEOUT = 10, + + /* WoW error due to FATAL event */ + WMI_WOW_NON_ACK_REASON_FATAL_EVENT = 11, + + /* WoW error if close to TBTT */ + WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12, +} WMI_WOW_NACK_STATUS; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */ /* reserved0: @@ -22033,12 +24904,37 @@ typedef struct { A_UINT32 set; /* Set the GPIO pin*/ } wmi_gpio_output_cmd_fixed_param; +/* WMI_GPIO_STATE_REQ_CMDID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param */ + A_UINT32 gpio_num; /* GPIO number to get state */ +} wmi_gpio_state_req_cmd_fixed_param; + /* WMI_GPIO_INPUT_EVENTID */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param */ A_UINT32 gpio_num; /* GPIO number which changed state */ } wmi_gpio_input_event_fixed_param; +typedef enum { + /** + * The following wmi_gpio_state_type is mutually exclusive. + * 0: gpio_invalid_state + * 1: gpio_state is LO + * 2: gpio_state is HIGH + */ + WMI_GPIO_STATE_INVALID, /* GPIO state is invalid. */ + WMI_GPIO_STATE_LOW, /* GPIO state is low. */ + WMI_GPIO_STATE_HIGH, /* GPIO state is high. */ +} WMI_GPIO_STATE_TYPE; + +/* WMI_GPIO_STATE_RES_EVENTID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param */ + A_UINT32 gpio_num; /* GPIO number */ + A_UINT32 gpio_state; /* state of GPIO pin defined in WMI_GPIO_STATE_TYPE 0 invalid 1 - LO, 2 -HI*/ +} wmi_gpio_state_res_event_fixed_param; + /* WMI_ANT_CONTROLLER_CMDID */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param */ @@ -22603,7 +25499,8 @@ typedef struct { enum wmi_tdls_offchan_mode { WMI_TDLS_ENABLE_OFFCHANNEL, - WMI_TDLS_DISABLE_OFFCHANNEL + WMI_TDLS_DISABLE_OFFCHANNEL, /* passive offchannel disable */ + WMI_TDLS_ACTIVE_DISABLE_OFFCHANNEL, }; typedef struct { @@ -22625,6 +25522,9 @@ typedef struct { A_UINT32 offchan_oper_class; /* off channel frequency in MHz */ A_UINT32 offchan_freq; +/** This fixed_param TLV is followed by the below additional TLVs: + * - wmi_channel peer_chan_info[]: optional per-peer chan_info + */ } wmi_tdls_set_offchan_mode_cmd_fixed_param; @@ -24786,6 +27686,10 @@ typedef struct { A_UINT32 tlv_header; /** NDP instance id */ A_UINT32 ndp_instance_id; + /** vdev_id valid flag */ + A_UINT32 vdev_id_valid; + /** vdev id */ + A_UINT32 vdev_id; } wmi_ndp_end_req_PROTOTYPE; #define wmi_ndp_end_req wmi_ndp_end_req_PROTOTYPE @@ -25585,12 +28489,24 @@ typedef struct { */ } wmi_stats_ext_event_fixed_param; +typedef enum { + /** Default: no replay required. */ + WMI_PEER_DELETE_NO_REPLAY = 0, + /** + * Replay requested due to UMAC hang during Peer delete. + * Replay done by Host SW after MLO UMAC SSR recovered the UMAC. + */ + WMI_PEER_DELETE_REPLAY_FOR_UMAC, +} WMI_PEER_DELETE_REPLAY_T; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** peer MAC address */ wmi_mac_addr peer_macaddr; + /** WMI_PEER_DELETE_REPLAY_T */ + A_UINT32 replay_type; } wmi_peer_delete_resp_event_fixed_param; typedef struct { @@ -25605,6 +28521,8 @@ typedef struct { * 2 - EFAILED; Delete all peer failed */ A_UINT32 status; + /** WMI_PEER_DELETE_REPLAY_T */ + A_UINT32 replay_type; } wmi_vdev_delete_all_peer_resp_event_fixed_param; typedef struct { @@ -29117,6 +32035,42 @@ typedef struct { A_UINT32 antenna_series; } wmi_peer_smart_ant_set_tx_antenna_series; +#define WMI_PER_VALID_BIT_POS 0 +#define WMI_PER_VALID_NUM_BITS 1 + +#define WMI_GET_PER_VALID(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_VALID_BIT_POS, WMI_PER_VALID_NUM_BITS) + +#define WMI_PER_VALID_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_VALID_BIT_POS, WMI_PER_VALID_NUM_BITS, value) + +#define WMI_PER_THRESHOLD_BIT_POS 1 +#define WMI_PER_THRESHOLD_NUM_BITS 8 + +#define WMI_GET_PER_THRESHOLD(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_THRESHOLD_BIT_POS, WMI_PER_THRESHOLD_NUM_BITS) + +#define WMI_PER_THRESHOLD_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_THRESHOLD_BIT_POS, WMI_PER_THRESHOLD_NUM_BITS, value) + +#define WMI_PER_MIN_TX_PKTS_BIT_POS 9 +#define WMI_PER_MIN_TX_PKTS_NUM_BITS 16 + +#define WMI_GET_PER_MIN_TX_PKTS(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS) + +#define WMI_PER_MIN_TX_PKTS_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS, value) + +#define WMI_RATE_SERIES_320_BIT_POS 0 +#define WMI_RATE_SERIES_320_NUM_BITS 16 + +#define WMI_GET_RATE_SERIES_320(train_rate_series_ext) \ + WMI_GET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS) + +#define WMI_SET_RATE_SERIES_320(train_rate_series_ext) \ + WMI_SET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */ /* rate array */ @@ -29138,6 +32092,11 @@ typedef struct { A_UINT32 rc_flags; /* rate array -- continued */ A_UINT32 train_rate_series_hi; /* Higher 32 bits of rate array */ + /* train_rate_series_ext: + * 15:0 - 320Mhz rate + * 31:16 - Reserved + */ + A_UINT32 train_rate_series_ext; /* For 320Mhz and Reserved for other */ } wmi_peer_smart_ant_set_train_antenna_param; typedef struct { @@ -29148,10 +32107,19 @@ typedef struct { wmi_mac_addr peer_macaddr; /* num packets; 0-stop training */ A_UINT32 num_pkts; - /* - * Following this structure is the TLV: - * wmi_peer_smart_ant_set_train_antenna_param - */ + /* per_threshold: + * bits | interpretation + * ------+-------------------------- + * 0 | PER Threshold is valid + * 1:8 | Per Threshold + * 9:24 | min_tx_pkts Minimum number of pkts need to be checked + * 25:31 | Reserved + */ + A_UINT32 per_threshold; +/* + * Following this structure is the TLV: + * wmi_peer_smart_ant_set_train_antenna_param + */ } wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param; typedef struct { @@ -29879,6 +32847,16 @@ typedef struct { #define WMI_LATENCY_SET_DISABLE_UL_MU_MIMO(latency_tid_info,val) \ WMI_SET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS, WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS, val) +#define WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS 20 +#define WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS 1 + +#define WMI_LATENCY_GET_SAWF_UL_PARAMS_BIT(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS) + +#define WMI_LATENCY_SET_SAWF_UL_PARAMS_BIT(latency_tid_info, val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS, val) + + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_tid_latency_info @@ -29922,7 +32900,8 @@ typedef struct { */ A_UINT32 min_tput; /* latency_tid_info - * Bits 20-31 - Reserved (Shall be zero) + * Bits 21-31 - Reserved (Shall be zero) + * Bit 20 - Flag to indicate SAWF UL params (and not mesh latency) * Bit 19 - Disable UL MU-MIMO. If set, UL MU-MIMO is disabled * for the specified AC. Note that TID level control is * not possible for UL MU-MIMO (the granularity is AC). @@ -30089,9 +33068,11 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info */ - A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ - A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ - A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ + A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ + A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + A_UINT32 ratecode_160; /* Rate code for 160MHz BW */ + A_UINT32 ratecode_320; /* Rate code for 320MHz BW */ } wmi_peer_mcs_rate_info; typedef struct { @@ -30100,6 +33081,7 @@ typedef struct { A_UINT32 ratecount; /* Max Rate count for each mode */ A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ A_UINT32 pdev_id; /* ID of the pdev this peer belongs to */ + A_UINT32 ratecount_ext; /* Max Rate count for 160, 320MHz */ /* * Following this structure are the TLV: * struct wmi_peer_cck_ofdm_rate_info; @@ -31183,6 +34165,9 @@ typedef enum { WMI_REQUEST_CTRL_PATH_AFC_STAT = 11, WMI_REQUEST_CTRL_PATH_PMLO_STAT = 12, WMI_REQUEST_CTRL_PATH_CFR_STAT = 13, + WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14, + WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15, + WMI_REQUEST_CTRL_PATH_PEER_STAT = 16, } wmi_ctrl_path_stats_id; typedef enum { @@ -31473,6 +34458,16 @@ typedef enum wmi_hw_mode_config_type { * and Tx/Rx trigger on any PHY will switch * from 1x1 to 2x2 on that Phy */ + WMI_HW_MODE_AUX_EMLSR_SINGLE = 9, /* PHYA0 and AUX are active in listen mode + * in 1x1 and Tx/Rx trigger on any. + * PHY will switch from 1x1 to 2x2 + * on that Phy. + */ + WMI_HW_MODE_AUX_EMLSR_SPLIT = 10, /* PHYA1 and AUX are active in listen mode + * in 1x1 and Tx/Rx trigger on any. + * PHY will switch from 1x1 to 2x2 + * on that Phy. + */ } WMI_HW_MODE_CONFIG_TYPE; /* @@ -31652,6 +34647,12 @@ typedef enum wmi_hw_mode_config_type { #define WMI_SUPPORT_AAR_GET(mld_capability) WMI_GET_BITS(mld_capability, 12, 1) #define WMI_SUPPORT_AAR_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 12, 1, value) +/* + * 11BE Ext MLD Capability Set and Get macros + */ +#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_GET(ext_mld_capability) WMI_GET_BITS(ext_mld_capability, 0, 1) +#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_SET(ext_mld_capability, value) WMI_SET_BITS(ext_mld_capability, 0, 1, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, as specified @@ -31927,6 +34928,14 @@ typedef struct { }; A_UINT32 mld_capability; }; + union { + struct { + A_UINT32 + op_update_para_support:1, /* Indicates support of operation parameter update negotiation */ + reserved3: 31; + }; + A_UINT32 ext_mld_capability; + }; } WMI_MAC_PHY_CAPABILITIES_EXT; typedef struct { @@ -32170,9 +35179,9 @@ typedef struct { * The DFS feature is disabled on this scan radio, since there will not be * much TX traffic. * The Host has to disable CAC timer because DFS feature not supported here. - * In order to know about the scan radio RDP and DFS disabled case, - * the target has to send this information to Host per pdev via - * WMI_SERVICE_READY_EXT2_EVENT. + * In order to know about the scan radio RDP, DFS disabled case and + * SCAN BLANKING support, the target has to send this information to Host + * per pdev via WMI_SERVICE_READY_EXT2_EVENT. * The target is notified of the special scan VAP by the flags variable * in the WMI_CREATE_CMD. */ @@ -32186,7 +35195,11 @@ typedef struct { * Bit 1: * 1 - DFS enabled 0 - DFS disabled * Refer to WMI_SCAN_RADIO_CAP_DFS_FLAG_SET, GET macros - * [2:31] reserved + * Bit 2: + * 1 - SCAN RADIO blanking supported + * 0 - SCAN RADIO blanking not supported + * Refer to WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_SET, GET macros + * [3:31] reserved */ A_UINT32 flags; } WMI_SCAN_RADIO_CAPABILITIES_EXT2; @@ -32197,6 +35210,9 @@ typedef struct { #define WMI_SCAN_RADIO_CAP_DFS_FLAG_GET(flag) WMI_GET_BITS(flag, 1, 1) #define WMI_SCAN_RADIO_CAP_DFS_FLAG_SET(flag, val) WMI_SET_BITS(flag, 1, 1, val) +#define WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_GET(flag) WMI_GET_BITS(flag, 2, 1) +#define WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_SET(flag, val) WMI_SET_BITS(flag, 2, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES */ A_UINT32 num_phy; @@ -33237,6 +36253,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_RMC_SET_MANUAL_LEADER_CMDID); WMI_RETURN_STRING(WMI_11D_SCAN_START_CMDID); WMI_RETURN_STRING(WMI_11D_SCAN_STOP_CMDID); + WMI_RETURN_STRING(WMI_VENDOR_PDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */ @@ -33244,6 +36261,13 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_TDMA_SCHEDULE_REQUEST_CMDID); WMI_RETURN_STRING(WMI_HPA_CMDID); WMI_RETURN_STRING(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); /* To set target rate to power table */ + WMI_RETURN_STRING(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); + WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID); + WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ + WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); + WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -34581,12 +37605,15 @@ typedef struct { * requester and broadcast requester. Same way for RESPONDER. * */ +/* 0: requester; 1: responder */ #define TWT_EN_DIS_FLAGS_GET_REQ_RESP(flag) WMI_GET_BITS(flag, 4, 1) #define TWT_EN_DIS_FLAGS_SET_REQ_RESP(flag, val) WMI_SET_BITS(flag, 4, 1, val) +/* 0: iTWT; 1: bTWT */ #define TWT_EN_DIS_FLAGS_GET_I_B_TWT(flag) WMI_GET_BITS(flag, 5, 1) #define TWT_EN_DIS_FLAGS_SET_I_B_TWT(flag, val) WMI_SET_BITS(flag, 5, 1, val) +/* 0: bTWT; 1: rTWT */ #define TWT_EN_DIS_FLAGS_GET_B_R_TWT(flag) WMI_GET_BITS(flag, 6, 1) #define TWT_EN_DIS_FLAGS_SET_B_R_TWT(flag, val) WMI_SET_BITS(flag, 6, 1, val) @@ -34846,6 +37873,8 @@ typedef enum _WMI_ADD_TWT_STATUS_T { WMI_ADD_TWT_STATUS_CHAN_SW_IN_PROGRESS, /* Channel switch in progress */ WMI_ADD_TWT_STATUS_SCAN_IN_PROGRESS, /* Scan in progress */ WMI_ADD_TWT_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */ + WMI_ADD_TWT_STATUS_BTWT_NOT_ENBABLED, /* Broadcast TWT is not enabled */ + WMI_ADD_TWT_STATUS_RTWT_NOT_ENBABLED, /* Restricted TWT is not enabled */ } WMI_ADD_TWT_STATUS_T; typedef struct { @@ -35016,6 +38045,9 @@ typedef struct { A_UINT32 vdev_id; /* VDEV identifier */ wmi_mac_addr peer_macaddr; /* peer MAC address */ A_UINT32 dialog_id; /* TWT dialog ID */ + /* parameters required for R-TWT feature */ + A_UINT32 r_twt_dl_tid_bitmap; + A_UINT32 r_twt_ul_tid_bitmap; } wmi_twt_btwt_invite_sta_cmd_fixed_param; /* status code of inviting STA to B-TWT dialog */ @@ -35043,6 +38075,9 @@ typedef struct { A_UINT32 vdev_id; /* VDEV identifier */ wmi_mac_addr peer_macaddr; /* peer MAC address */ A_UINT32 dialog_id; /* TWT dialog ID */ + /* parameters required for R-TWT feature */ + A_UINT32 r_twt_dl_tid_bitmap; + A_UINT32 r_twt_ul_tid_bitmap; } wmi_twt_btwt_remove_sta_cmd_fixed_param; /* status code of removing STA from B-TWT dialog */ @@ -35068,6 +38103,7 @@ typedef struct { typedef enum { WMI_DMA_RING_CONFIG_MODULE_SPECTRAL, WMI_DMA_RING_CONFIG_MODULE_RTT, + WMI_DMA_RING_CONFIG_MODULE_CV_UPLOAD, } WMI_DMA_RING_SUPPORTED_MODULE; typedef struct { @@ -35226,6 +38262,7 @@ typedef struct { /* This TLV is followed by another TLV of array of structs. * wmi_dma_buf_release_entry entries[num_buf_release_entry]; * wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry]; + * wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry] */ } wmi_dma_buf_release_fixed_param; @@ -35577,6 +38614,12 @@ typedef struct { A_UINT32 timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 original_timeout; + /* + * If disallow_linkid_bitmap is not 0, then means current entity + * is for MLD AP and bssid field is standing for MLD address. + * If all links for MLD AP is disallow, then the value shall be 0xffffffff + */ + A_UINT32 disallow_linkid_bitmap; } wmi_pdev_bssid_disallow_list_config_param; typedef enum { @@ -35838,9 +38881,9 @@ typedef struct { /* btm_req_dialog_token: dialog token number in BTM request frame */ A_UINT32 btm_req_dialog_token; /* data RSSI in dBm when abort to roam scan */ - A_UINT32 data_rssi; + A_INT32 data_rssi; /* data RSSI threshold in dBm */ - A_UINT32 data_rssi_threshold; + A_INT32 data_rssi_threshold; /* rx linkspeed status, 0:good linkspeed, 1:bad */ A_UINT32 rx_linkspeed_status; } wmi_roam_trigger_reason; @@ -35962,6 +39005,11 @@ typedef enum { WMI_ROAM_FAIL_REASON_SAE_PREAUTH_FAIL, /* WPA3-SAE pre-authentication failed */ WMI_ROAM_FAIL_REASON_UNABLE_TO_START_ROAM_HO, /* Roam HO is not started due to FW internal issue */ + /* Failure reasons to indicate no candidate and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_NO_AP_FOUND_AND_FINAL_BMISS_SENT, /* No roamable APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT, /* No candidate APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */ + WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; @@ -38438,7 +41486,20 @@ typedef struct { #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 1, 1) #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value) -/* Bits 66-71: reserved */ +/* Bit 66: 20Mhz-only limited capabilities support */ +#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value) + +/* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */ +#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value) + +/* Bit 68: 20Mhz-only M-RU support */ +#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value) + + +/* Bits 69-71: reserved */ /****** End of 11BE EHT PHY Capabilities Information field ******/ @@ -40214,6 +43275,9 @@ typedef struct { #define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_GET(_var) WMI_GET_BITS(_var, 22, 1) #define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_SET(_var, _val) WMI_SET_BITS(_var, 22, 1, _val) +#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_GET(_var) WMI_GET_BITS(_var, 23, 1) +#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_SET(_var, _val) WMI_SET_BITS(_var, 23, 1, _val) + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_session_stats_info */ A_UINT32 tlv_hdr; @@ -40257,7 +43321,7 @@ typedef struct { typedef struct wmi_pdev_vendor_event { - /* type is WMI_PDEV_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40271,10 +43335,11 @@ typedef struct wmi_pdev_vendor_event * would change, causing backwards incompatibilities. */ } wmi_pdev_vendor_event_fixed_param; +typedef wmi_pdev_vendor_event_fixed_param wmi_vendor_pdev_event_fixed_param; typedef struct wmi_vdev_vendor_event { - /* type is WMI_VDEV_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40290,10 +43355,11 @@ typedef struct wmi_vdev_vendor_event * would change, causing backwards incompatibilities. */ } wmi_vdev_vendor_event_fixed_param; +typedef wmi_vdev_vendor_event_fixed_param wmi_vendor_vdev_event_fixed_param; typedef struct wmi_peer_vendor_event { - /* type is WMI_PEER_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40311,10 +43377,11 @@ typedef struct wmi_peer_vendor_event * would change, causing backwards incompatibilities. */ } wmi_peer_vendor_event_fixed_param; +typedef wmi_peer_vendor_event_fixed_param wmi_vendor_peer_event_fixed_param; typedef struct wmi_pdev_vendor_cmd { - /* type is WMI_PDEV_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40328,10 +43395,11 @@ typedef struct wmi_pdev_vendor_cmd * would change, causing backwards incompatibilities. */ } wmi_pdev_vendor_cmd_fixed_param; +typedef wmi_pdev_vendor_cmd_fixed_param wmi_vendor_pdev_cmd_fixed_param; typedef struct wmi_vdev_vendor_cmd { - /* type is WMI_VDEV_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40347,10 +43415,11 @@ typedef struct wmi_vdev_vendor_cmd * would change, causing backwards incompatibilities. */ } wmi_vdev_vendor_cmd_fixed_param; +typedef wmi_vdev_vendor_cmd_fixed_param wmi_vendor_vdev_cmd_fixed_param; typedef struct wmi_peer_vendor_cmd { - /* type is WMI_PEER_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -40368,6 +43437,7 @@ typedef struct wmi_peer_vendor_cmd * would change, causing backwards incompatibilities. */ } wmi_peer_vendor_cmd_fixed_param; +typedef wmi_peer_vendor_cmd_fixed_param wmi_vendor_peer_cmd_fixed_param; typedef enum { WMI_MLO_LINK_FORCE_ACTIVE = 1, /* Force specific links active */ @@ -40382,6 +43452,7 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_NEW_CONNECT = 1, /* Set force specific links because of new connection */ WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, /* Set force specific links because of new dis-connection */ WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, /* Set force specific links because of AP-side link removal */ + WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ } WMI_MLO_LINK_FORCE_REASON; typedef struct wmi_mlo_link_set_active_cmd @@ -40541,6 +43612,10 @@ typedef struct { #define WMI_MAX_NUM_PREFERRED_LINKS 4 +/* NOTE: + * wmi_peer_preferred_link_map will be deprecated and replaced + * by wmi_mlo_peer_link_control_param. + */ typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ A_UINT32 tlv_header; @@ -40564,6 +43639,62 @@ typedef struct { A_UINT32 expected_max_latency_ms[WLAN_MAX_AC]; } wmi_peer_preferred_link_map; +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_TX_LINK_TUPLE_CONFIG(comp, value) \ + WMI_SET_BITS(comp, 0, 1, value) +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_TX_LINK_TUPLE_CONFIG(comp) \ + WMI_GET_BITS(comp, 0, 1) + +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_PREFERRED_LINK_CONFIG(comp, value) \ + WMI_SET_BITS(comp, 1, 1, value) +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_PREFERRED_LINK_CONFIG(comp) \ + WMI_GET_BITS(comp, 1, 1) + +#define WMI_MAX_NUM_MLO_LINKS 5 + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ + A_UINT32 tlv_header; + + /** flags: + * Bit0 : tx_link_tuple enable/disable. + * When enabled, f/w picks the links in tx_link_tuple_bitmap + * for TX scheduling. + * Bit1 : preferred_link enable/disable. + * When enabled, f/w schedules the data on preferred link first. + * If it fails to deliver within a timeout, it additionally + * starts attempting TX on non-preferred links. + * Bit2-31 : reserved + */ + A_UINT32 flags; + + /* num_links: number of links present in link_priority_order array below. + * 0 - we dont have sorted list of link priority + * non zero - this should be the max number of links that the peer supports. + */ + A_UINT32 num_links; + + /* link_priority_order: + * [0] - ID of highest priority link, + * [1] - ID of 2nd highest priority link, etc. + */ + A_UINT32 link_priority_order[WMI_MAX_NUM_MLO_LINKS]; + + /* tx_link_tuple_bitmap: + * bitmap of indices within link_priority_order array that needs to be + * selected in the TX link tuple. + * FW will not attempt scheduling on a link if it is not part of the + * tx_link_tuple. + */ + A_UINT32 tx_link_tuple_bitmap; + + /* max_timeout_ms: applicable only when preferred_link is enabled + * 0 - max_timeout_ms to be estimated in Firmware + * Non 0 - value beyond which, firmware should additionally start + * scheduling on non preferred links + */ + A_UINT32 max_timeout_ms[WLAN_MAX_AC]; +} wmi_mlo_peer_link_control_param; + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param */ A_UINT32 tlv_header; @@ -40579,6 +43710,8 @@ typedef struct { * - struct wmi_peer_preferred_link_map peer_preferred_link_map[]; * Note - TLV array of peer_preferred_link_map has either 0 or 1 * entries, not multiple entries. + * - struct wmi_mlo_peer_link_control_param[]; + * Note: can have 0 or 1 entry. */ } wmi_peer_tid_to_link_map_fixed_param; @@ -40606,6 +43739,22 @@ typedef enum { WMI_EXPECTED_DUR_EXPIRED, } WMI_MLO_TID_TO_LINK_MAP_STATUS; +#define WMI_BCAST_T2LM_MAX 16 /* max number of vdevs covered by T2LM stats */ +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct + */ + A_UINT32 tlv_header; + /* + * The below arrays store per-vdev counters, and are indexed by vdev ID. + * The number of valid elements is min(WMI_BCAST_T2LM_MAX, num vdevs). + */ + A_UINT32 bcast_t2lm_wmi_cmd[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_map_swt_tme_tsf[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_map_swt_tme_exp[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_exp_dur_exp[WMI_BCAST_T2LM_MAX]; +} wmi_ctrl_path_t2lm_stats_struct; + typedef struct{ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param */ A_UINT32 tlv_header; @@ -40630,6 +43779,9 @@ typedef struct{ #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_GET(_var) WMI_GET_BITS(_var, 4, 1) #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_SET(_var, _val) WMI_SET_BITS(_var, 4, 1, _val) +#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET(_var) WMI_GET_BITS(_var, 5, 1) +#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET(_var, _val) WMI_SET_BITS(_var, 5, 1, _val) + #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET(_var) WMI_GET_BITS(_var, 8, 8) #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET(_var, _val) WMI_SET_BITS(_var, 8, 8, _val) @@ -40710,7 +43862,12 @@ typedef struct { * // 0 - Expected Duration Field * // not Present * - * reserved:3 + * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET + * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET + * link_mapping_size:1 // 1 - Link Mapping Size 1 Octets + * // 0 - Link Mapping Size 2 Octets + * + * reserved:2 * * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET / * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET @@ -41719,9 +44876,409 @@ typedef enum { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param */ - A_UINT32 status; /* enum wmi_pdev_set_tgtr2p_event_status_type to indicate the status code/result */ + + /* status: + * enum wmi_pdev_set_tgtr2p_event_status_type to indicate the status + * code/result + */ + A_UINT32 status; + A_UINT32 pdev_id; /* to identify for which pdev the response is received */ } wmi_pdev_set_tgtr2p_table_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param */ + A_UINT32 vdev_id; + wmi_mac_addr mld_macaddr; /* MLD MAC address */ +} wmi_mlo_vdev_get_link_info_cmd_fixed_param; + +typedef enum { + WMI_LINK_INFO_EVENT_SUCCESS = 0, + + /* reject due to common failure reason */ + WMI_LINK_INFO_EVENT_REJECT_FAILURE, + + /* reject as vdev is not up */ + WMI_LINK_INFO_EVENT_REJECT_VDEV_NOT_UP, + + /* reject as roaming is in progress */ + WMI_LINK_INFO_EVENT_REJECT_ROAMING_IN_PROGRESS, + + /* reject as it's not MLO connection */ + WMI_LINK_INFO_EVENT_REJECT_NON_MLO_CONNECTION, +} wmi_mlo_vdev_link_info_event_status_type; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param */ + + /* status: + * enum wmi_mlo_vdev_link_info_event_status_type to indicate the status + */ + A_UINT32 status; + + /* vdev_id: + * unique id identifying the VDEV, generated by the caller + */ + A_UINT32 vdev_id; + + wmi_mac_addr mld_macaddr; /* MLD MAC address */ + + /* hw_mode_index: + * current hardware mode index, see soc_hw_mode_t for values + */ + A_UINT32 hw_mode_index; +} wmi_mlo_vdev_link_info_event_fixed_param; + +#define WMI_MLO_VDEV_LINK_INFO_GET_VDEVID(link_info) WMI_GET_BITS(link_info, 0, 8) +#define WMI_MLO_VDEV_LINK_INFO_SET_VDEVID(link_info, value) WMI_SET_BITS(link_info, 0, 8, value) +#define WMI_MLO_VDEV_LINK_INFO_GET_LINKID(link_info) WMI_GET_BITS(link_info, 8, 8) +#define WMI_MLO_VDEV_LINK_INFO_SET_LINKID(link_info, value) WMI_SET_BITS(link_info, 8, 8, value) +#define WMI_MLO_VDEV_LINK_INFO_GET_LINK_STATUS(link_info) WMI_GET_BITS(link_info, 16, 2) +#define WMI_MLO_VDEV_LINK_INFO_SET_LINK_STATUS(link_info, value) WMI_SET_BITS(link_info, 16, 2, value) + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info */ + union { + struct { + A_UINT32 vdev_id:8, /* vdev id for this link */ + link_id:8, /* link id defined as in 802.11 BE spec. */ + link_status:2, /* link_status - 0: active, 1: inactive */ + reserved:14; + }; + A_UINT32 link_info; + }; + A_UINT32 chan_freq; /* Channel frequency in MHz */ +} wmi_mlo_vdev_link_info; + +/* Manual UL OFDMA trigger frame data structures */ + +typedef enum { + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_NONE, + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_RESP, /* response timeout, mismatch, + * BW mismatch, mimo ctrl mismatch, + * CRC error.. */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FILT, /* blocked by tx filtering */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FIFO, /* fifo, misc errors in HW */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_SWABORT, /* software initiated abort + * (TX_ABORT) */ + + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX = 0xff, + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_INVALID = + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX +} wmi_ul_ofdma_manual_trig_txerr_t; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* To indicate whether feedback event is for SU (0) or MU trigger (1) */ + A_UINT32 feedback_trig_type; + + /* Feedback Params */ + A_UINT32 curr_su_manual_trig_count; + A_UINT32 remaining_su_manual_trig; + A_UINT32 remaining_mu_trig_peers; + A_UINT32 manual_trig_status; /* holds a wmi_ul_ofdma_manual_trig_txerr_t */ + + /** + * This TLV is followed by TLVs below: + * wmi_mac_addr peer_macaddr[]; + * Array length corresponds to the number of triggered peers + */ +} wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* Configurable Parameters for manual UL OFDMA Multi-User Trigger frame */ + A_UINT32 manual_trig_preferred_ac; + /** + * This TLV is followed by TLVs below: + * wmi_mac_addr peer_macaddr[]; + * The array has one element for each peer to be included in the + * manually-triggered UL MU transmission. + */ +} wmi_vdev_set_manual_mu_trig_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* Configurable Parameters for manual UL OFDMA Single-User Trigger frame */ + wmi_mac_addr peer_macaddr; + A_UINT32 manual_trig_preferred_ac; + A_UINT32 num_su_manual_trig; + A_UINT32 manual_trig_length; + A_UINT32 manual_trig_mcs; + A_UINT32 manual_trig_nss; + A_INT32 manual_trig_target_rssi; /* units = dBm */ +} wmi_vdev_set_manual_su_trig_cmd_fixed_param; + + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \ + WMI_SET_BITS(asnr_params, 0, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \ + WMI_GET_BITS(asnr_params, 0, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_OFFSET(asnr_params, value) \ + WMI_SET_BITS(asnr_params, 16, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_OFFSET(asnr_params) \ + WMI_GET_BITS(asnr_params, 16, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_LENGTH(dsnr_params, value) \ + WMI_SET_BITS(dsnr_params, 0, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_LENGTH(dsnr_params) \ + WMI_GET_BITS(dsnr_params, 0, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_OFFSET(dsnr_params, value) \ + WMI_SET_BITS(dsnr_params, 16, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_OFFSET(dsnr_params) \ + WMI_GET_BITS(dsnr_params, 16, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NC(fb_params, value) \ + WMI_SET_BITS(fb_params, 0, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NC(fb_params) \ + WMI_GET_BITS(fb_params, 0, 2) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NSS_NUM(fb_params, value) \ + WMI_SET_BITS(fb_params, 2, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \ + WMI_GET_BITS(fb_params, 2, 2) + + +#define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \ + WMI_SET_BITS(snd_params, 0, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \ + WMI_GET_BITS(snd_params, 0, 1) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \ + WMI_SET_BITS(snd_params, 1, 2, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \ + WMI_GET_BITS(snd_params, 1, 2) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \ + WMI_SET_BITS(snd_params, 3, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \ + WMI_GET_BITS(snd_params, 3, 1) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \ + WMI_SET_BITS(snd_params, 4, 3, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \ + WMI_GET_BITS(snd_params, 4, 3) + + +typedef enum _WMI_STANDALONE_SOUND_STATUS_T { + WMI_STANDALONE_SOUND_STATUS_OK, + WMI_STANDALONE_SOUND_STATUS_ERR_NUM_PEERS_EXCEEDED, + WMI_STANDALONE_SOUND_STATUS_ERR_NG_INVALID, + WMI_STANDALONE_SOUND_STATUS_ERR_NUM_REPEAT_EXCEEDED, + WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOESNOT_SUPPORT_BW, + WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_PEER, + WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_VDEV, + WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOES_NOT_SUPPORT_MU_FB, + WMI_STANDALONE_SOUND_STATUS_ERR_DMA_NOT_CONFIGURED, + WMI_STANDALONE_SOUND_STATUS_ERR_COMPLETE_FAILURE, +} WMI_STANDALONE_SOUND_STATUS_T; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data */ + /** Set if the CV is valid */ + A_UINT32 is_valid; + /** Feedback type */ + A_UINT32 fb_type; + /** + * [15:0] ASNR length + * [31:16] ASNR offset + */ + A_UINT32 asnr_params; + /** + * [15:0] DSNR length + * [31:16] DSNR offset + */ + A_UINT32 dsnr_params; + /** Peer mac address */ + wmi_mac_addr peer_mac_address; + /** + * [1:0] Nc + * [3:2] nss_num + */ + A_UINT32 fb_params; +} wmi_dma_buf_release_cv_upload_meta_data; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */ + /** vdev identifier */ + A_UINT32 vdev_id; + /** sounding_params: + * [0] Feedback type + * [2:1] Ng + * [3] Codebook + * [6:4] BW + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + * [31:7] Reserved + */ + A_UINT32 sounding_params; + /** The number of sounding repeats */ + A_UINT32 num_sounding_repeats; + /** + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * wmi_mac_addr peer_list[num_peers]; + */ +} wmi_standalone_sounding_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param */ + /** vdev identifier */ + A_UINT32 vdev_id; + /** status: + * standalone sounding command status - + * refer to WMI_STANDALONE_SOUND_STATUS_T + */ + A_UINT32 status; + /** number of CV buffers uploaded */ + A_UINT32 buffer_uploaded; + /** TLV (tag length value) parameters follow the + * structure. The TLV's are: + * A_UINT32 snd_failed[num_sounding_repeats]; + * snd_failed[] array's elements hold the number of failures + * for each sounding. + */ +} wmi_standalone_sounding_evt_fixed_param; + +typedef struct { + /* + * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* pdev_id for identifying the MAC */ + A_UINT32 pdev_id; + /* + * rf_path : + * 0 - primary RF path + * 1 - secondary RF path + */ + A_UINT32 rf_path; +} wmi_pdev_set_rf_path_cmd_fixed_param; + +#define WMI_SET_RX_PEER_STATS_RESP_TYPE(rx_params, value) \ + WMI_SET_BITS(rx_params, 0, 1, value) +#define WMI_GET_RX_PEER_STATS_RESP_TYPE(rx_params) \ + WMI_GET_BITS(rx_params, 0, 1) + +#define WMI_SET_RX_PEER_STATS_MCS(rx_params, value) \ + WMI_SET_BITS(rx_params, 1, 5, value) +#define WMI_GET_RX_PEER_STATS_MCS(rx_params) \ + WMI_GET_BITS(rx_params, 1, 5) + +#define WMI_SET_RX_PEER_STATS_NSS(rx_params, value) \ + WMI_SET_BITS(rx_params, 6, 4, value) +#define WMI_GET_RX_PEER_STATS_NSS(rx_params) \ + WMI_GET_BITS(rx_params, 6, 4) + +#define WMI_SET_RX_PEER_STATS_GI_LTF_TYPE(rx_params, value) \ + WMI_SET_BITS(rx_params, 10, 4, value) +#define WMI_GET_RX_PEER_STATS_GI_LTF_TYPE(rx_params) \ + WMI_GET_BITS(rx_params, 10, 4) + +typedef enum { + WMI_PEER_RX_RESP_SU = 0, + WMI_PEER_RX_RESP_MIMO = 1, + WMI_PEER_RX_RESP_OFDMA = 2, +} WMI_PEER_RX_RESP_TYPE; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo */ + A_UINT32 tlv_header; + + /* Peer mac address */ + wmi_mac_addr peer_macaddr; + + /* Per peer RX parameters */ + /* [0] - Flag to indicate if peer responded with QoS Data or QoS NULL. + * 0 -> indicates QoS NULL, 1-> indicates QoS Data response + * [5:1] - MCS - Peer response MCS + * [9:6] - NSS - Peer response NSS + * [13:10] - GI LTF Type - Peer response GI/LTF type + * 0 => gi == GI_1600 && ltf == 1x LTF + * 1 => gi == GI_1600 && ltf == 2x LTF + * 2 => gi == GI_3200 && ltf == 4x LTF + * [31:14] - Reserved + */ + A_UINT32 rx_peer_stats; + + /* Peer response per chain RSSI */ + A_INT32 peer_per_chain_rssi[WMI_MAX_CHAINS]; +} wmi_manual_ul_ofdma_trig_rx_peer_userinfo; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param */ + A_UINT32 tlv_header; + + A_UINT32 vdev_id; /* VDEV identifier */ + + /* combined_rssi: + * RX Combined RSSI in dBm + * Value indicates the average RSSI per 20MHz by averaging the total RSSI + * across entire BW for each OFDMA STA + */ + A_INT32 combined_rssi; + + /* rx_ppdu_resp_type: + * RX PPDU Response Type + * Refer WMI_PEER_RX_RESP_TYPE for possible values + */ + A_UINT32 rx_ppdu_resp_type; + + /* rx_resp_bw: + * RX response bandwidth + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + */ + A_UINT32 rx_resp_bw; + + /** + * This TLV is followed by TLVs below: + * wmi_manual_ul_ofdma_trig_rx_peer_userinfo rx_peer_userinfo[] + * TLV length specified by number of peer responses for manual + * UL OFDMA trigger + */ +} wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param; + +typedef enum _WMI_VDEV_PAUSE_TYPE +{ + WMI_VDEV_PAUSE_TYPE_UNKNOWN = 0, + WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1, + WMI_VDEV_PAUSE_TYPE_TX = 2, +} WMI_VDEV_PAUSE_TYPE; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** type of pause, refer to WMI_VDEV_PAUSE_TYPE */ + A_UINT32 pause_type; + /** duration of pause, in unit of ms */ + A_UINT32 pause_dur_ms; +} wmi_vdev_pause_cmd_fixed_param; diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h index 1158e62f7d81..f5d8720c0b51 100644 --- a/drivers/staging/fw-api/fw/wmi_version.h +++ b/drivers/staging/fw-api/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1270 +#define __WMI_REVISION_ 1319 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work diff --git a/drivers/staging/fw-api/hw/kiwi/v2/ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/ack_report.h new file mode 100644 index 000000000000..b92cb77fd2a6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/ack_report.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_ACK_REPORT 1 + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, + ax_trigger_type : 4, + sr_ppdu : 1, + reserved : 7, + frame_control : 16; +#else + uint32_t frame_control : 16, + reserved : 7, + sr_ppdu : 1, + ax_trigger_type : 4, + selfgen_response_reason : 4; +#endif +}; + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/coex_rx_status.h b/drivers/staging/fw-api/hw/kiwi/v2/coex_rx_status.h new file mode 100644 index 000000000000..53bbf0053f48 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/coex_rx_status.h @@ -0,0 +1,147 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +#define NUM_OF_QWORDS_COEX_RX_STATUS 1 + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, + rx_with_tx_response : 1, + rx_rate : 5, + rx_bw : 3, + single_mpdu : 1, + filter_status : 1, + ampdu : 1, + directed : 1, + reserved_0 : 1, + rx_nss : 3, + rx_rssi : 8, + rx_type : 3, + retry_bit_setting : 1, + more_data_bit_setting : 1; + uint32_t remain_rx_packet_time : 16, + rx_remaining_fes_time : 16; +#else + uint32_t more_data_bit_setting : 1, + retry_bit_setting : 1, + rx_type : 3, + rx_rssi : 8, + rx_nss : 3, + reserved_0 : 1, + directed : 1, + ampdu : 1, + filter_status : 1, + single_mpdu : 1, + rx_bw : 3, + rx_rate : 5, + rx_with_tx_response : 1, + rx_mac_frame_status : 2; + uint32_t rx_remaining_fes_time : 16, + remain_rx_packet_time : 16; +#endif +}; + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_req.h b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_req.h new file mode 100644 index 000000000000..e19fefa41385 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_req.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +#define NUM_OF_QWORDS_COEX_TX_REQ 2 + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, + min_tx_pwr : 8, + nss : 3, + tx_chain_mask : 8, + bw : 3, + reserved_0 : 2; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + reserved_1 : 2; + uint32_t tx_pwr_1 : 8, + alt_tx_pwr_1 : 8, + wlan_request_duration : 16; + uint32_t wlan_pkt_type : 4, + coex_tx_reason : 2, + response_frame_type : 5, + wlan_low_priority_slicing_allowed : 1, + wlan_high_priority_slicing_allowed : 1, + sch_tx_burst_ongoing : 1, + coex_tx_priority : 4, + reserved_3a : 14; +#else + uint32_t reserved_0 : 2, + bw : 3, + tx_chain_mask : 8, + nss : 3, + min_tx_pwr : 8, + tx_pwr : 8; + uint32_t reserved_1 : 2, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t wlan_request_duration : 16, + alt_tx_pwr_1 : 8, + tx_pwr_1 : 8; + uint32_t reserved_3a : 14, + coex_tx_priority : 4, + sch_tx_burst_ongoing : 1, + wlan_high_priority_slicing_allowed : 1, + wlan_low_priority_slicing_allowed : 1, + response_frame_type : 5, + coex_tx_reason : 2, + wlan_pkt_type : 4; +#endif +}; + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x0000000038000000 + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_NSS_LSB 48 +#define COEX_TX_REQ_ALT_NSS_MSB 50 +#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_BW_LSB 59 +#define COEX_TX_REQ_ALT_BW_MSB 61 +#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_1_LSB 62 +#define COEX_TX_REQ_RESERVED_1_MSB 63 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESERVED_3A_LSB 50 +#define COEX_TX_REQ_RESERVED_3A_MSB 63 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_status.h b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_status.h new file mode 100644 index 000000000000..597c37388879 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/coex_tx_status.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_STATUS 4 + +#define NUM_OF_QWORDS_COEX_TX_STATUS 2 + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, + tx_bw : 3, + tx_status_reason : 3, + tx_wait_ack : 1, + fes_tx_is_gen_frame : 1, + sch_tx_burst_ongoing : 1, + current_tx_duration : 16; + uint32_t next_rx_active_time : 16, + remaining_fes_time : 16; + uint32_t tx_antenna_mask : 8, + shared_ant_tx_pwr : 8, + other_ant_tx_pwr : 8, + reserved_2 : 8; + uint32_t tlv64_padding : 32; +#else + uint32_t current_tx_duration : 16, + sch_tx_burst_ongoing : 1, + fes_tx_is_gen_frame : 1, + tx_wait_ack : 1, + tx_status_reason : 3, + tx_bw : 3, + reserved_0a : 7; + uint32_t remaining_fes_time : 16, + next_rx_active_time : 16; + uint32_t reserved_2 : 8, + other_ant_tx_pwr : 8, + shared_ant_tx_pwr : 8, + tx_antenna_mask : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 + +#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 +#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 +#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 000000000000..9ae112a88007 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,110 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + sta_coding : 1, + sta_spatial_config : 6, + reserved_0a : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0a : 1, + sta_spatial_config : 6, + sta_coding : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_ofdma_info.h new file mode 100644 index 000000000000..4700af7c4610 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_ofdma_info.h @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0b : 1, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_su_info.h new file mode 100644 index 000000000000..746d557796f9 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/eht_sig_usr_su_info.h @@ -0,0 +1,89 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 9, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0b : 9, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; +#endif +}; + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/expected_response.h b/drivers/staging/fw-api/hw/kiwi/v2/expected_response.h new file mode 100644 index 000000000000..e62901b24604 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/expected_response.h @@ -0,0 +1,217 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 + +#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; + uint32_t tx_ad2_47_32 : 16, + expected_response_type : 5, + response_to_response : 3, + su_ba_user_number : 1, + response_info_part2_required : 1, + transmitted_bssid_check_en : 1, + reserved_1 : 5; + uint32_t ndp_sta_partial_aid_2_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid1_8_0 : 11; + uint32_t ast_index : 16, + capture_ack_ba_sounding : 1, + capture_sounding_1str_20mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_320mhz : 1, + reserved_3a : 9; + uint32_t fcs : 9, + reserved_4a : 1, + crc : 4, + scrambler_seed : 7, + reserved_4b : 11; + uint32_t tlv64_padding : 32; +#else + uint32_t tx_ad2_31_0 : 32; + uint32_t reserved_1 : 5, + transmitted_bssid_check_en : 1, + response_info_part2_required : 1, + su_ba_user_number : 1, + response_to_response : 3, + expected_response_type : 5, + tx_ad2_47_32 : 16; + uint32_t ndp_sta_partial_aid1_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid_2_8_0 : 11; + uint32_t reserved_3a : 9, + capture_sounding_1str_320mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_20mhz : 1, + capture_ack_ba_sounding : 1, + ast_index : 16; + uint32_t reserved_4b : 11, + scrambler_seed : 7, + crc : 4, + reserved_4a : 1, + fcs : 9; + uint32_t tlv64_padding : 32; +#endif +}; + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 59 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 + +#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 +#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 +#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 000000000000..3d3ff5b23ae9 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 000000000000..0996ff5b5460 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_su.h new file mode 100644 index 000000000000..6254d13942d8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_eht_sig_usr_su.h @@ -0,0 +1,85 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..fcbbd39d631e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,148 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..c150750711b0 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,98 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_su.h new file mode 100644 index 000000000000..0ae2a026c796 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_a_su.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b1_mu.h new file mode 100644 index 000000000000..de9156081d13 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b1_mu.h @@ -0,0 +1,60 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_mu.h new file mode 100644 index 000000000000..0204d9a3739d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_mu.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..09cde561aebd --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_ht_sig.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_ht_sig.h new file mode 100644 index 000000000000..2bbb61d6f40e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_ht_sig.h @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +#define NUM_OF_QWORDS_MACTX_HT_SIG 1 + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_a.h new file mode 100644 index 000000000000..1d7913d53c06 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_a.h @@ -0,0 +1,90 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_b.h new file mode 100644 index 000000000000..397c20f7067b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_l_sig_b.h @@ -0,0 +1,65 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_phy_desc.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_phy_desc.h new file mode 100644 index 000000000000..c6f7cdca83fc --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_phy_desc.h @@ -0,0 +1,371 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, + bf_type : 2, + wait_sifs : 2, + dot11b_preamble_type : 1, + pkt_type : 4, + su_or_mu : 2, + mu_type : 1, + bandwidth : 3, + channel_capture : 1; + uint32_t mcs : 4, + global_ofdma_mimo_enable : 1, + reserved_1a : 1, + stbc : 1, + dot11ax_su_extended : 1, + dot11ax_trigger_frame_embedded : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8, + measure_power : 1, + tpc_glut_self_cal : 1, + back_to_back_transmission_expected : 1, + heavy_clip_nss : 3, + txbf_per_packet_no_csd_no_walsh : 1; + uint32_t ndp : 2, + ul_flag : 1, + triggered : 1, + ap_pkt_bw : 3, + ru_position_start : 8, + pcu_ppdu_setup_start_reason : 3, + tlv_source : 1, + reserved_2a : 2, + nss : 3, + stream_offset : 3, + reserved_2b : 2, + clpc_enable : 1, + mu_ndp : 1, + response_expected : 1; + uint32_t rx_chain_mask : 8, + rx_chain_mask_valid : 1, + ant_sel_valid : 1, + ant_sel : 1, + cp_setting : 2, + he_ppdu_subtype : 2, + active_channel : 3, + generate_phyrx_tx_start_timing : 1, + ltf_size : 2, + ru_size_updated_v2 : 4, + reserved_3c : 1, + u_sig_puncture_pattern_encoding : 6; +#else + uint32_t channel_capture : 1, + bandwidth : 3, + mu_type : 1, + su_or_mu : 2, + pkt_type : 4, + dot11b_preamble_type : 1, + wait_sifs : 2, + bf_type : 2, + reserved_0a : 16; + uint32_t txbf_per_packet_no_csd_no_walsh : 1, + heavy_clip_nss : 3, + back_to_back_transmission_expected : 1, + tpc_glut_self_cal : 1, + measure_power : 1, + tx_pwr_unshared : 8, + tx_pwr_shared : 8, + dot11ax_trigger_frame_embedded : 1, + dot11ax_su_extended : 1, + stbc : 1, + reserved_1a : 1, + global_ofdma_mimo_enable : 1, + mcs : 4; + uint32_t response_expected : 1, + mu_ndp : 1, + clpc_enable : 1, + reserved_2b : 2, + stream_offset : 3, + nss : 3, + reserved_2a : 2, + tlv_source : 1, + pcu_ppdu_setup_start_reason : 3, + ru_position_start : 8, + ap_pkt_bw : 3, + triggered : 1, + ul_flag : 1, + ndp : 2; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_3c : 1, + ru_size_updated_v2 : 4, + ltf_size : 2, + generate_phyrx_tx_start_timing : 1, + active_channel : 3, + he_ppdu_subtype : 2, + cp_setting : 2, + ant_sel : 1, + ant_sel_valid : 1, + rx_chain_mask_valid : 1, + rx_chain_mask : 8; +#endif +}; + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 + +#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MCS_LSB 32 +#define MACTX_PHY_DESC_MCS_MSB 35 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 + +#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_STBC_LSB 38 +#define MACTX_PHY_DESC_STBC_MSB 38 +#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 + +#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 + +#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_LSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CP_SETTING_LSB 43 +#define MACTX_PHY_DESC_CP_SETTING_MSB 44 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h new file mode 100644 index 000000000000..35f58ab104f6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_tb.h new file mode 100644 index 000000000000..7318873f1a6a --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_u_sig_eht_tb.h @@ -0,0 +1,113 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_common.h new file mode 100644 index 000000000000..f3d78ce1ee1b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_common.h @@ -0,0 +1,484 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + reserved_0b : 5, + ltf_size : 2, + reserved_0c : 3, + he_stf_long : 1, + reserved_0d : 7, + num_users_he_sigb_band0 : 8; + uint32_t num_ltf_symbols : 3, + reserved_1a : 5, + num_users_he_sigb_band1 : 8, + reserved_1b : 16; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + reserved : 2, + he_sigb_dcm : 1, + reserved_2b : 7, + he_sigb_compression : 1, + reserved_2c : 15; + uint32_t he_sigb_0_mcs : 3, + reserved_3a : 13, + num_he_sigb_sym : 5, + center_ru_0 : 1, + center_ru_1 : 1, + reserved_3b : 1, + ftm_en : 1, + pe_nss : 3, + pe_ltf_size : 2, + pe_content : 1, + pe_chain_csd_en : 1; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, + ndp_ru_tone_set_index : 7, + ndp_feedback_status : 1, + doppler_indication : 1, + reserved_14a : 7; + uint32_t spatial_reuse : 16, + reserved_15a : 16; +#else + uint32_t num_users_he_sigb_band0 : 8, + reserved_0d : 7, + he_stf_long : 1, + reserved_0c : 3, + ltf_size : 2, + reserved_0b : 5, + num_users : 6; + uint32_t reserved_1b : 16, + num_users_he_sigb_band1 : 8, + reserved_1a : 5, + num_ltf_symbols : 3; + uint32_t reserved_2c : 15, + he_sigb_compression : 1, + reserved_2b : 7, + he_sigb_dcm : 1, + reserved : 2, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t pe_chain_csd_en : 1, + pe_content : 1, + pe_ltf_size : 2, + pe_nss : 3, + ftm_en : 1, + reserved_3b : 1, + center_ru_1 : 1, + center_ru_0 : 1, + num_he_sigb_sym : 5, + reserved_3a : 13, + he_sigb_0_mcs : 3; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, + doppler_indication : 1, + ndp_feedback_status : 1, + ndp_ru_tone_set_index : 7, + num_data_symbols : 16; + uint32_t reserved_15a : 16, + spatial_reuse : 16; +#endif +}; + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_per_user.h new file mode 100644 index 000000000000..c0cf26c9ecb1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_user_desc_per_user.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, + reserved_0a : 8; + uint32_t ru_start_index : 8, + ru_size : 4, + reserved_1b : 4, + ofdma_mu_mimo_enabled : 1, + nss : 3, + stream_offset : 3, + reserved_1c : 1, + mcs : 4, + dcm : 1, + reserved_1d : 3; + uint32_t fec_type : 1, + reserved_2a : 7, + user_bf_type : 2, + reserved_2b : 6, + drop_user_cbf : 1, + reserved_2c : 7, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_2d : 6; + uint32_t sw_peer_id : 16, + per_user_subband_mask : 16; +#else + uint32_t reserved_0a : 8, + psdu_length : 24; + uint32_t reserved_1d : 3, + dcm : 1, + mcs : 4, + reserved_1c : 1, + stream_offset : 3, + nss : 3, + ofdma_mu_mimo_enabled : 1, + reserved_1b : 4, + ru_size : 4, + ru_start_index : 8; + uint32_t reserved_2d : 6, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + reserved_2c : 7, + drop_user_cbf : 1, + reserved_2b : 6, + user_bf_type : 2, + reserved_2a : 7, + fec_type : 1; + uint32_t per_user_subband_mask : 16, + sw_peer_id : 16; +#endif +}; + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 59 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_a.h new file mode 100644 index 000000000000..34eddc4b435c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_a.h @@ -0,0 +1,128 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu160.h new file mode 100644 index 000000000000..52e85cdec205 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu160.h @@ -0,0 +1,198 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu20.h new file mode 100644 index 000000000000..626929b4c767 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu20.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu40.h new file mode 100644 index 000000000000..bc1e56c46c53 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu40.h @@ -0,0 +1,83 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu80.h new file mode 100644 index 000000000000..d4499072674d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_mu80.h @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su160.h new file mode 100644 index 000000000000..aa74f8a27a12 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su160.h @@ -0,0 +1,238 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su20.h new file mode 100644 index 000000000000..823052ebfd88 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su20.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su40.h new file mode 100644 index 000000000000..610db4be1fcf --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su40.h @@ -0,0 +1,88 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su80.h new file mode 100644 index 000000000000..ae448945e01b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mactx_vht_sig_b_su80.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/kiwi/v2/mlo_sta_id_details.h new file mode 100644 index 000000000000..91bf584790fc --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mlo_sta_id_details.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, + block_self_ml_sync : 1, + block_partner_ml_sync : 1, + nstr_mlo_sta_id_valid : 1, + reserved_0a : 3; +#else + uint16_t reserved_0a : 3, + nstr_mlo_sta_id_valid : 1, + block_partner_ml_sync : 1, + block_self_ml_sync : 1, + nstr_mlo_sta_id : 10; +#endif +}; + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_buffer_addr.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_buffer_addr.h new file mode 100644 index 000000000000..afbfb52367c2 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_buffer_addr.h @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 + +#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t dma_length : 12, + reserved_2a : 4, + msdu_continuation : 1, + truncated : 1, + reserved_2b : 14; + uint32_t tlv64_padding : 32; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reserved_2b : 14, + truncated : 1, + msdu_continuation : 1, + reserved_2a : 4, + dma_length : 12; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 + +#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 +#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 +#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_destination_ring.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_destination_ring.h new file mode 100644 index 000000000000..c92ec87f4d99 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_destination_ring.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t end_offset : 12, + reserved_3a : 4, + end_reason : 2, + initiator : 1, + empty_descriptor : 1, + ring_id : 8, + looping_count : 4; +#else + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t looping_count : 4, + ring_id : 8, + empty_descriptor : 1, + initiator : 1, + end_reason : 2, + reserved_3a : 4, + end_offset : 12; +#endif +}; + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 15 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000 + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_drop.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_drop.h new file mode 100644 index 000000000000..f4af1328c76e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_drop.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DROP 2 + +#define NUM_OF_QWORDS_MON_DROP 1 + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; + uint32_t ppdu_drop_cnt : 10, + mpdu_drop_cnt : 10, + tlv_drop_cnt : 10, + end_of_ppdu_seen : 1, + reserved_1a : 1; +#else + uint32_t ppdu_id : 32; + uint32_t reserved_1a : 1, + end_of_ppdu_seen : 1, + tlv_drop_cnt : 10, + mpdu_drop_cnt : 10, + ppdu_drop_cnt : 10; +#endif +}; + +#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_DROP_CNT_LSB 32 +#define MON_DROP_PPDU_DROP_CNT_MSB 41 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_MPDU_DROP_CNT_LSB 42 +#define MON_DROP_MPDU_DROP_CNT_MSB 51 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_TLV_DROP_CNT_LSB 52 +#define MON_DROP_TLV_DROP_CNT_MSB 61 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 + +#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 +#define MON_DROP_RESERVED_1A_LSB 63 +#define MON_DROP_RESERVED_1A_MSB 63 +#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/mon_ingress_ring.h b/drivers/staging/fw-api/hw/kiwi/v2/mon_ingress_ring.h new file mode 100644 index 000000000000..5ddfc4f725f5 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/mon_ingress_ring.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#endif +}; + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/no_ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/no_ack_report.h new file mode 100644 index 000000000000..9e545358e5d3 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/no_ack_report.h @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, + macrx_abort_reason : 4, + phyrx_abort_reason : 8, + frame_control : 16; + uint32_t rx_ppdu_duration : 24, + sr_ppdu_during_obss : 1, + selfgen_response_reason_to_sr_ppdu : 4, + reserved_1 : 3; + uint32_t pre_bt_broadcast_status_details : 12, + first_bt_broadcast_status_details : 12, + reserved_2 : 8; + uint32_t second_bt_broadcast_status_details : 12, + reserved_3 : 20; +#else + uint32_t frame_control : 16, + phyrx_abort_reason : 8, + macrx_abort_reason : 4, + no_ack_transmit_reason : 4; + uint32_t reserved_1 : 3, + selfgen_response_reason_to_sr_ppdu : 4, + sr_ppdu_during_obss : 1, + rx_ppdu_duration : 24; + uint32_t reserved_2 : 8, + first_bt_broadcast_status_details : 12, + pre_bt_broadcast_status_details : 12; + uint32_t reserved_3 : 20, + second_bt_broadcast_status_details : 12; +#endif +}; + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/kiwi/v2/ofdma_trigger_details.h new file mode 100644 index 000000000000..86a807ab89f6 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/ofdma_trigger_details.h @@ -0,0 +1,840 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, + rx_trigger_frame_user_source : 2, + received_bandwidth : 3, + txop_duration_all_ones : 1, + eht_trigger_response : 1, + pre_rssi_comb : 8, + rssi_comb : 8, + rxpcu_pcie_l0_req_duration : 8; + uint32_t he_trigger_ul_ppdu_length : 5, + he_trigger_ru_allocation : 8, + he_trigger_dl_tx_power : 5, + he_trigger_ul_target_rssi : 5, + he_trigger_ul_mcs : 2, + he_trigger_reserved : 1, + bss_color : 6; + uint32_t trigger_type : 4, + lsig_response_length : 12, + cascade_indication : 1, + carrier_sense : 1, + bandwidth : 2, + cp_ltf_size : 2, + mu_mimo_ltf_mode : 1, + number_of_ltfs : 3, + stbc : 1, + ldpc_extra_symbol : 1, + ap_tx_power_lsb_part : 4; + uint32_t ap_tx_power_msb_part : 2, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + spatial_reuse : 16, + doppler : 1, + he_siga_reserved : 9, + reserved_3b : 1; + uint32_t aid12 : 12, + ru_allocation : 9, + mcs : 4, + dcm : 1, + start_spatial_stream : 3, + number_of_spatial_stream : 3; + uint32_t target_rssi : 7, + coding_type : 1, + mpdu_mu_spacing_factor : 2, + tid_aggregation_limit : 3, + reserved_5b : 1, + prefered_ac : 2, + bar_control_ack_policy : 1, + bar_control_multi_tid : 1, + bar_control_compressed_bitmap : 1, + bar_control_reserved : 9, + bar_control_tid_info : 4; + uint32_t nr0_per_tid_info_reserved : 12, + nr0_per_tid_info_tid_value : 4, + nr0_start_seq_ctrl_frag_number : 4, + nr0_start_seq_ctrl_start_seq_number : 12; + uint32_t nr1_per_tid_info_reserved : 12, + nr1_per_tid_info_tid_value : 4, + nr1_start_seq_ctrl_frag_number : 4, + nr1_start_seq_ctrl_start_seq_number : 12; + uint32_t nr2_per_tid_info_reserved : 12, + nr2_per_tid_info_tid_value : 4, + nr2_start_seq_ctrl_frag_number : 4, + nr2_start_seq_ctrl_start_seq_number : 12; + uint32_t nr3_per_tid_info_reserved : 12, + nr3_per_tid_info_tid_value : 4, + nr3_start_seq_ctrl_frag_number : 4, + nr3_start_seq_ctrl_start_seq_number : 12; + uint32_t nr4_per_tid_info_reserved : 12, + nr4_per_tid_info_tid_value : 4, + nr4_start_seq_ctrl_frag_number : 4, + nr4_start_seq_ctrl_start_seq_number : 12; + uint32_t nr5_per_tid_info_reserved : 12, + nr5_per_tid_info_tid_value : 4, + nr5_start_seq_ctrl_frag_number : 4, + nr5_start_seq_ctrl_start_seq_number : 12; + uint32_t nr6_per_tid_info_reserved : 12, + nr6_per_tid_info_tid_value : 4, + nr6_start_seq_ctrl_frag_number : 4, + nr6_start_seq_ctrl_start_seq_number : 12; + uint32_t nr7_per_tid_info_reserved : 12, + nr7_per_tid_info_tid_value : 4, + nr7_start_seq_ctrl_frag_number : 4, + nr7_start_seq_ctrl_start_seq_number : 12; + uint32_t fb_segment_retransmission_bitmap : 8, + reserved_14a : 2, + u_sig_puncture_pattern_encoding : 6, + dot11be_puncture_bitmap : 16; + uint32_t rx_chain_mask : 8, + rx_duration_field : 16, + scrambler_seed : 7, + rx_chain_mask_type : 1; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t sw_peer_id : 16, + response_tx_duration : 16; + uint32_t __reserved_g_0005_trigger_subtype : 4, + tbr_trigger_common_info_79_68 : 12, + tbr_trigger_sound_reserved_20_12 : 9, + i2r_rep : 3, + tbr_trigger_sound_reserved_25_24 : 2, + reserved_18a : 1, + qos_null_only_response_tx : 1; + uint32_t tbr_trigger_sound_sac : 16, + reserved_19a : 8, + u_sig_reserved2 : 5, + reserved_19b : 3; + uint32_t eht_special_aid12 : 12, + phy_version : 3, + bandwidth_ext : 2, + eht_spatial_reuse : 8, + u_sig_reserved1 : 7; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, + rssi_comb : 8, + pre_rssi_comb : 8, + eht_trigger_response : 1, + txop_duration_all_ones : 1, + received_bandwidth : 3, + rx_trigger_frame_user_source : 2, + ax_trigger_source : 1; + uint32_t bss_color : 6, + he_trigger_reserved : 1, + he_trigger_ul_mcs : 2, + he_trigger_ul_target_rssi : 5, + he_trigger_dl_tx_power : 5, + he_trigger_ru_allocation : 8, + he_trigger_ul_ppdu_length : 5; + uint32_t ap_tx_power_lsb_part : 4, + ldpc_extra_symbol : 1, + stbc : 1, + number_of_ltfs : 3, + mu_mimo_ltf_mode : 1, + cp_ltf_size : 2, + bandwidth : 2, + carrier_sense : 1, + cascade_indication : 1, + lsig_response_length : 12, + trigger_type : 4; + uint32_t reserved_3b : 1, + he_siga_reserved : 9, + doppler : 1, + spatial_reuse : 16, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + ap_tx_power_msb_part : 2; + uint32_t number_of_spatial_stream : 3, + start_spatial_stream : 3, + dcm : 1, + mcs : 4, + ru_allocation : 9, + aid12 : 12; + uint32_t bar_control_tid_info : 4, + bar_control_reserved : 9, + bar_control_compressed_bitmap : 1, + bar_control_multi_tid : 1, + bar_control_ack_policy : 1, + prefered_ac : 2, + reserved_5b : 1, + tid_aggregation_limit : 3, + mpdu_mu_spacing_factor : 2, + coding_type : 1, + target_rssi : 7; + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, + nr0_start_seq_ctrl_frag_number : 4, + nr0_per_tid_info_tid_value : 4, + nr0_per_tid_info_reserved : 12; + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, + nr1_start_seq_ctrl_frag_number : 4, + nr1_per_tid_info_tid_value : 4, + nr1_per_tid_info_reserved : 12; + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, + nr2_start_seq_ctrl_frag_number : 4, + nr2_per_tid_info_tid_value : 4, + nr2_per_tid_info_reserved : 12; + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, + nr3_start_seq_ctrl_frag_number : 4, + nr3_per_tid_info_tid_value : 4, + nr3_per_tid_info_reserved : 12; + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, + nr4_start_seq_ctrl_frag_number : 4, + nr4_per_tid_info_tid_value : 4, + nr4_per_tid_info_reserved : 12; + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, + nr5_start_seq_ctrl_frag_number : 4, + nr5_per_tid_info_tid_value : 4, + nr5_per_tid_info_reserved : 12; + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, + nr6_start_seq_ctrl_frag_number : 4, + nr6_per_tid_info_tid_value : 4, + nr6_per_tid_info_reserved : 12; + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, + nr7_start_seq_ctrl_frag_number : 4, + nr7_per_tid_info_tid_value : 4, + nr7_per_tid_info_reserved : 12; + uint32_t dot11be_puncture_bitmap : 16, + u_sig_puncture_pattern_encoding : 6, + reserved_14a : 2, + fb_segment_retransmission_bitmap : 8; + uint32_t rx_chain_mask_type : 1, + scrambler_seed : 7, + rx_duration_field : 16, + rx_chain_mask : 8; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, + sw_peer_id : 16; + uint32_t qos_null_only_response_tx : 1, + reserved_18a : 1, + tbr_trigger_sound_reserved_25_24 : 2, + i2r_rep : 3, + tbr_trigger_sound_reserved_20_12 : 9, + tbr_trigger_common_info_79_68 : 12, + __reserved_g_0005_trigger_subtype : 4; + uint32_t reserved_19b : 3, + u_sig_reserved2 : 5, + reserved_19a : 8, + tbr_trigger_sound_sac : 16; + uint32_t u_sig_reserved1 : 7, + eht_spatial_reuse : 8, + bandwidth_ext : 2, + phy_version : 3, + eht_special_aid12 : 12; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#endif +}; + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/kiwi/v2/pcu_ppdu_setup_init.h new file mode 100644 index 000000000000..8ff86d18db24 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pcu_ppdu_setup_init.h @@ -0,0 +1,2288 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, + response_type : 5, + response_info_part2_required : 1, + response_to_response : 3, + mba_user_order : 2, + expected_mba_size : 11, + required_ul_mu_resp_user_count : 6, + transmitted_bssid_check_en : 1; + uint32_t mprot_required_bw1 : 1, + mprot_required_bw20 : 1, + mprot_required_bw40 : 1, + mprot_required_bw80 : 1, + mprot_required_bw160 : 1, + mprot_required_bw240 : 1, + mprot_required_bw320 : 1, + ppdu_allowed_bw1 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw320 : 1, + set_fc_pwr_mgt : 1, + use_cts_duration_for_data_tx : 1, + update_timestamp_64 : 1, + update_timestamp_32_lower : 1, + update_timestamp_32_upper : 1, + reserved_1a : 13; + uint32_t insert_timestamp_offset_0 : 16, + insert_timestamp_offset_1 : 16; + uint32_t max_bw40_try_count : 4, + max_bw80_try_count : 4, + max_bw160_try_count : 4, + max_bw240_try_count : 4, + max_bw320_try_count : 4, + insert_wur_timestamp_offset : 6, + update_wur_timestamp : 1, + wur_embedded_bssid_present : 1, + insert_wur_fcs : 1, + reserved_3b : 3; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, + r2r_rx_duration_field : 16; + uint32_t r2r_group_id : 6, + r2r_response_frame_type : 4, + r2r_sta_partial_aid : 11, + use_address_fields_for_protection : 1, + r2r_set_required_response_time : 1, + reserved_29a : 3, + r2r_bw20_active_channel : 3, + r2r_bw40_active_channel : 3; + uint32_t r2r_bw80_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw320_active_channel : 3, + r2r_bw20 : 3, + r2r_bw40 : 3, + r2r_bw80 : 3, + r2r_bw160 : 3, + r2r_bw240 : 3, + r2r_bw320 : 3, + reserved_30a : 2; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t mu_response_expected_bitmap_36_32 : 5, + mu_expected_response_cbf_count : 6, + mu_expected_response_sta_count : 6, + transmit_includes_multidestination : 1, + insert_prev_tx_start_timing_info : 1, + insert_current_tx_start_timing_info : 1, + tx_start_transmit_time_byte_offset : 12; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad1_47_32 : 16, + protection_frame_ad2_15_0 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t dynamic_medium_prot_threshold : 24, + dynamic_medium_prot_type : 1, + reserved_54a : 7; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad3_47_32 : 16, + protection_frame_ad4_15_0 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#else + uint32_t transmitted_bssid_check_en : 1, + required_ul_mu_resp_user_count : 6, + expected_mba_size : 11, + mba_user_order : 2, + response_to_response : 3, + response_info_part2_required : 1, + response_type : 5, + medium_prot_type : 3; + uint32_t reserved_1a : 13, + update_timestamp_32_upper : 1, + update_timestamp_32_lower : 1, + update_timestamp_64 : 1, + use_cts_duration_for_data_tx : 1, + set_fc_pwr_mgt : 1, + ppdu_allowed_bw320 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw1 : 1, + mprot_required_bw320 : 1, + mprot_required_bw240 : 1, + mprot_required_bw160 : 1, + mprot_required_bw80 : 1, + mprot_required_bw40 : 1, + mprot_required_bw20 : 1, + mprot_required_bw1 : 1; + uint32_t insert_timestamp_offset_1 : 16, + insert_timestamp_offset_0 : 16; + uint32_t reserved_3b : 3, + insert_wur_fcs : 1, + wur_embedded_bssid_present : 1, + update_wur_timestamp : 1, + insert_wur_timestamp_offset : 6, + max_bw320_try_count : 4, + max_bw240_try_count : 4, + max_bw160_try_count : 4, + max_bw80_try_count : 4, + max_bw40_try_count : 4; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, + r2r_hw_response_tx_duration : 16; + uint32_t r2r_bw40_active_channel : 3, + r2r_bw20_active_channel : 3, + reserved_29a : 3, + r2r_set_required_response_time : 1, + use_address_fields_for_protection : 1, + r2r_sta_partial_aid : 11, + r2r_response_frame_type : 4, + r2r_group_id : 6; + uint32_t reserved_30a : 2, + r2r_bw320 : 3, + r2r_bw240 : 3, + r2r_bw160 : 3, + r2r_bw80 : 3, + r2r_bw40 : 3, + r2r_bw20 : 3, + r2r_bw320_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw80_active_channel : 3; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t tx_start_transmit_time_byte_offset : 12, + insert_current_tx_start_timing_info : 1, + insert_prev_tx_start_timing_info : 1, + transmit_includes_multidestination : 1, + mu_expected_response_sta_count : 6, + mu_expected_response_cbf_count : 6, + mu_response_expected_bitmap_36_32 : 5; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad2_15_0 : 16, + protection_frame_ad1_47_32 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t reserved_54a : 7, + dynamic_medium_prot_type : 1, + dynamic_medium_prot_threshold : 24; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad4_15_0 : 16, + protection_frame_ad3_47_32 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#endif +}; + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0x00000000c0000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pdg_response.h b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response.h new file mode 100644 index 000000000000..6dff64802111 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response.h @@ -0,0 +1,479 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +#define NUM_OF_QWORDS_PDG_RESPONSE 6 + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, + rx_duration_field : 16; + uint32_t punctured_response_transmission : 1, + cca_subband_channel_bonding_mask : 16, + scrambler_seed_override : 2, + response_density_valid : 1, + response_density : 5, + more_data : 1, + duration_indication : 1, + relayed_frame : 1, + address_indicator : 1, + bandwidth : 3; + uint32_t ack_id : 16, + block_ack_bitmap : 16; + uint32_t response_frame_type : 4, + ack_id_ext : 10, + ftm_en : 1, + group_id : 6, + sta_partial_aid : 11; + uint32_t ndp_ba_start_seq_ctrl : 12, + active_channel : 3, + txop_duration_all_ones : 1, + frame_length : 16; +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, + hw_response_tx_duration : 16; + uint32_t bandwidth : 3, + address_indicator : 1, + relayed_frame : 1, + duration_indication : 1, + more_data : 1, + response_density : 5, + response_density_valid : 1, + scrambler_seed_override : 2, + cca_subband_channel_bonding_mask : 16, + punctured_response_transmission : 1; + uint32_t block_ack_bitmap : 16, + ack_id : 16; + uint32_t sta_partial_aid : 11, + group_id : 6, + ftm_en : 1, + ack_id_ext : 10, + response_frame_type : 4; + uint32_t frame_length : 16, + txop_duration_all_ones : 1, + active_channel : 3, + ndp_ba_start_seq_ctrl : 12; +#endif +}; + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000 + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000 + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ACK_ID_LSB 32 +#define PDG_RESPONSE_ACK_ID_MSB 47 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response_rate_setting.h new file mode 100644 index 000000000000..1749452d5809 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pdg_response_rate_setting.h @@ -0,0 +1,418 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, + tx_antenna_sector_ctrl : 24, + pkt_type : 4, + smoothing : 1, + ldpc : 1, + stbc : 1; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + stf_ltf_3db_boost : 1, + force_extra_symbol : 1; + uint32_t alt_rate_mcs : 4, + nss : 3, + dpd_enable : 1, + tx_pwr : 8, + min_tx_pwr : 8, + tx_chain_mask : 8; + uint32_t reserved_3a : 8, + sgi : 2, + rate_mcs : 4, + reserved_3b : 2, + tx_pwr_1 : 8, + alt_tx_pwr_1 : 8; + uint32_t aggregation : 1, + dot11ax_bss_color_id : 6, + dot11ax_spatial_reuse : 4, + dot11ax_cp_ltf_size : 2, + dot11ax_dcm : 1, + dot11ax_doppler_indication : 1, + dot11ax_su_extended : 1, + dot11ax_min_packet_extension : 2, + dot11ax_pe_nss : 3, + dot11ax_pe_content : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_chain_csd_en : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_dl_ul_flag : 1, + reserved_4a : 5; + uint32_t dot11ax_ext_ru_start_index : 4, + dot11ax_ext_ru_size : 4, + eht_duplicate_mode : 2, + he_sigb_dcm : 1, + he_sigb_0_mcs : 3, + num_he_sigb_sym : 5, + required_response_time_source : 1, + reserved_5a : 6, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, + dot11be_params_placeholder : 4; +#else + uint32_t stbc : 1, + ldpc : 1, + smoothing : 1, + pkt_type : 4, + tx_antenna_sector_ctrl : 24, + reserved_0a : 1; + uint32_t force_extra_symbol : 1, + stf_ltf_3db_boost : 1, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t tx_chain_mask : 8, + min_tx_pwr : 8, + tx_pwr : 8, + dpd_enable : 1, + nss : 3, + alt_rate_mcs : 4; + uint32_t alt_tx_pwr_1 : 8, + tx_pwr_1 : 8, + reserved_3b : 2, + rate_mcs : 4, + sgi : 2, + reserved_3a : 8; + uint32_t reserved_4a : 5, + dot11ax_dl_ul_flag : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_chain_csd_en : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_pe_content : 1, + dot11ax_pe_nss : 3, + dot11ax_min_packet_extension : 2, + dot11ax_su_extended : 1, + dot11ax_doppler_indication : 1, + dot11ax_dcm : 1, + dot11ax_cp_ltf_size : 2, + dot11ax_spatial_reuse : 4, + dot11ax_bss_color_id : 6, + aggregation : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_5a : 6, + required_response_time_source : 1, + num_he_sigb_sym : 5, + he_sigb_0_mcs : 3, + he_sigb_dcm : 1, + eht_duplicate_mode : 2, + dot11ax_ext_ru_size : 4, + dot11ax_ext_ru_start_index : 4; + uint32_t dot11be_params_placeholder : 4, + required_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/pdg_tx_req.h b/drivers/staging/fw-api/hw/kiwi/v2/pdg_tx_req.h new file mode 100644 index 000000000000..a954537e537e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/pdg_tx_req.h @@ -0,0 +1,105 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +#define NUM_OF_QWORDS_PDG_TX_REQ 1 + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, + use_puncture_pattern : 2, + req_bw : 3, + puncture_pattern_number : 6, + reserved_0b : 1, + req_paprd : 1, + duration_field_boundary_valid : 1, + duration_field_boundary : 16; + uint32_t puncture_subband_mask : 16, + reserved_0c : 16; +#else + uint32_t duration_field_boundary : 16, + duration_field_boundary_valid : 1, + req_paprd : 1, + reserved_0b : 1, + puncture_pattern_number : 6, + req_bw : 3, + use_puncture_pattern : 2, + tx_reason : 2; + uint32_t reserved_0c : 16, + puncture_subband_mask : 16; +#endif +}; + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0C_LSB 48 +#define PDG_TX_REQ_RESERVED_0C_MSB 63 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/kiwi/v2/phytx_abort_request_info.h new file mode 100644 index 000000000000..ec6ad5a04f9c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/phytx_abort_request_info.h @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, + user_number : 6, + reserved : 2; +#else + uint16_t reserved : 2, + user_number : 6, + phytx_abort_reason : 8; +#endif +}; + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/kiwi/v2/phytx_ppdu_header_info_request.h new file mode 100644 index 000000000000..8e6e268b02b1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/phytx_ppdu_header_info_request.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, + reserved : 11; + uint16_t tlv32_padding : 16; +#else + uint16_t reserved : 11, + request_type : 5; + uint16_t tlv32_padding : 16; +#endif +}; + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_15_8.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_15_8.h new file mode 100644 index 000000000000..df9b22bc1376 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_15_8.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_23_16.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_23_16.h new file mode 100644 index 000000000000..3a7f724d7658 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_23_16.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_31_24.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_31_24.h new file mode 100644 index 000000000000..db8fd4fa68a8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_31_24.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_36_32.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_36_32.h new file mode 100644 index 000000000000..e4748fa8e304 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_36_32.h @@ -0,0 +1,721 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_7_0.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_7_0.h new file mode 100644 index 000000000000..53d81ee64a51 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_7_0.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_info.h b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_info.h new file mode 100644 index 000000000000..500b5c456c16 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_response_user_info.h @@ -0,0 +1,222 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, + mpdu_fcs_fail_count : 12, + qosnull_frame_count : 4, + reserved_0a : 3, + user_info_valid : 1; + uint32_t null_delimiter_count : 22, + reserved_1a : 9, + ht_control_valid : 1; + uint32_t ht_control : 32; + uint32_t qos_control_valid : 16, + eosp : 16; + uint32_t qos_control_15_8_tid_0 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_3 : 8; + uint32_t qos_control_15_8_tid_4 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_7 : 8; + uint32_t qos_control_15_8_tid_8 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_11 : 8; + uint32_t qos_control_15_8_tid_12 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_15 : 8; +#else + uint32_t user_info_valid : 1, + reserved_0a : 3, + qosnull_frame_count : 4, + mpdu_fcs_fail_count : 12, + mpdu_fcs_pass_count : 12; + uint32_t ht_control_valid : 1, + reserved_1a : 9, + null_delimiter_count : 22; + uint32_t ht_control : 32; + uint32_t eosp : 16, + qos_control_valid : 16; + uint32_t qos_control_15_8_tid_3 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_0 : 8; + uint32_t qos_control_15_8_tid_7 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_4 : 8; + uint32_t qos_control_15_8_tid_11 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_8 : 8; + uint32_t qos_control_15_8_tid_15 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_12 : 8; +#endif +}; + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info.h b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info.h new file mode 100644 index 000000000000..047d20f508d1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info.h @@ -0,0 +1,130 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 + +#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; +#else + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info_details.h b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info_details.h new file mode 100644 index 000000000000..61e59fa4788c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/received_trigger_info_details.h @@ -0,0 +1,152 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, + ax_trigger_source : 1, + ax_trigger_type : 4, + trigger_source_sta_full_aid : 13, + frame_control_valid : 1, + qos_control_valid : 1, + he_control_info_valid : 1, + __reserved_g_0005_trigger_subtype : 4, + reserved_0b : 3; + uint32_t phy_ppdu_id : 16, + lsig_response_length : 12, + reserved_1a : 4; + uint32_t frame_control : 16, + qos_control : 16; + uint32_t sw_peer_id : 16, + reserved_3a : 16; + uint32_t he_control : 32; +#else + uint32_t reserved_0b : 3, + __reserved_g_0005_trigger_subtype : 4, + he_control_info_valid : 1, + qos_control_valid : 1, + frame_control_valid : 1, + trigger_source_sta_full_aid : 13, + ax_trigger_type : 4, + ax_trigger_source : 1, + trigger_type : 4; + uint32_t reserved_1a : 4, + lsig_response_length : 12, + phy_ppdu_id : 16; + uint32_t qos_control : 16, + frame_control : 16; + uint32_t reserved_3a : 16, + sw_peer_id : 16; + uint32_t he_control : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/response_end_status.h b/drivers/staging/fw-api/hw/kiwi/v2/response_end_status.h new file mode 100644 index 000000000000..287618e10f25 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/response_end_status.h @@ -0,0 +1,468 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 + +#define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_tx : 1, + global_data_underflow_warning : 1, + response_transmit_status : 4, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + generated_response : 3, + mba_user_count : 7, + mba_fake_bitmap_count : 7, + coex_based_tx_bw : 3, + trig_response_related : 1, + dpdtrain_done : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8; + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + phy_tx_gain_setting : 8, + timing_status : 2, + only_null_delim_sent : 1, + brp_info_valid : 1, + reserved_2a : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t mu_response_bitmap_36_32 : 5, + reserved_4a : 11, + transmit_delay : 16; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t tx_group_delay : 12, + reserved_7a : 4, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_31_16 : 16, + tpc_dbg_info_47_32 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_47_32 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + __reserved_g_0005 : 1, + secure : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 13; + uint32_t tlv64_padding : 32; +#else + uint32_t dpdtrain_done : 1, + trig_response_related : 1, + coex_based_tx_bw : 3, + mba_fake_bitmap_count : 7, + mba_user_count : 7, + generated_response : 3, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + response_transmit_status : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_tx : 1; + uint32_t cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 9, + brp_info_valid : 1, + only_null_delim_sent : 1, + timing_status : 2, + phy_tx_gain_setting : 8, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t transmit_delay : 16, + reserved_4a : 11, + mu_response_bitmap_36_32 : 5; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + reserved_7a : 4, + tx_group_delay : 12; + uint32_t tpc_dbg_info_47_32 : 16, + tpc_dbg_info_31_16 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t reserved_20a : 13, + __reserved_g_0005_ftm_frame_sent : 1, + secure : 1, + __reserved_g_0005 : 1, + addr3_47_32 : 16; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 + +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 + +#define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 +#define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 +#define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 + +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 + +#define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 +#define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 +#define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 + +#define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 +#define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 +#define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/response_start_status.h b/drivers/staging/fw-api/hw/kiwi/v2/response_start_status.h new file mode 100644 index 000000000000..4556dcd5a1b4 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/response_start_status.h @@ -0,0 +1,79 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, + __reserved_g_0012 : 2, + trig_response_related : 1, + response_sta_count : 7, + reserved : 19; + uint32_t phy_ppdu_id : 16, + sw_peer_id : 16; +#else + uint32_t reserved : 19, + response_sta_count : 7, + trig_response_related : 1, + __reserved_g_0012 : 2, + generated_response : 3; + uint32_t sw_peer_id : 16, + phy_ppdu_id : 16; +#endif +}; + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/ru_allocation_160_info.h new file mode 100644 index 000000000000..e622b5dd713e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/ru_allocation_160_info.h @@ -0,0 +1,131 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, + ru_allocation_band0_1 : 9, + reserved_0a : 6, + ru_allocations_01_subband80_mask : 4, + ru_allocations_23_subband80_mask : 4; + uint32_t ru_allocation_band0_2 : 9, + ru_allocation_band0_3 : 9, + reserved_1a : 14; + uint32_t ru_allocation_band1_0 : 9, + ru_allocation_band1_1 : 9, + reserved_2a : 14; + uint32_t ru_allocation_band1_2 : 9, + ru_allocation_band1_3 : 9, + reserved_3a : 14; +#else + uint32_t ru_allocations_23_subband80_mask : 4, + ru_allocations_01_subband80_mask : 4, + reserved_0a : 6, + ru_allocation_band0_1 : 9, + ru_allocation_band0_0 : 9; + uint32_t reserved_1a : 14, + ru_allocation_band0_3 : 9, + ru_allocation_band0_2 : 9; + uint32_t reserved_2a : 14, + ru_allocation_band1_1 : 9, + ru_allocation_band1_0 : 9; + uint32_t reserved_3a : 14, + ru_allocation_band1_3 : 9, + ru_allocation_band1_2 : 9; +#endif +}; + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h new file mode 100644 index 000000000000..f58e7f9f03dc --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,350 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 + +#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, + ba_bitmap_size : 2, + reserved_0b : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0c : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0c : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0b : 3, + ba_bitmap_size : 2, + reserved_0a : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_ack.h new file mode 100644 index 000000000000..e0f3b8e931e1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_ack.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, + explicit_ack : 1, + explict_ack_type : 3, + ba_bitmap_size : 2, + reserved_0a : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0b : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0b : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0a : 3, + ba_bitmap_size : 2, + explict_ack_type : 3, + explicit_ack : 1, + no_bitmap_available : 1; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_req.h new file mode 100644 index 000000000000..de968d0021a1 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_frame_bitmap_req.h @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, + user_request_type : 1, + user_number : 6, + sw_peer_id : 16, + tid_specific_request : 1, + requested_tid : 4, + reserved_0 : 3; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0 : 3, + requested_tid : 4, + tid_specific_request : 1, + sw_peer_id : 16, + user_number : 6, + user_request_type : 1, + explicit_user_request : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 + +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_ack_report.h new file mode 100644 index 000000000000..3448121a2498 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_ack_report.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 + +#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; +#else + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_no_ack_report.h new file mode 100644 index 000000000000..3f7778ff5156 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_ppdu_no_ack_report.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_preamble.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_preamble.h new file mode 100644 index 000000000000..2c60b26ac775 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_preamble.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PREAMBLE 2 + +#define NUM_OF_QWORDS_RX_PREAMBLE 1 + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + pkt_type : 4, + direction : 1, + reserved_0a : 21; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 21, + direction : 1, + pkt_type : 4, + num_users : 6; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 + +#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_TLV64_PADDING_LSB 32 +#define RX_PREAMBLE_TLV64_PADDING_MSB 63 +#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_response_required_info.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_response_required_info.h new file mode 100644 index 000000000000..01c3b946ea6d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_response_required_info.h @@ -0,0 +1,709 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 + +#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + su_or_uplink_mu_reception : 1, + trigger_frame_received : 1, + __reserved_g_0012 : 2, + tb___reserved_g_0005_response_required : 2, + mac_security : 1, + filter_pass_monitor_ovrd : 1, + ast_search_incomplete : 1, + r2r_end_status_to_follow : 1, + reserved_0a : 2, + three_or_more_type_subtypes : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2; + uint32_t general_frame_control : 16, + second_frame_control : 16; + uint32_t duration : 16, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + sgi : 2, + stbc : 1, + ldpc : 1, + ampdu : 1, + vht_ack : 1, + rts_ta_grp_bit : 1; + uint32_t ctrl_frame_soliciting_resp : 1, + ast_fail_for_dot11ax_su_ext : 1, + service_dynamic : 1, + m_pkt : 1, + sta_partial_aid : 12, + group_id : 6, + ctrl_resp_pwr_mgmt : 1, + response_indication : 2, + ndp_indication : 1, + ndp_frame_type : 3, + second_frame_control_valid : 1, + reserved_3a : 2; + uint32_t ack_id : 16, + ack_id_ext : 10, + agc_cbw : 3, + service_cbw : 3; + uint32_t response_sta_count : 7, + reserved : 4, + ht_vht_sig_cbw : 3, + cts_cbw : 3, + response_ack_count : 7, + response_assoc_ack_count : 7, + txop_duration_all_ones : 1; + uint32_t response_ba32_count : 7, + response_ba64_count : 7, + response_ba128_count : 7, + response_ba256_count : 7, + multi_tid : 1, + sw_response_tlv_from_crypto : 1, + dot11ax_dl_ul_flag : 1, + reserved_6a : 1; + uint32_t sw_response_frame_length : 16, + response_ba512_count : 7, + response_ba1024_count : 7, + reserved_7a : 2; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + ftm_fields_valid : 1, + ftm_pe_nss : 3, + ftm_pe_ltf_size : 2, + ftm_pe_content : 1, + ftm_chain_csd_en : 1, + ftm_pe_chain_csd_en : 1; + uint32_t dot11ax_response_rate_source : 8, + dot11ax_ext_response_rate_source : 8, + sw_peer_id : 16; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + eht_duplicate_mode : 2, + force_extra_symbol : 1, + reserved_13a : 5, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, + reserved_after_struct16 : 4; + uint32_t tlv64_padding : 32; +#else + uint32_t wait_sifs : 2, + wait_sifs_config_valid : 1, + three_or_more_type_subtypes : 1, + reserved_0a : 2, + r2r_end_status_to_follow : 1, + ast_search_incomplete : 1, + filter_pass_monitor_ovrd : 1, + mac_security : 1, + tb___reserved_g_0005_response_required : 2, + __reserved_g_0012 : 2, + trigger_frame_received : 1, + su_or_uplink_mu_reception : 1, + phy_ppdu_id : 16; + uint32_t second_frame_control : 16, + general_frame_control : 16; + uint32_t rts_ta_grp_bit : 1, + vht_ack : 1, + ampdu : 1, + ldpc : 1, + stbc : 1, + sgi : 2, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + duration : 16; + uint32_t reserved_3a : 2, + second_frame_control_valid : 1, + ndp_frame_type : 3, + ndp_indication : 1, + response_indication : 2, + ctrl_resp_pwr_mgmt : 1, + group_id : 6, + sta_partial_aid : 12, + m_pkt : 1, + service_dynamic : 1, + ast_fail_for_dot11ax_su_ext : 1, + ctrl_frame_soliciting_resp : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + ack_id_ext : 10, + ack_id : 16; + uint32_t txop_duration_all_ones : 1, + response_assoc_ack_count : 7, + response_ack_count : 7, + cts_cbw : 3, + ht_vht_sig_cbw : 3, + reserved : 4, + response_sta_count : 7; + uint32_t reserved_6a : 1, + dot11ax_dl_ul_flag : 1, + sw_response_tlv_from_crypto : 1, + multi_tid : 1, + response_ba256_count : 7, + response_ba128_count : 7, + response_ba64_count : 7, + response_ba32_count : 7; + uint32_t reserved_7a : 2, + response_ba1024_count : 7, + response_ba512_count : 7, + sw_response_frame_length : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ftm_pe_chain_csd_en : 1, + ftm_chain_csd_en : 1, + ftm_pe_content : 1, + ftm_pe_ltf_size : 2, + ftm_pe_nss : 3, + ftm_fields_valid : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t sw_peer_id : 16, + dot11ax_ext_response_rate_source : 8, + dot11ax_response_rate_source : 8; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_13a : 5, + force_extra_symbol : 1, + eht_duplicate_mode : 2, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_after_struct16 : 4, + he_a_control_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 + +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_start_param.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_start_param.h new file mode 100644 index 000000000000..364538c2c017 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_start_param.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_START_PARAM 2 + +#define NUM_OF_QWORDS_RX_START_PARAM 1 + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + reserved_0a : 12, + remaining_rx_time : 16; + uint32_t tlv64_padding : 32; +#else + uint32_t remaining_rx_time : 16, + reserved_0a : 12, + pkt_type : 4; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 + +#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_START_PARAM_TLV64_PADDING_LSB 32 +#define RX_START_PARAM_TLV64_PADDING_MSB 63 +#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rx_trig_info.h b/drivers/staging/fw-api/hw/kiwi/v2/rx_trig_info.h new file mode 100644 index 000000000000..c246aa15f986 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rx_trig_info.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +#define NUM_OF_QWORDS_RX_TRIG_INFO 1 + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, + trigger_resp_type : 3, + reserved_0 : 27; + uint32_t ppdu_duration : 16, + unique_destination_id : 16; +#else + uint32_t reserved_0 : 27, + trigger_resp_type : 3, + rx_trigger_frame_type : 2; + uint32_t unique_destination_id : 16, + ppdu_duration : 16; +#endif +}; + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/kiwi/v2/rxpcu_early_rx_indication.h new file mode 100644 index 000000000000..4761a1dacd3e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/rxpcu_early_rx_indication.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 + +#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + dot11ax_received_ext_ru_size : 4, + reserved_0a : 19; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 19, + dot11ax_received_ext_ru_size : 4, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0 + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00 + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000 + +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_cbf_info.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_cbf_info.h new file mode 100644 index 000000000000..c84dac34f70b --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_cbf_info.h @@ -0,0 +1,464 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_CBF_INFO 16 + +#define NUM_OF_QWORDS_TX_CBF_INFO 8 + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, + pre_cbf_duration : 16; + uint32_t brpoll_info_valid : 1, + trigger_brpoll_info_valid : 1, + npda_info_11ac_valid : 1, + npda_info_11ax_valid : 1, + dot11ax_su_extended : 1, + bandwidth : 3, + brpoll_info : 8, + cbf_response_table_base_index : 8, + peer_index : 3, + pkt_type : 4, + txop_duration_all_ones : 1; + uint32_t trigger_brpoll_common_info_15_0 : 16, + trigger_brpoll_common_info_31_16 : 16; + uint32_t trigger_brpoll_user_info_15_0 : 16, + trigger_brpoll_user_info_31_16 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + sta_partial_aid : 11, + reserved_8a : 4, + cbf_resp_pwr_mgmt : 1; + uint32_t group_id : 6, + rssi_comb : 8, + reserved_9a : 2, + vht_ndpa_sta_info : 16; + uint32_t he_eht_sta_info_15_0 : 16, + he_eht_sta_info_31_16 : 16; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_dl_ul_flag : 1, + reserved_11a : 8; + uint32_t sw_response_frame_length : 16, + sw_response_tlv_from_crypto : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2, + __reserved_g_0005 : 1, + secure : 1, + tb___reserved_g_0005_response_required : 2, + reserved_12a : 2, + u_sig_puncture_pattern_encoding : 6; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + npda_info_11be_valid : 1, + eht_duplicate_mode : 2, + reserved_13a : 11; + uint32_t eht_sta_info_39_32 : 8, + reserved_14a : 24; + uint32_t tlv64_padding : 32; +#else + uint32_t pre_cbf_duration : 16, + sw_peer_id : 16; + uint32_t txop_duration_all_ones : 1, + pkt_type : 4, + peer_index : 3, + cbf_response_table_base_index : 8, + brpoll_info : 8, + bandwidth : 3, + dot11ax_su_extended : 1, + npda_info_11ax_valid : 1, + npda_info_11ac_valid : 1, + trigger_brpoll_info_valid : 1, + brpoll_info_valid : 1; + uint32_t trigger_brpoll_common_info_31_16 : 16, + trigger_brpoll_common_info_15_0 : 16; + uint32_t trigger_brpoll_user_info_31_16 : 16, + trigger_brpoll_user_info_15_0 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t cbf_resp_pwr_mgmt : 1, + reserved_8a : 4, + sta_partial_aid : 11, + addr3_47_32 : 16; + uint32_t vht_ndpa_sta_info : 16, + reserved_9a : 2, + rssi_comb : 8, + group_id : 6; + uint32_t he_eht_sta_info_31_16 : 16, + he_eht_sta_info_15_0 : 16; + uint32_t reserved_11a : 8, + dot11ax_dl_ul_flag : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_12a : 2, + tb___reserved_g_0005_response_required : 2, + secure : 1, + __reserved_g_0005 : 1, + wait_sifs : 2, + wait_sifs_config_valid : 1, + sw_response_tlv_from_crypto : 1, + sw_response_frame_length : 16; + uint32_t reserved_13a : 11, + eht_duplicate_mode : 2, + npda_info_11be_valid : 1, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_14a : 24, + eht_sta_info_39_32 : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BANDWIDTH_LSB 37 +#define TX_CBF_INFO_BANDWIDTH_MSB 39 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PEER_INDEX_LSB 56 +#define TX_CBF_INFO_PEER_INDEX_MSB 58 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PKT_TYPE_LSB 59 +#define TX_CBF_INFO_PKT_TYPE_MSB 62 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_47_32_LSB 32 +#define TX_CBF_INFO_ADDR1_47_32_MSB 47 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR2_15_0_LSB 48 +#define TX_CBF_INFO_ADDR2_15_0_MSB 63 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR3_31_0_LSB 32 +#define TX_CBF_INFO_ADDR3_31_0_MSB 63 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000 + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_GROUP_ID_LSB 32 +#define TX_CBF_INFO_GROUP_ID_MSB 37 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RSSI_COMB_LSB 38 +#define TX_CBF_INFO_RSSI_COMB_MSB 45 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_9A_LSB 46 +#define TX_CBF_INFO_RESERVED_9A_MSB 47 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_RESERVED_11A_LSB 56 +#define TX_CBF_INFO_RESERVED_11A_MSB 63 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 + +#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000 + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 24 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000 + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_13A_LSB 53 +#define TX_CBF_INFO_RESERVED_13A_MSB 63 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00 + +#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_TLV64_PADDING_LSB 32 +#define TX_CBF_INFO_TLV64_PADDING_MSB 63 +#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_setup.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_setup.h new file mode 100644 index 000000000000..3c6ac61fba18 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_setup.h @@ -0,0 +1,487 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +#define NUM_OF_QWORDS_TX_FES_SETUP 5 + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t fes_in_11ax_trigger_response_config : 1, + bo_based_tid_aggregation_limit : 4, + __reserved_g_0005 : 1, + expect_i2r_lmr : 1, + transmit_start_reason : 3, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + puncture_from_all_allowed_modes : 1, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + number_of_users : 6, + mu_type : 1, + ofdma_triggered_response : 1, + response_to_response_cmd : 1; + uint32_t schedule_try : 4, + ndp_frame : 2, + txbf : 1, + allow_txop_exceed_in_1st_pkt : 1, + ignore_bw_available : 1, + ignore_tbtt : 1, + static_bandwidth : 3, + set_txop_duration_all_ones : 1, + transmission_contains_mu_rts : 1, + bw_restricted_frames_embedded : 1, + ast_index : 16; + uint32_t cv_id : 8, + trigger_resp_txpdu_ppdu_boundary : 2, + rxpcu_setup_complete_present : 1, + rbo_must_have_data_user_limit : 4, + mu_ndp : 1, + bf_type : 2, + cbf_nc_index_mask : 1, + cbf_nc_index : 3, + cbf_nr_index_mask : 1, + cbf_nr_index : 3, + secure___reserved_g_0005_ista : 1, + ndpa : 1, + wait_sifs : 2, + cbf_feedback_type_mask : 1, + cbf_feedback_type : 1; + uint32_t cbf_sounding_token : 6, + cbf_sounding_token_mask : 1, + cbf_bw_mask : 1, + cbf_bw : 3, + use_static_bw : 1, + coex_nack_count : 5, + sch_tx_burst_ongoing : 1, + gen_tqm_update_mpdu_count_tlv : 1, + transmit_vif : 4, + optimal_bw_retry_count : 4, + fes_continuation_ratio_threshold : 5; + uint32_t transmit_cca_bitmap : 32; + uint32_t tb___reserved_g_0005 : 1, + __reserved_g_0005_trigger_subtype : 4, + min_cts2self_count : 4, + max_cts2self_count : 4, + wifi_radar_enable : 1, + reserved_6a : 18; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t monitor_override_sta_36_32 : 5, + reserved_8a : 27; + uint32_t fw2sw_info : 32; +#else + uint32_t schedule_id : 32; + uint32_t response_to_response_cmd : 1, + ofdma_triggered_response : 1, + mu_type : 1, + number_of_users : 6, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + puncture_from_all_allowed_modes : 1, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + transmit_start_reason : 3, + expect_i2r_lmr : 1, + __reserved_g_0005 : 1, + bo_based_tid_aggregation_limit : 4, + fes_in_11ax_trigger_response_config : 1; + uint32_t ast_index : 16, + bw_restricted_frames_embedded : 1, + transmission_contains_mu_rts : 1, + set_txop_duration_all_ones : 1, + static_bandwidth : 3, + ignore_tbtt : 1, + ignore_bw_available : 1, + allow_txop_exceed_in_1st_pkt : 1, + txbf : 1, + ndp_frame : 2, + schedule_try : 4; + uint32_t cbf_feedback_type : 1, + cbf_feedback_type_mask : 1, + wait_sifs : 2, + ndpa : 1, + secure___reserved_g_0005_ista : 1, + cbf_nr_index : 3, + cbf_nr_index_mask : 1, + cbf_nc_index : 3, + cbf_nc_index_mask : 1, + bf_type : 2, + mu_ndp : 1, + rbo_must_have_data_user_limit : 4, + rxpcu_setup_complete_present : 1, + trigger_resp_txpdu_ppdu_boundary : 2, + cv_id : 8; + uint32_t fes_continuation_ratio_threshold : 5, + optimal_bw_retry_count : 4, + transmit_vif : 4, + gen_tqm_update_mpdu_count_tlv : 1, + sch_tx_burst_ongoing : 1, + coex_nack_count : 5, + use_static_bw : 1, + cbf_bw : 3, + cbf_bw_mask : 1, + cbf_sounding_token_mask : 1, + cbf_sounding_token : 6; + uint32_t transmit_cca_bitmap : 32; + uint32_t reserved_6a : 18, + wifi_radar_enable : 1, + max_cts2self_count : 4, + min_cts2self_count : 4, + __reserved_g_0005_trigger_subtype : 4, + tb___reserved_g_0005 : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t reserved_8a : 27, + monitor_override_sta_36_32 : 5; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_MU_TYPE_LSB 61 +#define TX_FES_SETUP_MU_TYPE_MSB 61 +#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 + +#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CV_ID_LSB 32 +#define TX_FES_SETUP_CV_ID_MSB 39 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_MU_NDP_LSB 47 +#define TX_FES_SETUP_MU_NDP_MSB 47 +#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BF_TYPE_LSB 48 +#define TX_FES_SETUP_BF_TYPE_MSB 49 +#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDPA_LSB 59 +#define TX_FES_SETUP_NDPA_MSB 59 +#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_WAIT_SIFS_LSB 60 +#define TX_FES_SETUP_WAIT_SIFS_MSB 61 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 + +#define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 +#define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 +#define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 31 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 5 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_FW2SW_INFO_LSB 32 +#define TX_FES_SETUP_FW2SW_INFO_MSB 63 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_1k_ba.h new file mode 100644 index 000000000000..97238a99431f --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_1k_ba.h @@ -0,0 +1,329 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#endif +}; + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_ack_or_ba.h new file mode 100644 index 000000000000..6ddc78925274 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_ack_or_ba.h @@ -0,0 +1,161 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#endif +}; + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_end.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_end.h new file mode 100644 index 000000000000..5061be22988e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_end.h @@ -0,0 +1,739 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 22 + +#define NUM_OF_QWORDS_TX_FES_STATUS_END 11 + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_rx : 1, + global_data_underflow_warning : 1, + global_fes_transmit_result : 4, + cbf_bw_received_valid : 1, + cbf_bw_received : 3, + actual_received_ack_type : 4, + sta_response_count : 6, + dpdtrain_done : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, + brp_info_valid : 1, + reserved_1a : 6, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + fes_in_11ax_trigger_response_config : 1, + null_delim_inserted_before_mpdus : 1, + only_null_delim_sent : 1; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t terminate___reserved_g_0005_sequence : 1, + reserved_4a : 7, + timing_status : 2, + response_type : 5, + r2r_end_status_to_follow : 1, + transmit_delay : 16; + uint32_t tx_group_delay : 12, + reserved_5a : 4, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_cmn_31_16 : 16, + tpc_dbg_info_47_32 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_47_32 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; + uint32_t beamform_masked_user_bitmap_15_0 : 16, + beamform_masked_user_bitmap_31_16 : 16; + uint32_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8, + highest_achieved_data_null_ratio : 5, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + beamform_masked_user_bitmap_36_32 : 5, + pdg_mpdu_ready : 1; + uint32_t pdg_mpdu_count : 16, + pdg_est_mpdu_tx_count : 16; + uint32_t pdg_overview_length : 24, + txop_duration : 7, + pdg_dropped_mpdu_warning : 1; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + fec_type : 1, + stbc : 1, + num_data_symbols : 16, + ru_size : 4, + reserved_17a : 4; + uint32_t num_ltf_symbols : 3, + ltf_size : 2, + cp_setting : 2, + reserved_18a : 5, + dcm : 1, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_18b : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8; + uint32_t __reserved_g_0005_active_user_map : 16, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 6, + cv_corr_status : 8; + uint32_t current_tx_duration : 16, + reserved_21a : 16; +#else + uint32_t dpdtrain_done : 1, + sta_response_count : 6, + actual_received_ack_type : 4, + cbf_bw_received : 3, + cbf_bw_received_valid : 1, + global_fes_transmit_result : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_bt_tx_while_wlan_tx : 1; + uint32_t only_null_delim_sent : 1, + null_delim_inserted_before_mpdus : 1, + fes_in_11ax_trigger_response_config : 1, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + reserved_1a : 6, + brp_info_valid : 1, + reserved_after_struct16 : 4; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t transmit_delay : 16, + r2r_end_status_to_follow : 1, + response_type : 5, + timing_status : 2, + reserved_4a : 7, + terminate___reserved_g_0005_sequence : 1; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + reserved_5a : 4, + tx_group_delay : 12; + uint32_t tpc_dbg_info_47_32 : 16, + tpc_dbg_info_cmn_31_16 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; + uint32_t beamform_masked_user_bitmap_31_16 : 16, + beamform_masked_user_bitmap_15_0 : 16; + uint32_t pdg_mpdu_ready : 1, + beamform_masked_user_bitmap_36_32 : 5, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + highest_achieved_data_null_ratio : 5, + cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + uint32_t pdg_est_mpdu_tx_count : 16, + pdg_mpdu_count : 16; + uint32_t pdg_dropped_mpdu_warning : 1, + txop_duration : 7, + pdg_overview_length : 24; + uint32_t reserved_17a : 4, + ru_size : 4, + num_data_symbols : 16, + stbc : 1, + fec_type : 1, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t tx_pwr_unshared : 8, + tx_pwr_shared : 8, + reserved_18b : 1, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + dcm : 1, + reserved_18a : 5, + cp_setting : 2, + ltf_size : 2, + num_ltf_symbols : 3; + uint32_t cv_corr_status : 8, + reserved_20a : 6, + __reserved_g_0005_ftm_frame_sent : 1, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_active_user_map : 16; + uint32_t reserved_21a : 16, + current_tx_duration : 16; +#endif +}; + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 + +#define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 53 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_4A_LSB 1 +#define TX_FES_STATUS_END_RESERVED_4A_MSB 7 +#define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe + +#define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 +#define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 +#define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 + +#define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 44 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 47 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 35 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 36 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_CP_SETTING_LSB 37 +#define TX_FES_STATUS_END_CP_SETTING_MSB 38 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 39 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 43 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 + +#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_DCM_LSB 44 +#define TX_FES_STATUS_END_DCM_MSB 44 +#define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 + +#define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_20A_LSB 18 +#define TX_FES_STATUS_END_RESERVED_20A_MSB 23 +#define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 48 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 63 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_prot.h new file mode 100644 index 000000000000..fed16b594806 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_prot.h @@ -0,0 +1,340 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 + +#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + reserved_0 : 20, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4; + uint32_t frame_type : 2, + frame_subtype : 4, + rx_pwr_mgmt : 1, + status : 1, + duration_field : 16, + reserved_1a : 2, + agc_cbw : 3, + service_cbw : 3; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t tx_group_delay : 12, + timing_status : 2, + dpdtrain_done : 1, + reserved_4 : 1, + transmit_delay : 16; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + tpc_dbg_info_cmn_31_16 : 16; + uint32_t tpc_dbg_info_cmn_47_32 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; +#else + uint32_t rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + reserved_0 : 20, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + success : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + reserved_1a : 2, + duration_field : 16, + status : 1, + rx_pwr_mgmt : 1, + frame_subtype : 4, + frame_type : 2; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t transmit_delay : 16, + reserved_4 : 1, + dpdtrain_done : 1, + timing_status : 2, + tx_group_delay : 12; + uint32_t tpc_dbg_info_cmn_31_16 : 16, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_cmn_47_32 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_47_32 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; +#endif +}; + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_STATUS_LSB 39 +#define TX_FES_STATUS_PROT_STATUS_MSB 39 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff + +#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 + +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 + +#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 + +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start.h new file mode 100644 index 000000000000..2b87d6dbe791 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t reserved_1a : 8, + transmit_start_reason : 3, + disabled_user_bitmap_36_32 : 5, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + schedule_try : 4, + medium_prot_type : 3, + reserved_1b : 2; + uint32_t optimal_bw_try_count : 4, + number_of_users : 7, + coex_nack_count : 5, + cca_ed0 : 16; + uint32_t disabled_user_bitmap_31_0 : 32; +#else + uint32_t schedule_id : 32; + uint32_t reserved_1b : 2, + medium_prot_type : 3, + schedule_try : 4, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + disabled_user_bitmap_36_32 : 5, + transmit_start_reason : 3, + reserved_1a : 8; + uint32_t cca_ed0 : 16, + coex_nack_count : 5, + number_of_users : 7, + optimal_bw_try_count : 4; + uint32_t disabled_user_bitmap_31_0 : 32; +#endif +}; + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_ppdu.h new file mode 100644 index 000000000000..d008fc794224 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_ppdu.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 2 + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + ndp_frame : 2, + reserved_2b : 2, + coex_based_tx_bw : 3, + coex_based_ant_mask : 8, + reserved_2c : 1; + uint32_t coex_based_tx_pwr_shared_ant : 8, + coex_based_tx_pwr_ant : 8, + concurrent_bt_tx : 1, + concurrent_wlan_tx : 1, + concurrent_wan_tx : 1, + concurrent_wan_rx : 1, + coex_pwr_reduction_bt : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_wan : 1, + coex_result_alt_based : 1, + request_packet_bw : 3, + response_type : 5; +#else + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t reserved_2c : 1, + coex_based_ant_mask : 8, + coex_based_tx_bw : 3, + reserved_2b : 2, + ndp_frame : 2, + subband_mask : 16; + uint32_t response_type : 5, + request_packet_bw : 3, + coex_result_alt_based : 1, + coex_pwr_reduction_wan : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_bt : 1, + concurrent_wan_rx : 1, + concurrent_wan_tx : 1, + concurrent_wlan_tx : 1, + concurrent_bt_tx : 1, + coex_based_tx_pwr_ant : 8, + coex_based_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000030000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x00000000000c0000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_prot.h new file mode 100644 index 000000000000..9e7bbe980258 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_start_prot.h @@ -0,0 +1,168 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 2 + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + reserved_2b : 4, + prot_coex_based_tx_bw : 3, + prot_coex_based_ant_mask : 8, + prot_coex_result_alt_based : 1; + uint32_t prot_coex_tx_pwr_shared_ant : 8, + prot_coex_tx_pwr_ant : 8, + prot_concurrent_bt_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wan_rx : 1, + prot_coex_pwr_reduction_bt : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_wan : 1, + prot_request_packet_bw : 3, + response_type : 5, + reserved_3a : 1; +#else + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t prot_coex_result_alt_based : 1, + prot_coex_based_ant_mask : 8, + prot_coex_based_tx_bw : 3, + reserved_2b : 4, + subband_mask : 16; + uint32_t reserved_3a : 1, + response_type : 5, + prot_request_packet_bw : 3, + prot_coex_pwr_reduction_wan : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_bt : 1, + prot_concurrent_wan_rx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_bt_tx : 1, + prot_coex_tx_pwr_ant : 8, + prot_coex_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_ppdu.h new file mode 100644 index 000000000000..84732390eb1d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_ppdu.h @@ -0,0 +1,210 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + bw_drop_underflow_warning : 1, + qc_eosp_setting : 1, + fc_more_data_setting : 1, + fc_pwr_mgt_setting : 1, + mpdu_tx_count : 9, + user_blocked : 1, + pre_trig_response_delim_count : 7; + uint32_t underflow_byte_count : 16, + coex_abort_mpdu_count_valid : 1, + coex_abort_mpdu_count : 9, + transmitted_tid : 4, + txdma_dropped_mpdu_warning : 1, + reserved_1 : 1; + uint32_t duration : 16, + num_eof_delim_added : 16; + uint32_t psdu_octet : 24, + qos_buf_state : 8; + uint32_t num_null_delim_added : 22, + reserved_4a : 2, + cv_corr_user_valid_in_phy : 1, + nss : 3, + mcs : 4; + uint32_t ht_control : 32; +#else + uint32_t pre_trig_response_delim_count : 7, + user_blocked : 1, + mpdu_tx_count : 9, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 1, + qc_eosp_setting : 1, + bw_drop_underflow_warning : 1, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t reserved_1 : 1, + txdma_dropped_mpdu_warning : 1, + transmitted_tid : 4, + coex_abort_mpdu_count : 9, + coex_abort_mpdu_count_valid : 1, + underflow_byte_count : 16; + uint32_t num_eof_delim_added : 16, + duration : 16; + uint32_t qos_buf_state : 8, + psdu_octet : 24; + uint32_t mcs : 4, + nss : 3, + cv_corr_user_valid_in_phy : 1, + reserved_4a : 2, + num_null_delim_added : 22; + uint32_t ht_control : 32; +#endif +}; + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_response.h new file mode 100644 index 000000000000..da58b669a450 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_fes_status_user_response.h @@ -0,0 +1,74 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, + reserved_0 : 28; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; +#else + uint32_t reserved_0 : 28, + fes_transmit_result : 4; + uint32_t reserved_after_struct16 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_flush_req.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_flush_req.h new file mode 100644 index 000000000000..bcb5be4a4e96 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_flush_req.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 + +#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, + phytx_abort_reason : 8, + flush_req_user_number_or_link_id : 6, + mlo_abort_reason : 5, + reserved_0a : 5; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 5, + mlo_abort_reason : 5, + flush_req_user_number_or_link_id : 6, + phytx_abort_reason : 8, + flush_req_reason : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 + +#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 +#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 +#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_mpdu_start.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_mpdu_start.h new file mode 100644 index 000000000000..a7006918117f --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_mpdu_start.h @@ -0,0 +1,308 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MPDU_START 10 + +#define NUM_OF_QWORDS_TX_MPDU_START 5 + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, + frame_not_from_tqm : 1, + vht_control_present : 1, + mpdu_header_length : 8, + retry_count : 7, + wds : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_47_32 : 16, + mpdu_sequence_number : 12, + raw_already_encrypted : 1, + frame_type : 2, + txdma_dropped_mpdu_warning : 1; + uint32_t iv_byte_0 : 8, + iv_byte_1 : 8, + iv_byte_2 : 8, + iv_byte_3 : 8; + uint32_t iv_byte_4 : 8, + iv_byte_5 : 8, + iv_byte_6 : 8, + iv_byte_7 : 8; + uint32_t iv_byte_8 : 8, + iv_byte_9 : 8, + iv_byte_10 : 8, + iv_byte_11 : 8; + uint32_t iv_byte_12 : 8, + iv_byte_13 : 8, + iv_byte_14 : 8, + iv_byte_15 : 8; + uint32_t iv_byte_16 : 8, + iv_byte_17 : 8, + iv_len : 5, + icv_len : 5, + vht_control_offset : 6; + uint32_t mpdu_type : 1, + transmit_bw_restriction : 1, + allowed_transmit_bw : 4, + tx_notify_frame : 3, + reserved_8a : 23; + uint32_t tlv64_padding : 32; +#else + uint32_t wds : 1, + retry_count : 7, + mpdu_header_length : 8, + vht_control_present : 1, + frame_not_from_tqm : 1, + mpdu_length : 14; + uint32_t pn_31_0 : 32; + uint32_t txdma_dropped_mpdu_warning : 1, + frame_type : 2, + raw_already_encrypted : 1, + mpdu_sequence_number : 12, + pn_47_32 : 16; + uint32_t iv_byte_3 : 8, + iv_byte_2 : 8, + iv_byte_1 : 8, + iv_byte_0 : 8; + uint32_t iv_byte_7 : 8, + iv_byte_6 : 8, + iv_byte_5 : 8, + iv_byte_4 : 8; + uint32_t iv_byte_11 : 8, + iv_byte_10 : 8, + iv_byte_9 : 8, + iv_byte_8 : 8; + uint32_t iv_byte_15 : 8, + iv_byte_14 : 8, + iv_byte_13 : 8, + iv_byte_12 : 8; + uint32_t vht_control_offset : 6, + icv_len : 5, + iv_len : 5, + iv_byte_17 : 8, + iv_byte_16 : 8; + uint32_t reserved_8a : 23, + tx_notify_frame : 3, + allowed_transmit_bw : 4, + transmit_bw_restriction : 1, + mpdu_type : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 + +#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x0000000080000000 + +#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 +#define TX_MPDU_START_PN_31_0_LSB 32 +#define TX_MPDU_START_PN_31_0_MSB 63 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 + +#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_0_LSB 32 +#define TX_MPDU_START_IV_BYTE_0_MSB 39 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_1_LSB 40 +#define TX_MPDU_START_IV_BYTE_1_MSB 47 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_2_LSB 48 +#define TX_MPDU_START_IV_BYTE_2_MSB 55 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_3_LSB 56 +#define TX_MPDU_START_IV_BYTE_3_MSB 63 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_8_LSB 32 +#define TX_MPDU_START_IV_BYTE_8_MSB 39 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_9_LSB 40 +#define TX_MPDU_START_IV_BYTE_9_MSB 47 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_10_LSB 48 +#define TX_MPDU_START_IV_BYTE_10_MSB 55 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_11_LSB 56 +#define TX_MPDU_START_IV_BYTE_11_MSB 63 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_16_LSB 32 +#define TX_MPDU_START_IV_BYTE_16_MSB 39 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_17_LSB 40 +#define TX_MPDU_START_IV_BYTE_17_MSB 47 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_LEN_LSB 48 +#define TX_MPDU_START_IV_LEN_MSB 52 +#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_ICV_LEN_LSB 53 +#define TX_MPDU_START_ICV_LEN_MSB 57 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 + +#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TLV64_PADDING_LSB 32 +#define TX_MPDU_START_TLV64_PADDING_MSB 63 +#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_msdu_start.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_msdu_start.h new file mode 100644 index 000000000000..04d105db7488 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_msdu_start.h @@ -0,0 +1,266 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_START 8 + +#define NUM_OF_QWORDS_TX_MSDU_START 4 + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, + first_msdu : 1, + last_msdu : 1, + encap_type : 2, + epd_en : 1, + da_sa_present : 2, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + dummy_msdu_delimitation : 1, + reserved_0a : 5; + uint32_t tso_enable : 1, + reserved_1a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + mesh_enable : 1, + reserved_1b : 6; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + checksum_offset : 13, + partial_checksum_en : 1, + reserved_4 : 2; + uint32_t payload_start_offset : 14, + reserved_5a : 2, + payload_end_offset : 14, + reserved_5b : 2; + uint32_t udp_length : 16, + reserved_6 : 16; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 5, + dummy_msdu_delimitation : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + da_sa_present : 2, + epd_en : 1, + encap_type : 2, + last_msdu : 1, + first_msdu : 1, + msdu_len : 14; + uint32_t reserved_1b : 6, + mesh_enable : 1, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_1a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t reserved_4 : 2, + partial_checksum_en : 1, + checksum_offset : 13, + ip_identification : 16; + uint32_t reserved_5b : 2, + payload_end_offset : 14, + reserved_5a : 2, + payload_start_offset : 14; + uint32_t reserved_6 : 16, + udp_length : 16; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 + +#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TSO_ENABLE_LSB 32 +#define TX_MSDU_START_TSO_ENABLE_MSB 32 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1A_LSB 33 +#define TX_MSDU_START_RESERVED_1A_MSB 38 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_LSB 39 +#define TX_MSDU_START_TCP_FLAG_MSB 47 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MESH_ENABLE_LSB 57 +#define TX_MSDU_START_MESH_ENABLE_MSB 57 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1B_LSB 58 +#define TX_MSDU_START_RESERVED_1B_MSB 63 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5A_LSB 46 +#define TX_MSDU_START_RESERVED_5A_MSB 47 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5B_LSB 62 +#define TX_MSDU_START_RESERVED_5B_MSB 63 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 + +#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 +#define TX_MSDU_START_TLV64_PADDING_LSB 32 +#define TX_MSDU_START_TLV64_PADDING_MSB 63 +#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_peer_entry.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_peer_entry.h new file mode 100644 index 000000000000..d9213c4e8813 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_peer_entry.h @@ -0,0 +1,295 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +#define NUM_OF_QWORDS_TX_PEER_ENTRY 9 + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_a_47_32 : 16, + mac_addr_b_15_0 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t use_ad_b : 1, + strip_insert_vlan_inner : 1, + strip_insert_vlan_outer : 1, + vlan_llc_mode : 1, + key_type : 4, + a_msdu_wds_ad3_ad4 : 3, + ignore_hard_filters : 1, + ignore_soft_filters : 1, + epd_output : 1, + wds : 1, + insert_or_strip : 1, + sw_filter_id : 16; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t sta_partial_aid : 11, + transmit_vif : 4, + block_this_user : 1, + mesh_amsdu_mode : 2, + use_qos_alt_mute_mask : 1, + dl_ul_direction : 1, + reserved_12 : 12; + uint32_t insert_vlan_outer_tci : 16, + insert_vlan_inner_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t multi_link_addr_crypto_enable : 1, + reserved_17a : 15, + sw_peer_id : 16; +#else + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_b_15_0 : 16, + mac_addr_a_47_32 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t sw_filter_id : 16, + insert_or_strip : 1, + wds : 1, + epd_output : 1, + ignore_soft_filters : 1, + ignore_hard_filters : 1, + a_msdu_wds_ad3_ad4 : 3, + key_type : 4, + vlan_llc_mode : 1, + strip_insert_vlan_outer : 1, + strip_insert_vlan_inner : 1, + use_ad_b : 1; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t reserved_12 : 12, + dl_ul_direction : 1, + use_qos_alt_mute_mask : 1, + mesh_amsdu_mode : 2, + block_this_user : 1, + transmit_vif : 4, + sta_partial_aid : 11; + uint32_t insert_vlan_inner_tci : 16, + insert_vlan_outer_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t sw_peer_id : 16, + reserved_17a : 15, + multi_link_addr_crypto_enable : 1; +#endif +}; + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_USE_AD_B_LSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_WDS_LSB 46 +#define TX_PEER_ENTRY_WDS_MSB 46 +#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 33 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_queue_extension.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_queue_extension.h new file mode 100644 index 000000000000..938e3bcad7b8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_queue_extension.h @@ -0,0 +1,322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, + qos_ctl : 16; + uint32_t ampdu_flag : 1, + tx_notify_no_htc_override : 1, + reserved_1a : 7, + checksum_tso_disable_for_frag : 1, + key_id : 8, + qos_buf_state_overwrite : 1, + buf_state_sta_id : 1, + buf_state_source : 1, + ht_control_overwrite_enable : 1, + ht_control_overwrite_source : 4, + reserved_1b : 6; + uint32_t ul_headroom_insertion_enable : 1, + ul_headroom_offset : 5, + bqrp_insertion_enable : 1, + bqrp_offset : 5, + ul_headroom_rsvd_7_6 : 2, + bqr_rsvd_9_8 : 2, + base_pn_63_48 : 16; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t cas_control_info : 8, + cas_offset : 5, + cas_insertion_enable : 1, + reserved_10a : 2, + ht_control_overwrite_source_for_srp : 4, + ht_control_overwrite_source_for_bsrp : 4, + reserved_10b : 6, + mpdu_hdr_len_override_en : 1, + bar_ssn_overwrite_enable : 1; + uint32_t bar_ssn_offset : 12, + mpdu_hdr_len_override_val : 9, + reserved_11a : 11; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#else + uint32_t qos_ctl : 16, + frame_ctl : 16; + uint32_t reserved_1b : 6, + ht_control_overwrite_source : 4, + ht_control_overwrite_enable : 1, + buf_state_source : 1, + buf_state_sta_id : 1, + qos_buf_state_overwrite : 1, + key_id : 8, + checksum_tso_disable_for_frag : 1, + reserved_1a : 7, + tx_notify_no_htc_override : 1, + ampdu_flag : 1; + uint32_t base_pn_63_48 : 16, + bqr_rsvd_9_8 : 2, + ul_headroom_rsvd_7_6 : 2, + bqrp_offset : 5, + bqrp_insertion_enable : 1, + ul_headroom_offset : 5, + ul_headroom_insertion_enable : 1; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t bar_ssn_overwrite_enable : 1, + mpdu_hdr_len_override_en : 1, + reserved_10b : 6, + ht_control_overwrite_source_for_bsrp : 4, + ht_control_overwrite_source_for_srp : 4, + reserved_10a : 2, + cas_insertion_enable : 1, + cas_offset : 5, + cas_control_info : 8; + uint32_t reserved_11a : 11, + mpdu_hdr_len_override_val : 9, + bar_ssn_offset : 12; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/kiwi/v2/tx_raw_or_native_frame_setup.h new file mode 100644 index 000000000000..c54443a32721 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/tx_raw_or_native_frame_setup.h @@ -0,0 +1,280 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 1 + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, + fc_from_ds_mask : 1, + fc_more_frag_mask : 1, + fc_retry_mask : 1, + fc_pwr_mgt_mask : 1, + fc_more_data_mask : 1, + fc_prot_frame_mask : 1, + fc_order_mask : 1, + duration_field_mask : 1, + sequence_control_mask : 1, + qc_tid_mask : 1, + qc_eosp_mask : 1, + qc_ack_policy_mask : 1, + qc_amsdu_mask : 1, + reserved_0a : 1, + qc_15to8_mask : 1, + iv_mask : 1, + fc_to_ds_setting : 1, + fc_from_ds_setting : 1, + fc_more_frag_setting : 1, + fc_retry_setting : 2, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 2, + fc_prot_frame_setting : 2, + fc_order_setting : 1, + qc_tid_setting : 4; + uint32_t qc_eosp_setting : 2, + qc_ack_policy_setting : 2, + qc_amsdu_setting : 1, + qc_15to8_setting : 8, + mlo_addr_override : 1, + mlo_ignore_addr3_override : 1, + sequence_control_source : 1, + fragment_number : 4, + sequence_number : 12; +#else + uint32_t qc_tid_setting : 4, + fc_order_setting : 1, + fc_prot_frame_setting : 2, + fc_more_data_setting : 2, + fc_pwr_mgt_setting : 1, + fc_retry_setting : 2, + fc_more_frag_setting : 1, + fc_from_ds_setting : 1, + fc_to_ds_setting : 1, + iv_mask : 1, + qc_15to8_mask : 1, + reserved_0a : 1, + qc_amsdu_mask : 1, + qc_ack_policy_mask : 1, + qc_eosp_mask : 1, + qc_tid_mask : 1, + sequence_control_mask : 1, + duration_field_mask : 1, + fc_order_mask : 1, + fc_prot_frame_mask : 1, + fc_more_data_mask : 1, + fc_pwr_mgt_mask : 1, + fc_retry_mask : 1, + fc_more_frag_mask : 1, + fc_from_ds_mask : 1, + fc_to_ds_mask : 1; + uint32_t sequence_number : 12, + fragment_number : 4, + sequence_control_source : 1, + mlo_ignore_addr3_override : 1, + mlo_addr_override : 1, + qc_15to8_setting : 8, + qc_amsdu_setting : 1, + qc_ack_policy_setting : 2, + qc_eosp_setting : 2; +#endif +}; + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_basics.h new file mode 100644 index 000000000000..6ced947af53d --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_basics.h @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, + partial_tx_data_tlv_count : 8, + tx_data_tlv_count : 16; +#else + uint32_t tx_data_tlv_count : 16, + partial_tx_data_tlv_count : 8, + available_memory : 8; +#endif +}; + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_status.h new file mode 100644 index 000000000000..ce665cbd92fd --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_buffer_status.h @@ -0,0 +1,74 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved : 15; +#endif +}; + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_user_buffer_status.h new file mode 100644 index 000000000000..21dfda17c7a7 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/txpcu_user_buffer_status.h @@ -0,0 +1,81 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, + reserved_1a : 1, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved_1a : 1, + stored_word_count_user : 14; +#endif +}; + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_su_mu_info.h new file mode 100644 index 000000000000..38974da9e612 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_su_mu_info.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 5, + validate_0b : 1, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + punctured_channel_information : 5, + validate_1b : 1, + mcs_of_eht_sig : 2, + num_eht_sig_symbols : 5, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + reserved_1d : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + validate_0b : 1, + disregard_0a : 5, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + reserved_1d : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + num_eht_sig_symbols : 5, + mcs_of_eht_sig : 2, + validate_1b : 1, + punctured_channel_information : 5, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_tb_info.h new file mode 100644 index 000000000000..e62ff3dd18aa --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/u_sig_eht_tb_info.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 6, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + spatial_reuse : 8, + disregard_1b : 5, + crc : 4, + tail : 6, + reserved_1c : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + disregard_0a : 6, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + reserved_1c : 5, + tail : 6, + crc : 4, + disregard_1b : 5, + spatial_reuse : 8, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/unallocated_ru_160_info.h new file mode 100644 index 000000000000..23b78179ff68 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/unallocated_ru_160_info.h @@ -0,0 +1,61 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, + subband80_0_cc1 : 8, + subband80_1_cc0 : 8, + subband80_1_cc1 : 8; +#else + uint32_t subband80_1_cc1 : 8, + subband80_1_cc0 : 8, + subband80_0_cc1 : 8, + subband80_0_cc0 : 8; +#endif +}; + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu160_info.h new file mode 100644 index 000000000000..408c0a65e1f2 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu160_info.h @@ -0,0 +1,257 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + reserved_2 : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; + uint32_t length_copy_d : 19, + mcs_copy_d : 4, + tail_copy_d : 6, + reserved_4 : 3; + uint32_t length_copy_e : 19, + mcs_copy_e : 4, + tail_copy_e : 6, + reserved_5 : 3; + uint32_t length_copy_f : 19, + mcs_copy_f : 4, + tail_copy_f : 6, + mu_user_number : 3; + uint32_t length_copy_g : 19, + mcs_copy_g : 4, + tail_copy_g : 6, + reserved_7 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t reserved_2 : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; + uint32_t reserved_4 : 3, + tail_copy_d : 6, + mcs_copy_d : 4, + length_copy_d : 19; + uint32_t reserved_5 : 3, + tail_copy_e : 6, + mcs_copy_e : 4, + length_copy_e : 19; + uint32_t mu_user_number : 3, + tail_copy_f : 6, + mcs_copy_f : 4, + length_copy_f : 19; + uint32_t reserved_7 : 3, + tail_copy_g : 6, + mcs_copy_g : 4, + length_copy_g : 19; +#endif +}; + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu20_info.h new file mode 100644 index 000000000000..0c45d622217c --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu20_info.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, + mcs : 4, + tail : 6, + mu_user_number : 3, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + mu_user_number : 3, + tail : 6, + mcs : 4, + length : 16; +#endif +}; + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu40_info.h new file mode 100644 index 000000000000..7692f5df62aa --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu40_info.h @@ -0,0 +1,96 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + mcs : 4, + tail : 6, + reserved_0 : 2, + mu_user_number : 3; + uint32_t length_copy : 17, + mcs_copy : 4, + tail_copy : 6, + reserved_1 : 5; +#else + uint32_t mu_user_number : 3, + reserved_0 : 2, + tail : 6, + mcs : 4, + length : 17; + uint32_t reserved_1 : 5, + tail_copy : 6, + mcs_copy : 4, + length_copy : 17; +#endif +}; + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu80_info.h new file mode 100644 index 000000000000..0e4d483d4a2e --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_mu80_info.h @@ -0,0 +1,145 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + mu_user_number : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t mu_user_number : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; +#endif +}; + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su160_info.h new file mode 100644 index 000000000000..73b0f1470374 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su160_info.h @@ -0,0 +1,313 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; + uint32_t length_copy_d : 21, + vhtb_reserved_copy_d : 2, + tail_copy_d : 6, + reserved_4 : 2, + rx_ndp_copy_d : 1; + uint32_t length_copy_e : 21, + vhtb_reserved_copy_e : 2, + tail_copy_e : 6, + reserved_5 : 2, + rx_ndp_copy_e : 1; + uint32_t length_copy_f : 21, + vhtb_reserved_copy_f : 2, + tail_copy_f : 6, + reserved_6 : 2, + rx_ndp_copy_f : 1; + uint32_t length_copy_g : 21, + vhtb_reserved_copy_g : 2, + tail_copy_g : 6, + reserved_7 : 2, + rx_ndp_copy_g : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; + uint32_t rx_ndp_copy_d : 1, + reserved_4 : 2, + tail_copy_d : 6, + vhtb_reserved_copy_d : 2, + length_copy_d : 21; + uint32_t rx_ndp_copy_e : 1, + reserved_5 : 2, + tail_copy_e : 6, + vhtb_reserved_copy_e : 2, + length_copy_e : 21; + uint32_t rx_ndp_copy_f : 1, + reserved_6 : 2, + tail_copy_f : 6, + vhtb_reserved_copy_f : 2, + length_copy_f : 21; + uint32_t rx_ndp_copy_g : 1, + reserved_7 : 2, + tail_copy_g : 6, + vhtb_reserved_copy_g : 2, + length_copy_g : 21; +#endif +}; + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su20_info.h new file mode 100644 index 000000000000..f76a9f0680b8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su20_info.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + vhtb_reserved : 3, + tail : 6, + reserved : 5, + rx_ndp : 1; +#else + uint32_t rx_ndp : 1, + reserved : 5, + tail : 6, + vhtb_reserved : 3, + length : 17; +#endif +}; + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su40_info.h new file mode 100644 index 000000000000..d3439bf6e8ba --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su40_info.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + vhtb_reserved : 2, + tail : 6, + reserved : 4, + rx_ndp : 1; + uint32_t length_copy : 19, + vhtb_reserved_copy : 2, + tail_copy : 6, + reserved_copy : 4, + rx_ndp_copy : 1; +#else + uint32_t rx_ndp : 1, + reserved : 4, + tail : 6, + vhtb_reserved : 2, + length : 19; + uint32_t rx_ndp_copy : 1, + reserved_copy : 4, + tail_copy : 6, + vhtb_reserved_copy : 2, + length_copy : 19; +#endif +}; + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su80_info.h new file mode 100644 index 000000000000..1cf37a4864b8 --- /dev/null +++ b/drivers/staging/fw-api/hw/kiwi/v2/vht_sig_b_su80_info.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; +#endif +}; + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h index 7c7ebed4f901..f594c525deed 100644 --- a/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h +++ b/drivers/staging/fw-api/hw/kiwi/v2/wcss_seq_hwioreg_umac.h @@ -1,6 +1,5 @@ - /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -236,6 +235,11 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x53c) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x540) #define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x544) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) #define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) #define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 diff --git a/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h index 98ae42071fb7..861a72aef747 100644 --- a/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h +++ b/drivers/staging/fw-api/hw/qcn9224/v1/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; uint32_t stat_buf_virt_addr_63_32 : 32; uint32_t ppdu_id : 32; diff --git a/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h b/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h index 98ae42071fb7..861a72aef747 100644 --- a/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h +++ b/drivers/staging/fw-api/hw/qcn9224/v2/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; uint32_t stat_buf_virt_addr_63_32 : 32; uint32_t ppdu_id : 32; diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/HALcomdef.h b/drivers/staging/fw-api/hw/wcn6450/v1/HALcomdef.h new file mode 100644 index 000000000000..9e8d68aea47e --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/HALcomdef.h @@ -0,0 +1,53 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/HALhwio.h b/drivers/staging/fw-api/hw/wcn6450/v1/HALhwio.h new file mode 100644 index 000000000000..b3b004df85ba --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/HALhwio.h @@ -0,0 +1,424 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OPT_OUTM2(hwiosym, mask1, mask2, val1, val2) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM3(hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM4(hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM5(hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM6(hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + reg = (reg & ~mask6) | (val6 & mask6); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUT2F(io, field1, field2, val1, val2) HWIO_OPT_OUTM2(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OPT_OUT3F(io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTM3(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OPT_OUT4F(io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTM4(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) +#define HWIO_OPT_OUT5F(io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTM5(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) ) +#define HWIO_OPT_OUT6F(io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTM6(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) ) + +#define HWIO_OPT_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM5(base, hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM6(base, hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + reg = (reg & ~mask6) | (val6 & mask6); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OPT_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OPT_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OPT_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) +#define HWIO_OPT_OUTX5F(base, io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTXM5(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) ) +#define HWIO_OPT_OUTX6F(base, io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTXM6(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) ) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#ifdef PLAT_MSL_REG_READ +#ifdef __cplusplus +extern "C" { +#endif +extern uint32 plat_register_read(uint32 addr); +#ifdef __cplusplus +} +#endif + +#define __inpdw(port) plat_register_read((uint32) (port)) +#else +#define __inpdw(port) (*((volatile uint32 *) (port))) +#endif +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/buffer_addr_info.h new file mode 100644 index 000000000000..1c8adb53220b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/buffer_addr_info.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 3, + sw_buffer_cookie : 21; +}; + +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/wcn6450/v1/ce_src_desc.h new file mode 100644 index 000000000000..6563dade5ec4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/ce_src_desc.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 4, + length : 16; + uint32_t fw_metadata : 16, + ce_res_1 : 16; + uint32_t ce_res_2 : 20, + ring_id : 8, + looping_count : 4; +}; + +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_1_GATHER_LSB 11 +#define CE_SRC_DESC_1_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_1_CE_RES_0_LSB 12 +#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000 + +#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_LENGTH_LSB 16 +#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_2_FW_METADATA_LSB 0 +#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008 +#define CE_SRC_DESC_2_CE_RES_1_LSB 16 +#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000 + +#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c +#define CE_SRC_DESC_3_CE_RES_2_LSB 0 +#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff + +#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_3_RING_ID_LSB 20 +#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/wcn6450/v1/ce_stat_desc.h new file mode 100644 index 000000000000..721480683df4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/ce_stat_desc.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_6 : 4, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +}; + +#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_5_LSB 0 +#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_0_GATHER_LSB 11 +#define CE_STAT_DESC_0_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_6_LSB 12 +#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000 + +#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_0_LENGTH_LSB 16 +#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_3_FW_METADATA_LSB 0 +#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_3_CE_RES_7_LSB 16 +#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_3_RING_ID_LSB 20 +#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/com_dtypes.h b/drivers/staging/fw-api/hw/wcn6450/v1/com_dtypes.h new file mode 100644 index 000000000000..83c89f335860 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/com_dtypes.h @@ -0,0 +1,182 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..85ffe9701396 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_dl_info.h @@ -0,0 +1,137 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity: 1, + crc : 4, + tail : 6, + reserved_1b : 6; +}; + +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..0e8230eee221 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_mu_ul_info.h @@ -0,0 +1,87 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 6; +}; + +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_su_info.h new file mode 100644 index 000000000000..72f6e8535441 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_a_su_info.h @@ -0,0 +1,162 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity: 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 4, + rx_ndp : 1; +}; + +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31 +#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..8a077e7fe7bd --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b1_mu_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { + uint32_t ru_allocation : 8, + reserved_0 : 24; +}; + +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..ca97877b50a3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_mu_info.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1 + +struct he_sig_b2_mu_info { + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 8, + nsts : 3; +}; + +#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000 + +#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29 +#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..6f6a8381e482 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/he_sig_b2_ofdma_info.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1 + +struct he_sig_b2_ofdma_info { + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 11; +}; + +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/ht_sig_info.h new file mode 100644 index 000000000000..2205a0c0818b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/ht_sig_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 8; +}; + +#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_0_MCS_LSB 0 +#define HT_SIG_INFO_0_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_0_CBW_LSB 7 +#define HT_SIG_INFO_0_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_0_LENGTH_LSB 8 +#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_0_RESERVED_0_LSB 24 +#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SMOOTHING_LSB 0 +#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_1_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_1_AGGREGATION_LSB 3 +#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_STBC_LSB 4 +#define HT_SIG_INFO_1_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_FEC_CODING_LSB 6 +#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SHORT_GI_LSB 7 +#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_CRC_LSB 10 +#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_1_RESERVED_1_LSB 24 +#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/hwio.h b/drivers/staging/fw-api/hw/wcn6450/v1/hwio.h new file mode 100644 index 000000000000..f2498dd31705 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/hwio.h @@ -0,0 +1,1322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __HWIO_H__ +#define __HWIO_H__ + +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00000000) +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_USED 0x8c + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_RMSK 0x3ff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x14) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x18) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_RMSK 0x1ffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_SHFT 24 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_BMSK 0x800000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_SHFT 23 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_BMSK 0x400000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_SHFT 22 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_BMSK 0x200000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_SHFT 21 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_BMSK 0x100000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_SHFT 20 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_SHFT 19 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x1c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x20) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x24) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x28) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x2c) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x30) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x34) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x38) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x3c) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x40) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x44) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x48) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4c) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x50) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x54) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_RMSK 0x7 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x58) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x5c) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x60) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x64) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x68) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_RMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x6c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x70) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x74) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x78) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x7c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x80) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x84) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x88) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8c) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_SHFT 0 + +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00001000) +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_USED 0x8c + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_RMSK 0x3ff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x14) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x18) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_RMSK 0x1ffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_SHFT 24 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_BMSK 0x800000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_SHFT 23 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_BMSK 0x400000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_SHFT 22 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_BMSK 0x200000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_SHFT 21 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_BMSK 0x100000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_SHFT 20 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_SHFT 19 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x1c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x20) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x24) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x28) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x2c) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x30) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x34) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x38) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x3c) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x40) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x44) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x48) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4c) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x50) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x54) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_RMSK 0x7 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x58) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x5c) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x60) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x64) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x68) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_RMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x6c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x70) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x74) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x78) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x7c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x80) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x84) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x88) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8c) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_SHFT 0 + +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00010000) +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_USED 0x10 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_RMSK 0xfff000 +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK 0xfff000 +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT 12 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_SHFT 0 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_a_info.h new file mode 100644 index 000000000000..c55cb46730d3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_a_info.h @@ -0,0 +1,72 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 3; +}; + +#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RATE_LSB 0 +#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LENGTH_LSB 5 +#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PARITY_LSB 17 +#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_TAIL_LSB 18 +#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RESERVED_LSB 29 +#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_b_info.h new file mode 100644 index 000000000000..13d842077556 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/l_sig_b_info.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { + uint32_t rate : 4, + length : 12, + reserved : 16; +}; + +#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RATE_LSB 0 +#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_LENGTH_LSB 4 +#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RESERVED_LSB 16 +#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/macrx_abort_request_info.h new file mode 100644 index 000000000000..d9b718575707 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/macrx_abort_request_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +}; + +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/wcn6450/v1/msmhwiobase.h new file mode 100644 index 000000000000..55619985a835 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/msmhwiobase.h @@ -0,0 +1,27 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define HOST_SOC_WFSS_CE_REG_TOP_BASE 0x1b80000 +#define HOST_SOC_WFSS_CE_REG_TOP_BASE_SIZE 0x0001c000 +#define HOST_SOC_WFSS_CE_REG_TOP_BASE_PHYS 0x01b80000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_abort_request_info.h new file mode 100644 index 000000000000..bf0cad1fbfed --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_abort_request_info.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + reserved_0 : 6, + receive_duration : 16; +}; + +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00 + +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_common_user_info.h new file mode 100644 index 000000000000..ca0e568d6184 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_common_user_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 1 + +struct phyrx_common_user_info { + uint32_t receive_duration : 16, + reserved_0a : 16; +}; + +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_MASK 0x0000ffff + +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..e41b29af5faf --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,119 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +}; + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..98bae636ad88 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,79 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +}; + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..97ec7273f978 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_a_su.h @@ -0,0 +1,139 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +}; + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..6b4c32f30ba1 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h @@ -0,0 +1,43 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +}; + +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..c641efc8054b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1 + +struct phyrx_he_sig_b2_mu { + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +}; + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..08b9f511fc98 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + +struct phyrx_he_sig_b2_ofdma { + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +}; + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_ht_sig.h new file mode 100644 index 000000000000..2677b0bdc309 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_ht_sig.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" + +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { + struct ht_sig_info phyrx_ht_sig_info_details; +}; + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_a.h new file mode 100644 index 000000000000..568c80c44c49 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_a.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" + +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { + struct l_sig_a_info phyrx_l_sig_a_info_details; +}; + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_b.h new file mode 100644 index 000000000000..37e0e4bc857a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_l_sig_b.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" + +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { + struct l_sig_b_info phyrx_l_sig_b_info_details; +}; + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..54a54ddccb3a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end.h new file mode 100644 index 000000000000..1a86068be10c --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end.h @@ -0,0 +1,503 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" + +#define NUM_OF_DWORDS_PHYRX_PKT_END 33 + +struct phyrx_pkt_end { + struct phyrx_pkt_end_info rx_pkt_end_details; +}; + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000 + +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..d71467a50c1e --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_pkt_end_info.h @@ -0,0 +1,524 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#include "rx_timing_offset_info.h" +#include "receive_rssi_info.h" + +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 + +struct phyrx_pkt_end_info { + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + rx_frame_correction_needed : 1, + frameless_frame_received : 1, + reserved_0a : 6, + dl_ofdma_info_valid : 1, + dl_ofdma_ru_start_index : 7, + dl_ofdma_ru_width : 7, + reserved_0b : 5; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_location_info rx_location_info_details; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +}; + +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 + +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..f9732e34b669 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_rssi_legacy.h @@ -0,0 +1,628 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" + +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37 + +struct phyrx_rssi_legacy { + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + reserved_0 : 1, + receive_bandwidth : 2, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +}; + +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020 + +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_user_info.h new file mode 100644 index 000000000000..2724759cf5be --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_user_info.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +#define NUM_OF_DWORDS_PHYRX_USER_INFO 3 + +struct phyrx_user_info { + struct receive_user_info receive_user_info_details; +}; + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..b9490245dbde --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/phyrx_vht_sig_a.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" + +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +}; + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/receive_rssi_info.h new file mode 100644 index 000000000000..3d3133b6f160 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/receive_rssi_info.h @@ -0,0 +1,352 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_pri20_chain4 : 8, + rssi_ext20_chain4 : 8, + rssi_ext40_low20_chain4 : 8, + rssi_ext40_high20_chain4 : 8; + uint32_t rssi_ext80_low20_chain4 : 8, + rssi_ext80_low_high20_chain4 : 8, + rssi_ext80_high_low20_chain4 : 8, + rssi_ext80_high20_chain4 : 8; + uint32_t rssi_pri20_chain5 : 8, + rssi_ext20_chain5 : 8, + rssi_ext40_low20_chain5 : 8, + rssi_ext40_high20_chain5 : 8; + uint32_t rssi_ext80_low20_chain5 : 8, + rssi_ext80_low_high20_chain5 : 8, + rssi_ext80_high_low20_chain5 : 8, + rssi_ext80_high20_chain5 : 8; + uint32_t rssi_pri20_chain6 : 8, + rssi_ext20_chain6 : 8, + rssi_ext40_low20_chain6 : 8, + rssi_ext40_high20_chain6 : 8; + uint32_t rssi_ext80_low20_chain6 : 8, + rssi_ext80_low_high20_chain6 : 8, + rssi_ext80_high_low20_chain6 : 8, + rssi_ext80_high20_chain6 : 8; + uint32_t rssi_pri20_chain7 : 8, + rssi_ext20_chain7 : 8, + rssi_ext40_low20_chain7 : 8, + rssi_ext40_high20_chain7 : 8; + uint32_t rssi_ext80_low20_chain7 : 8, + rssi_ext80_low_high20_chain7 : 8, + rssi_ext80_high_low20_chain7 : 8, + rssi_ext80_high20_chain7 : 8; +}; + +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/receive_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/receive_user_info.h new file mode 100644 index 000000000000..9b2eb60e1410 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/receive_user_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3 + +struct receive_user_info { + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + receive_bandwidth : 2, + mimo_ss_bitmap : 8, + ofdma_ru_allocation : 8, + ofdma_user_index : 7, + ofdma_content_channel : 1; + uint32_t ldpc : 1, + ru_width : 7, + reserved_2a : 24; +}; + +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_STBC_LSB 28 +#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_SGI_LSB 4 +#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_LDPC_LSB 0 +#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001 + +#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1 +#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe + +#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8 +#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..27f7972cc4eb --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,200 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 + +struct reo_descriptor_threshold_reached_status { + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_destination_ring.h new file mode 100644 index 000000000000..361b405f3342 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_destination_ring.h @@ -0,0 +1,301 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_msdu_desc_info.h" + +#define NUM_OF_DWORDS_REO_DESTINATION_RING 16 + +struct reo_destination_ring { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + receive_queue_number : 16; + uint32_t soft_reorder_info_valid : 1, + reorder_opcode : 4, + reorder_slot_index : 8, + mpdu_fragment_number : 4, + captured_msdu_data_size : 4, + sw_exception : 1, + reserved_8a : 10; + uint32_t reo_destination_struct_signature: 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15 : 20, + ring_id : 8, + looping_count : 4; +}; + +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 + +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 + +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 + +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 + +#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e + +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 + +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 + +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 + +#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 + +#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 +#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 + +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff + +#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 +#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff + +#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 +#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff + +#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 +#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff + +#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 +#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff + +#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 +#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff + +#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 +#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff + +#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RING_ID_LSB 20 +#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_entrance_ring.h new file mode 100644 index 000000000000..65bf3e407d76 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_entrance_ring.h @@ -0,0 +1,201 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" + +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid: 1, + sw_exception_destination_ring : 5, + reserved_6a : 13; + uint32_t phy_ppdu_id : 16, + reserved_7a : 4, + ring_id : 8, + looping_count : 4; +}; + +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 +#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 + +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16 +#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000 + +#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache.h new file mode 100644 index 000000000000..56304c89d5ad --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache.h @@ -0,0 +1,122 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + reserved_2b : 17; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 +#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 + +#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache_status.h new file mode 100644 index 000000000000..2030075c6cb9 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_cache_status.h @@ -0,0 +1,215 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25 + +struct reo_flush_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit: 1, + cache_controller_flush_status_desc_type: 3, + cache_controller_flush_status_client_id: 4, + cache_controller_flush_status_error: 2, + cache_controller_flush_count : 8, + reserved_2b : 6; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000 + +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue.h new file mode 100644 index 000000000000..9dbfc74a6ae5 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush: 1, + block_resource_index : 2, + invalidate_queue_and_flush : 1, + reserved_2a : 20; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800 + +#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000 + +#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue_status.h new file mode 100644 index 000000000000..612b138c3901 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_queue_status.h @@ -0,0 +1,180 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25 + +struct reo_flush_queue_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe + +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list.h new file mode 100644 index 000000000000..87acea7b1260 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003 + +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..edea895c2178 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_flush_timeout_list_status.h @@ -0,0 +1,190 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25 + +struct reo_flush_timeout_list_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats.h new file mode 100644 index 000000000000..cda805b47545 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 + +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 + +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..02f1e74010fa --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_get_queue_stats_status.h @@ -0,0 +1,220 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25 + +struct reo_get_queue_stats_status { + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 8, + reserved_2 : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t reserved_18 : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000 + +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000 + +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f + +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0 + +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache.h new file mode 100644 index 000000000000..bff80e52bae2 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8 + +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache_status.h new file mode 100644 index 000000000000..cd59f3a521f4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_unblock_cache_status.h @@ -0,0 +1,185 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25 + +struct reo_unblock_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002 + +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..86f8b3566477 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue.h @@ -0,0 +1,317 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter: 1, + update_disable_duplicate_detection: 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag: 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter: 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 8, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 5; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +}; + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000 + +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300 + +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800 + +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000 + +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..35afee0f3819 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25 + +struct reo_update_rx_reo_queue_status { + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_attention.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_attention.h new file mode 100644 index 000000000000..28f64d6d67b3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_attention.h @@ -0,0 +1,282 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; +}; + +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_0_RESERVED_0_LSB 9 +#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_1_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 + +#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1A_LSB 1 +#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 + +#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_1_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 + +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_1_POWER_MGMT_LSB 5 +#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 + +#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_1_NON_QOS_LSB 6 +#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 + +#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_NULL_DATA_LSB 7 +#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 + +#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 + +#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 + +#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_MORE_DATA_LSB 10 +#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 + +#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_1_EOSP_LSB 11 +#define RX_ATTENTION_1_EOSP_MASK 0x00000800 + +#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 + +#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_1_ORDER_LSB 14 +#define RX_ATTENTION_1_ORDER_MASK 0x00004000 + +#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_1_CCE_MATCH_LSB 15 +#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 + +#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1B_LSB 22 +#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 + +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_1_DIRECTED_LSB 25 +#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 + +#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 + +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_FCS_ERR_LSB 31 +#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 + +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 + +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 + +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 + +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 + +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 + +#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 + +#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 + +#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 + +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_2_RESERVED_2_LSB 14 +#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 + +#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_DONE_LSB 31 +#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_flow_search_entry.h new file mode 100644 index 000000000000..fea3afad657e --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_flow_search_entry.h @@ -0,0 +1,157 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 15, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_l4_checksum : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +}; + +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00 + +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_location_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_location_info.h new file mode 100644 index 000000000000..49a98519e032 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_location_info.h @@ -0,0 +1,207 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 9 + +struct rx_location_info { + uint32_t rtt_fac_legacy : 16, + rtt_fac_legacy_ext80 : 16; + uint32_t rtt_fac_vht : 16, + rtt_fac_vht_ext80 : 16; + uint32_t rtt_fac_legacy_status : 1, + rtt_fac_legacy_ext80_status : 1, + rtt_fac_vht_status : 1, + rtt_fac_vht_ext80_status : 1, + rtt_fac_sifs : 12, + rtt_fac_sifs_status : 2, + rtt_cfr_status : 1, + rtt_cir_status : 1, + rtt_channel_dump_size : 11, + rtt_hw_ifft_mode : 1; + uint32_t rtt_btcf_status : 1, + rtt_preamble_type : 5, + rtt_pkt_bw_leg : 2, + rtt_pkt_bw_vht : 2, + rtt_gi_type : 2, + rtt_mcs_rate : 5, + rtt_strongest_chain : 3, + rtt_strongest_chain_ext80 : 3, + rtt_rx_chain_mask : 8, + reserved_3 : 1; + uint32_t rx_start_ts : 32; + uint32_t rx_end_ts : 32; + uint32_t sfo_phase_pkt_start : 12, + sfo_phase_pkt_end : 12, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_cfo_measurement : 14, + rtt_chan_spread : 8, + rtt_timing_backoff_sel : 2, + reserved_8 : 7, + rx_location_info_valid : 1; +}; + +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB 0 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB 16 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB 0 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB 16 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB 0 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB 2 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB 4 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB 16 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB 18 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK 0x00040000 + +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB 19 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK 0x00080000 + +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB 31 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB 0 +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK 0x00000001 + +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB 1 +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB 6 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB 8 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB 10 +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK 0x00000c00 + +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB 12 +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK 0x0001f000 + +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB 17 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB 23 +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RESERVED_3_LSB 31 +#define RX_LOCATION_INFO_3_RESERVED_3_MASK 0x80000000 + +#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET 0x00000010 +#define RX_LOCATION_INFO_4_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_4_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_5_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_5_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB 0 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB 12 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000001c +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB 14 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RESERVED_8_LSB 24 +#define RX_LOCATION_INFO_8_RESERVED_8_MASK 0x7f000000 + +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB 31 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..3bca315ebb62 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_desc_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { + uint32_t msdu_count : 8, + mpdu_sequence_number : 12, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + sa_is_valid : 1, + sa_idx_timeout : 1, + da_is_valid : 1, + da_is_mcbc : 1, + da_idx_timeout : 1, + raw_mpdu : 1, + more_fragment_flag : 1; + uint32_t peer_meta_data : 32; +}; + +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000 + +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000 + +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000 + +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000 + +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000 + +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000 + +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_details.h new file mode 100644 index 000000000000..36216b3f25e9 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_details.h @@ -0,0 +1,113 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +}; + +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_end.h new file mode 100644 index 000000000000..8a22fcba1e6f --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_end.h @@ -0,0 +1,132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 2, + rxdma1_destination_ring : 2, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 3; +}; + +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_0_RESERVED_0_LSB 9 +#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1A_LSB 0 +#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff + +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 + +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 + +#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 + +#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 + +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_FCS_ERR_LSB 19 +#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 + +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 + +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 + +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 + +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 + +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 + +#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1B_LSB 29 +#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_info.h new file mode 100644 index 000000000000..c95fde7332c4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_info.h @@ -0,0 +1,537 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_INFO 23 + +struct rx_mpdu_info { + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t peer_meta_data : 32; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + reserved_9a : 2, + phy_ppdu_id : 16; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; +}; + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_PN_31_0_LSB 0 +#define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_4_PN_63_32_LSB 0 +#define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_5_PN_95_64_LSB 0 +#define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_6_PN_127_96_LSB 0 +#define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_EPD_EN_LSB 0 +#define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_TID_LSB 15 +#define RX_MPDU_INFO_7_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 +#define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 + +#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FR_DS_LSB 16 +#define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_TO_DS_LSB 17 +#define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NON_QOS_LSB 19 +#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_EOSP_LSB 24 +#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ORDER_LSB 26 +#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_DIRECTED_LSB 29 +#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..2abf815d92a0 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { + struct buffer_addr_info mpdu_link_desc_addr_info; +}; + +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_start.h new file mode 100644 index 000000000000..6ba62e26d355 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_mpdu_start.h @@ -0,0 +1,443 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_START 23 + +struct rx_mpdu_start { + struct rx_mpdu_info rx_mpdu_info_details; +}; + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_desc_info.h new file mode 100644 index 000000000000..085d111db807 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_desc_info.h @@ -0,0 +1,127 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 + +struct rx_msdu_desc_info { + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + reo_destination_indication : 5, + msdu_drop : 1, + sa_is_valid : 1, + sa_idx_timeout : 1, + da_is_valid : 1, + da_is_mcbc : 1, + da_idx_timeout : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + raw_mpdu : 1; + uint32_t sa_idx_or_sw_peer_id_14_0 : 15, + mpdu_ast_idx_or_sw_peer_id_14_0 : 15, + fr_ds : 1, + to_ds : 1; +}; + +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31 +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30 +#define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000 + +#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31 +#define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_details.h new file mode 100644 index 000000000000..70f0aa00145b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_details.h @@ -0,0 +1,129 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_msdu_desc_info.h" + +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; +}; + +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_end.h new file mode 100644 index 000000000000..03f1714d66ef --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_end.h @@ -0,0 +1,322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 17 + +struct rx_msdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t key_id_octet : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t rule_indication_63_32 : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t ipv6_options_crc : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t tcp_udp_chksum : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + reserved_12a : 6; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + sa_sw_peer_id : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + reserved_15a : 22; + uint32_t cumulative_l4_checksum : 16, + cumulative_ip_length : 16; +}; + +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_0_RESERVED_0_LSB 9 +#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +#define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_1_RESERVED_1A_LSB 30 +#define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 + +#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 +#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 + +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff + +#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff + +#define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_LSB 0 +#define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f + +#define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_LSB 6 +#define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 + +#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 + +#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 + +#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_5_RESERVED_5A_LSB 14 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 + +#define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_5_L3_TYPE_LSB 16 +#define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 + +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff + +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_9_TCP_FLAG_LSB 0 +#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff + +#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 + +#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_9_RESERVED_9A_LSB 10 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 + +#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 + +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 + +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 + +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 + +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 + +#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 + +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 + +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 + +#define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 + +#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 + +#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 + +#define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 + +#define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_LAST_MSDU_LSB 29 +#define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 + +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 + +#define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_11_SA_IDX_LSB 0 +#define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff + +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_12_MSDU_DROP_LSB 0 +#define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 + +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e + +#define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_12_FLOW_IDX_LSB 6 +#define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 + +#define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 +#define RX_MSDU_END_12_RESERVED_12A_LSB 26 +#define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 + +#define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_13_FSE_METADATA_LSB 0 +#define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff + +#define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_14_CCE_METADATA_LSB 0 +#define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff + +#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 +#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff + +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 + +#define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c +#define RX_MSDU_END_15_RESERVED_15A_LSB 10 +#define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 + +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_link.h new file mode 100644 index 000000000000..f068d4b9c4b7 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_link.h @@ -0,0 +1,659 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" + +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +}; + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_4_PN_31_0_LSB 0 +#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_5_PN_63_32_LSB 0 +#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_6_PN_95_64_LSB 0 +#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_7_PN_127_96_LSB 0 +#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_start.h new file mode 100644 index 000000000000..44aec3298482 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_msdu_start.h @@ -0,0 +1,232 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 9 + +struct rx_msdu_start { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + reserved_1a : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + stbc : 1, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 2, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +}; + +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_0_RESERVED_0_LSB 9 +#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_START_1_RESERVED_1A_LSB 14 +#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 + +#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L3_OFFSET_LSB 16 +#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_AH_LSB 23 +#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L4_OFFSET_LSB 24 +#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_PROTO_LSB 12 +#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_UDP_PROTO_LSB 13 +#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FRAG_LSB 14 +#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_START_2_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_2_LDPC_LSB 23 +#define RX_MSDU_START_2_LDPC_MASK 0x00800000 + +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_5_USER_RSSI_LSB 0 +#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_PKT_TYPE_LSB 8 +#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_START_5_STBC_OFFSET 0x00000014 +#define RX_MSDU_START_5_STBC_LSB 12 +#define RX_MSDU_START_5_STBC_MASK 0x00001000 + +#define RX_MSDU_START_5_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_5_SGI_LSB 13 +#define RX_MSDU_START_5_SGI_MASK 0x00006000 + +#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_5_RATE_MCS_LSB 15 +#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000 + +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000 + +#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK 0xff000000 + +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c +#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_8_VLAN_STAG_CI_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..f7b1ed909346 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats.h @@ -0,0 +1,406 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23 + +struct rx_ppdu_end_user_stats { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + ofdma_info_valid : 1, + dl_ofdma_ru_start_index : 7, + reserved_1a : 4; + uint32_t dl_ofdma_ru_width : 7, + reserved_2a : 1, + user_receive_quality : 8, + mpdu_cnt_fcs_err : 10, + wbm2rxdma_buf_source_used : 1, + fw2rxdma_buf_source_used : 1, + sw2rxdma_buf_source_used : 1, + reserved_2b : 3; + uint32_t mpdu_cnt_fcs_ok : 9, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid: 1, + ht_control_info_null_valid : 1, + reserved_3a : 2, + rxdma2reo_ring_used : 1, + rxdma2fw_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + reserved_3b : 8; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap: 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + reserved_20a : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; +}; + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff + +#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000 + +#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000 + +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000 + +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000 + +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f + +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000 + +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000 + +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000 + +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000 + +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000 + +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff + +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9 +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200 + +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10 +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800 + +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000 + +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..15a74c95ee51 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,101 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7 + +struct rx_ppdu_end_user_stats_ext { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; +}; + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start.h new file mode 100644 index 000000000000..3873d3b56e31 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 3 + +struct rx_ppdu_start { + uint32_t phy_ppdu_id : 16, + reserved_15 : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp : 32; +}; + +#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000 +#define RX_PPDU_START_0_RESERVED_15_LSB 16 +#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000 + +#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..149db67cf91b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_ppdu_start_user_info.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3 + +struct rx_ppdu_start_user_info { + struct receive_user_info receive_user_info_details; +}; + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue.h new file mode 100644 index 000000000000..1d9d6935a5c1 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue.h @@ -0,0 +1,362 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" + +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter: 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 8, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 6; + uint32_t svld : 1, + ssn : 12, + current_index : 8, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 8, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0: 32; + uint32_t ptr_to_previous_aging_queue_39_32: 8, + reserved_13a : 24; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t reserved_23 : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +}; + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_VLD_LSB 0 +#define RX_REO_QUEUE_2_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_AC_LSB 5 +#define RX_REO_QUEUE_2_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BAR_LSB 7 +#define RX_REO_QUEUE_2_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RTY_LSB 8 +#define RX_REO_QUEUE_2_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 + +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 + +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SIZE_LSB 23 +#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 + +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 + +#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 +#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 + +#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SVLD_LSB 0 +#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SSN_LSB 1 +#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 + +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 + +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 + +#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 +#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 + +#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_VALID_LSB 31 +#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_4_PN_31_0_LSB 0 +#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_5_PN_63_32_LSB 0 +#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_6_PN_95_64_LSB 0 +#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_7_PN_127_96_LSB 0 +#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 +#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 + +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_RESERVED_23_LSB 0 +#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f + +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_29_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_30_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_31_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue_ext.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue_ext.h new file mode 100644 index 000000000000..fe0a9b7cf150 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_reo_queue_ext.h @@ -0,0 +1,308 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "rx_mpdu_link_ptr.h" + +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +}; + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..8e8ffad90e79 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_rxpcu_classification_overview.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + reserved_0 : 9, + phy_ppdu_id : 16; +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rx_timing_offset_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rx_timing_offset_info.h new file mode 100644 index 000000000000..14e630e9637b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rx_timing_offset_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + +struct rx_timing_offset_info { + uint32_t residual_phase_offset : 12, + reserved : 20; +}; + +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..2db684821b4d --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rxpcu_ppdu_end_info.h @@ -0,0 +1,278 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 + +struct rxpcu_ppdu_end_info { + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + reserved_3 : 2; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details: 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details: 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t rx_ppdu_end_marker : 32; +}; + +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 + +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 + +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 + +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/rxpt_classify_info.h new file mode 100644 index 000000000000..8f2d34d9e13a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/rxpt_classify_info.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 2, + rxdma0_destination_ring_selection: 2, + reserved_0b : 17; +}; + +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/seq_hwio.h b/drivers/staging/fw-api/hw/wcn6450/v1/seq_hwio.h new file mode 100644 index 000000000000..6da319320aa4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/seq_hwio.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tcl_data_cmd.h b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_data_cmd.h new file mode 100644 index 000000000000..bc7a04c6cd52 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_data_cmd.h @@ -0,0 +1,231 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_TCL_DATA_CMD 7 + +struct tcl_data_cmd { + struct buffer_addr_info buf_addr_info; + uint32_t buf_or_ext_desc_type : 1, + epd : 1, + encap_type : 2, + encrypt_type : 4, + src_buffer_swap : 1, + link_meta_swap : 1, + tqm_no_drop : 1, + reserved_2a : 1, + search_type : 2, + addrx_en : 1, + addry_en : 1, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_3a : 1, + packet_offset : 9; + uint32_t buffer_timestamp : 19, + buffer_timestamp_valid : 1, + reserved_4a : 1, + hlos_tid_overwrite : 1, + hlos_tid : 4, + lmac_id : 2, + udp_flow_override : 2, + reserved_4b : 2; + uint32_t dscp_tid_table_num : 6, + search_index : 20, + cache_set_num : 4, + mesh_enable : 2; + uint32_t reserved_6a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_EPD_LSB 1 +#define TCL_DATA_CMD_2_EPD_MASK 0x00000002 + +#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 +#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c + +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 + +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 + +#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 +#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 + +#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10 +#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400 + +#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_RESERVED_2A_LSB 11 +#define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800 + +#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12 +#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000 + +#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 +#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 + +#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 +#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 + +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TO_FW_LSB 21 +#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_RESERVED_3A_LSB 22 +#define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000 + +#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff + +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 + +#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4A_LSB 20 +#define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000 + +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 + +#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_LSB 22 +#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 + +#define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_LMAC_ID_LSB 26 +#define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000 + +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB 28 +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK 0x30000000 + +#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4B_LSB 30 +#define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xc0000000 + +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f + +#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6 +#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0 + +#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000 + +#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30 +#define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000 + +#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 +#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff + +#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RING_ID_LSB 20 +#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tcl_gse_cmd.h b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_gse_cmd.h new file mode 100644 index 000000000000..21edac8b3ed0 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_gse_cmd.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 7 + +struct tcl_gse_cmd { + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_SWAP_LSB 14 +#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 +#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff + +#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff + +#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RING_ID_LSB 20 +#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_status_ring.h new file mode 100644 index 000000000000..29a3520b6388 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tcl_status_ring.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RING_ID_LSB 20 +#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_hdr.h new file mode 100644 index 000000000000..2129cb642f08 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_hdr.h @@ -0,0 +1,123 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_HDR_H_ + +#define _TLV_HDR_H_ + +#if !defined(__ASSEMBLER__) + +#endif + +struct tlv_usr_16_hdr { + + volatile uint16_t tlv_cflg_reserved : 1, + + tlv_tag : 5, + + tlv_len : 4, + + tlv_usrid : 6; + +}; + +struct tlv_16_hdr { + + volatile uint16_t tlv_cflg_reserved : 1, + + tlv_tag : 5, + + tlv_len : 4, + + tlv_reserved : 6; + +}; + +struct tlv_usr_32_hdr { + + volatile uint32_t tlv_cflg_reserved : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_usrid : 6; + +}; + +struct tlv_32_hdr { + + volatile uint32_t tlv_cflg_reserved : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_reserved : 6; + +}; + +struct tlv_usr_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_usrid : 6, + + tlv_reserved : 10, + + pad_42to64_bit : 22; + +}; + +struct tlv_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_reserved : 16, + + pad_42to64_bit : 22; + +}; + +struct tlv_usr_c_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_ctag : 3, + + tlv_usrid : 6, + + tlv_cdata : 32, + + pad_42to64_bit : 22; + +}; + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_tag_def.h new file mode 100644 index 000000000000..817873f23860 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tlv_tag_def.h @@ -0,0 +1,528 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum { + + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIMACRX_CBF_READ_REQUEST_E = 8 , + WIFIMACRX_CBF_DATA_REQUEST_E = 9 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 , + WIFIMACRX_NDP_TIMEOUT_E = 12 , + WIFIMACRX_ABORT_ACK_E = 13 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 14 , + WIFIMACRX_CHAIN_MASK_E = 15 , + WIFIMACRX_NAP_USER_E = 16 , + WIFIMACRX_ABORT_REQUEST_E = 17 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 , + WIFIPHYTX_ABORT_ACK_E = 19 , + WIFIPHYTX_ABORT_REQUEST_E = 20 , + WIFIPHYTX_PKT_END_E = 21 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 , + WIFIPHYTX_DATA_REQUEST_E = 24 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 , + WIFIPHYTX_NAP_ACK_E = 26 , + WIFIPHYTX_NAP_DONE_E = 27 , + WIFIPHYTX_OFF_ACK_E = 28 , + WIFIPHYTX_ON_ACK_E = 29 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 30 , + WIFIPHYTX_DEBUG16_E = 31 , + WIFIMACTX_ABORT_REQUEST_E = 32 , + WIFIMACTX_ABORT_ACK_E = 33 , + WIFIMACTX_PKT_END_E = 34 , + WIFIMACTX_PRE_PHY_DESC_E = 35 , + WIFIMACTX_BF_PARAMS_COMMON_E = 36 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 37 , + WIFIMACTX_PREFETCH_CV_E = 38 , + WIFIMACTX_USER_DESC_COMMON_E = 39 , + WIFIMACTX_USER_DESC_PER_USER_E = 40 , + WIFIEXAMPLE_USER_TLV_16_E = 41 , + WIFIEXAMPLE_TLV_16_E = 42 , + WIFIMACTX_PHY_OFF_E = 43 , + WIFIMACTX_PHY_ON_E = 44 , + WIFIMACTX_SYNTH_OFF_E = 45 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 46 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 , + WIFIMACTX_PHY_DESC_E = 48 , + WIFIMACTX_L_SIG_A_E = 49 , + WIFIMACTX_L_SIG_B_E = 50 , + WIFIMACTX_HT_SIG_E = 51 , + WIFIMACTX_VHT_SIG_A_E = 52 , + WIFIMACTX_VHT_SIG_B_SU20_E = 53 , + WIFIMACTX_VHT_SIG_B_SU40_E = 54 , + WIFIMACTX_VHT_SIG_B_SU80_E = 55 , + WIFIMACTX_VHT_SIG_B_SU160_E = 56 , + WIFIMACTX_VHT_SIG_B_MU20_E = 57 , + WIFIMACTX_VHT_SIG_B_MU40_E = 58 , + WIFIMACTX_VHT_SIG_B_MU80_E = 59 , + WIFIMACTX_VHT_SIG_B_MU160_E = 60 , + WIFIMACTX_SERVICE_E = 61 , + WIFIMACTX_HE_SIG_A_SU_E = 62 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 63 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 64 , + WIFIMACTX_HE_SIG_B1_MU_E = 65 , + WIFIMACTX_HE_SIG_B2_MU_E = 66 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 , + WIFIMACTX_DELETE_CV_E = 68 , + WIFIMACTX_MU_UPLINK_COMMON_E = 69 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 , + WIFIMACTX_PHY_NAP_E = 72 , + WIFIMACTX_DEBUG_E = 73 , + WIFIPHYRX_ABORT_ACK_E = 74 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 , + WIFIPHYRX_RSSI_LEGACY_E = 76 , + WIFIPHYRX_RSSI_HT_E = 77 , + WIFIPHYRX_USER_INFO_E = 78 , + WIFIPHYRX_PKT_END_E = 79 , + WIFIPHYRX_DEBUG_E = 80 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 , + WIFIPHYRX_L_SIG_A_E = 83 , + WIFIPHYRX_L_SIG_B_E = 84 , + WIFIPHYRX_HT_SIG_E = 85 , + WIFIPHYRX_VHT_SIG_A_E = 86 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 87 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 88 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 89 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 90 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 91 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 92 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 93 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 94 , + WIFIPHYRX_HE_SIG_A_SU_E = 95 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 , + WIFIPHYRX_HE_SIG_B1_MU_E = 98 , + WIFIPHYRX_HE_SIG_B2_MU_E = 99 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 , + WIFIPHYRX_COMMON_USER_INFO_E = 102 , + WIFIPHYRX_DATA_DONE_E = 103 , + WIFIRECEIVE_RSSI_INFO_E = 104 , + WIFIRECEIVE_USER_INFO_E = 105 , + WIFIMIMO_CONTROL_INFO_E = 106 , + WIFIRX_LOCATION_INFO_E = 107 , + WIFICOEX_TX_REQ_E = 108 , + WIFIDUMMY_E = 109 , + WIFIRX_TIMING_OFFSET_INFO_E = 110 , + WIFIEXAMPLE_TLV_32_NAME_E = 111 , + WIFIMPDU_LIMIT_E = 112 , + WIFINA_LENGTH_END_E = 113 , + WIFIOLE_BUF_STATUS_E = 114 , + WIFIPCU_PPDU_SETUP_DONE_E = 115 , + WIFIPCU_PPDU_SETUP_END_E = 116 , + WIFIPCU_PPDU_SETUP_INIT_E = 117 , + WIFIPCU_PPDU_SETUP_START_E = 118 , + WIFIPDG_FES_SETUP_E = 119 , + WIFIPDG_RESPONSE_E = 120 , + WIFIPDG_TX_REQ_E = 121 , + WIFISCH_WAIT_INSTR_E = 122 , + WIFISCHEDULER_TLV_E = 123 , + WIFITQM_FLOW_EMPTY_STATUS_E = 124 , + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 , + WIFITQM_GEN_MPDUS_E = 128 , + WIFITQM_GEN_MPDUS_STATUS_E = 129 , + WIFITQM_REMOVE_MPDU_E = 130 , + WIFITQM_REMOVE_MPDU_STATUS_E = 131 , + WIFITQM_REMOVE_MSDU_E = 132 , + WIFITQM_REMOVE_MSDU_STATUS_E = 133 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 , + WIFITQM_WRITE_CMD_E = 135 , + WIFIOFDMA_TRIGGER_DETAILS_E = 136 , + WIFITX_DATA_E = 137 , + WIFITX_FES_SETUP_E = 138 , + WIFIRX_PACKET_E = 139 , + WIFIEXPECTED_RESPONSE_E = 140 , + WIFITX_MPDU_END_E = 141 , + WIFITX_MPDU_START_E = 142 , + WIFITX_MSDU_END_E = 143 , + WIFITX_MSDU_START_E = 144 , + WIFITX_SW_MODE_SETUP_E = 145 , + WIFITXPCU_BUFFER_STATUS_E = 146 , + WIFITXPCU_USER_BUFFER_STATUS_E = 147 , + WIFIDATA_TO_TIME_CONFIG_E = 148 , + WIFIEXAMPLE_USER_TLV_32_E = 149 , + WIFIMPDU_INFO_E = 150 , + WIFIPDG_USER_SETUP_E = 151 , + WIFITX_11AH_SETUP_E = 152 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 , + WIFITX_PEER_ENTRY_E = 154 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 , + WIFIEXAMPLE_STRUCT_NAME_E = 156 , + WIFIPCU_PPDU_SETUP_END_INFO_E = 157 , + WIFIPPDU_RATE_SETTING_E = 158 , + WIFIPROT_RATE_SETTING_E = 159 , + WIFIRX_MPDU_DETAILS_E = 160 , + WIFIEXAMPLE_USER_TLV_42_E = 161 , + WIFIRX_MSDU_LINK_E = 162 , + WIFIRX_REO_QUEUE_E = 163 , + WIFIADDR_SEARCH_ENTRY_E = 164 , + WIFISCHEDULER_CMD_E = 165 , + WIFITX_FLUSH_E = 166 , + WIFITQM_ENTRANCE_RING_E = 167 , + WIFITX_DATA_WORD_E = 168 , + WIFITX_MPDU_DETAILS_E = 169 , + WIFITX_MPDU_LINK_E = 170 , + WIFITX_MPDU_LINK_PTR_E = 171 , + WIFITX_MPDU_QUEUE_HEAD_E = 172 , + WIFITX_MPDU_QUEUE_EXT_E = 173 , + WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 , + WIFITX_MSDU_DETAILS_E = 175 , + WIFITX_MSDU_EXTENSION_E = 176 , + WIFITX_MSDU_FLOW_E = 177 , + WIFITX_MSDU_LINK_E = 178 , + WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 , + WIFIRESPONSE_RATE_SETTING_E = 180 , + WIFITXPCU_BUFFER_BASICS_E = 181 , + WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 , + WIFIUNIFORM_TQM_CMD_HEADER_E = 183 , + WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 , + WIFIUSER_RATE_SETTING_E = 185 , + WIFIWBM_BUFFER_RING_E = 186 , + WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 , + WIFIWBM_RELEASE_RING_E = 188 , + WIFITX_FLUSH_REQ_E = 189 , + WIFIRX_MSDU_DETAILS_E = 190 , + WIFITQM_WRITE_CMD_STATUS_E = 191 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 193 , + WIFIEXAMPLE_USER_CTLV_32_E = 194 , + WIFITX_FES_STATUS_START_E = 195 , + WIFITX_FES_STATUS_USER_PPDU_E = 196 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 197 , + WIFITX_FES_STATUS_END_E = 198 , + WIFIRX_TRIG_INFO_E = 199 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 200 , + WIFIRX_FRAME_BITMAP_REQ_E = 201 , + WIFIRX_FRAME_BITMAP_ACK_E = 202 , + WIFICOEX_RX_STATUS_E = 203 , + WIFIRX_START_PARAM_E = 204 , + WIFIRX_PPDU_START_E = 205 , + WIFIRX_PPDU_END_E = 206 , + WIFIRX_MPDU_START_E = 207 , + WIFIRX_MPDU_END_E = 208 , + WIFIRX_MSDU_START_E = 209 , + WIFIRX_MSDU_END_E = 210 , + WIFIRX_ATTENTION_E = 211 , + WIFIRECEIVED_RESPONSE_INFO_E = 212 , + WIFIRX_PHY_SLEEP_E = 213 , + WIFIRX_HEADER_E = 214 , + WIFIRX_PEER_ENTRY_E = 215 , + WIFIRX_FLUSH_E = 216 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 , + WIFITX_CBF_INFO_E = 221 , + WIFIPCU_PPDU_SETUP_USER_E = 222 , + WIFIRX_MPDU_PCU_START_E = 223 , + WIFIRX_PM_INFO_E = 224 , + WIFIRX_USER_PPDU_END_E = 225 , + WIFIRX_PRE_PPDU_START_E = 226 , + WIFIRX_PREAMBLE_E = 227 , + WIFITX_FES_SETUP_COMPLETE_E = 228 , + WIFITX_LAST_MPDU_FETCHED_E = 229 , + WIFITXDMA_STOP_REQUEST_E = 230 , + WIFIRXPCU_SETUP_E = 231 , + WIFIRXPCU_USER_SETUP_E = 232 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 233 , + WIFITQM_ACKED_MPDU_E = 234 , + WIFICOEX_TX_RESP_E = 235 , + WIFICOEX_TX_STATUS_E = 236 , + WIFIMACTX_COEX_PHY_CTRL_E = 237 , + WIFICOEX_STATUS_BROADCAST_E = 238 , + WIFIRESPONSE_START_STATUS_E = 239 , + WIFIRESPONSE_END_STATUS_E = 240 , + WIFICRYPTO_STATUS_E = 241 , + WIFIRECEIVED_TRIGGER_INFO_E = 242 , + WIFIREO_ENTRANCE_RING_E = 243 , + WIFIRX_MPDU_LINK_E = 244 , + WIFICOEX_TX_STOP_CTRL_E = 245 , + WIFIRX_PPDU_ACK_REPORT_E = 246 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 247 , + WIFISCH_COEX_STATUS_E = 248 , + WIFISCHEDULER_COMMAND_STATUS_E = 249 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 , + WIFITX_FES_STATUS_PROT_E = 251 , + WIFITX_FES_STATUS_START_PPDU_E = 252 , + WIFITX_FES_STATUS_START_PROT_E = 253 , + WIFITXPCU_PHYTX_DEBUG32_E = 254 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 , + WIFIWHO_ANCHOR_OFFSET_E = 257 , + WIFIWHO_ANCHOR_VALUE_E = 258 , + WIFIWHO_CCE_INFO_E = 259 , + WIFIWHO_COMMIT_E = 260 , + WIFIWHO_COMMIT_DONE_E = 261 , + WIFIWHO_FLUSH_E = 262 , + WIFIWHO_L2_LLC_E = 263 , + WIFIWHO_L2_PAYLOAD_E = 264 , + WIFIWHO_L3_CHECKSUM_E = 265 , + WIFIWHO_L3_INFO_E = 266 , + WIFIWHO_L4_CHECKSUM_E = 267 , + WIFIWHO_L4_INFO_E = 268 , + WIFIWHO_MSDU_E = 269 , + WIFIWHO_MSDU_MISC_E = 270 , + WIFIWHO_PACKET_DATA_E = 271 , + WIFIWHO_PACKET_HDR_E = 272 , + WIFIWHO_PPDU_END_E = 273 , + WIFIWHO_PPDU_START_E = 274 , + WIFIWHO_TSO_E = 275 , + WIFIWHO_WMAC_HEADER_PV0_E = 276 , + WIFIWHO_WMAC_HEADER_PV1_E = 277 , + WIFIWHO_WMAC_IV_E = 278 , + WIFIMPDU_INFO_END_E = 279 , + WIFIMPDU_INFO_BITMAP_E = 280 , + WIFITX_QUEUE_EXTENSION_E = 281 , + WIFIRX_PEER_ENTRY_DETAILS_E = 282 , + WIFIRX_REO_QUEUE_REFERENCE_E = 283 , + WIFIRX_REO_QUEUE_EXT_E = 284 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 , + WIFITQM_ACKED_MPDU_STATUS_E = 287 , + WIFITQM_ADD_MSDU_STATUS_E = 288 , + WIFIRX_MPDU_LINK_PTR_E = 289 , + WIFIREO_DESTINATION_RING_E = 290 , + WIFITQM_LIST_GEN_DONE_E = 291 , + WIFIWHO_TERMINATE_E = 292 , + WIFITX_LAST_MPDU_END_E = 293 , + WIFITX_CV_DATA_E = 294 , + WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 , + WIFIPPDU_TX_END_E = 296 , + WIFIPROT_TX_END_E = 297 , + WIFIPDG_RESPONSE_RATE_SETTING_E = 298 , + WIFIMPDU_INFO_GLOBAL_END_E = 299 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 , + WIFIRX_PPDU_END_USER_STATS_E = 301 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 , + WIFINO_ACK_REPORT_E = 303 , + WIFIACK_REPORT_E = 304 , + WIFIUNIFORM_REO_CMD_HEADER_E = 305 , + WIFIREO_GET_QUEUE_STATS_E = 306 , + WIFIREO_FLUSH_QUEUE_E = 307 , + WIFIREO_FLUSH_CACHE_E = 308 , + WIFIREO_UNBLOCK_CACHE_E = 309 , + WIFIUNIFORM_REO_STATUS_HEADER_E = 310 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 312 , + WIFIREO_FLUSH_CACHE_STATUS_E = 313 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 , + WIFITQM_FLUSH_CACHE_E = 315 , + WIFITQM_UNBLOCK_CACHE_E = 316 , + WIFITQM_FLUSH_CACHE_STATUS_E = 317 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 , + WIFIRX_PPDU_END_STATUS_DONE_E = 319 , + WIFIRX_STATUS_BUFFER_DONE_E = 320 , + WIFIBUFFER_ADDR_INFO_E = 321 , + WIFIRX_MSDU_DESC_INFO_E = 322 , + WIFIRX_MPDU_DESC_INFO_E = 323 , + WIFITCL_DATA_CMD_E = 324 , + WIFITCL_GSE_CMD_E = 325 , + WIFITCL_EXIT_BASE_E = 326 , + WIFITCL_COMPACT_EXIT_RING_E = 327 , + WIFITCL_REGULAR_EXIT_RING_E = 328 , + WIFITCL_EXTENDED_EXIT_RING_E = 329 , + WIFIUPLINK_COMMON_INFO_E = 330 , + WIFIUPLINK_USER_SETUP_INFO_E = 331 , + WIFITX_DATA_SYNC_E = 332 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 , + WIFITCL_STATUS_RING_E = 334 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 335 , + WIFITQM_SYNC_CMD_E = 336 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 , + WIFITQM_SYNC_CMD_STATUS_E = 338 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 , + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 , + WIFIREO_TO_PPE_RING_E = 343 , + WIFIRX_MPDU_INFO_E = 344 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 , + WIFIRX_PPDU_START_USER_INFO_E = 348 , + WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 , + WIFIRX_RING_MASK_E = 350 , + WIFIWHO_CLASSIFY_INFO_E = 351 , + WIFITXPT_CLASSIFY_INFO_E = 352 , + WIFIRXPT_CLASSIFY_INFO_E = 353 , + WIFITX_FLOW_SEARCH_ENTRY_E = 354 , + WIFIRX_FLOW_SEARCH_ENTRY_E = 355 , + WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 , + WIFICOEX_MAC_NAP_E = 357 , + WIFIMACRX_ABORT_REQUEST_INFO_E = 358 , + WIFIMACTX_ABORT_REQUEST_INFO_E = 359 , + WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 , + WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 , + WIFIRXPCU_PPDU_END_INFO_E = 362 , + WIFIWHO_MESH_CONTROL_E = 363 , + WIFIL_SIG_A_INFO_E = 364 , + WIFIL_SIG_B_INFO_E = 365 , + WIFIHT_SIG_INFO_E = 366 , + WIFIVHT_SIG_A_INFO_E = 367 , + WIFIVHT_SIG_B_SU20_INFO_E = 368 , + WIFIVHT_SIG_B_SU40_INFO_E = 369 , + WIFIVHT_SIG_B_SU80_INFO_E = 370 , + WIFIVHT_SIG_B_SU160_INFO_E = 371 , + WIFIVHT_SIG_B_MU20_INFO_E = 372 , + WIFIVHT_SIG_B_MU40_INFO_E = 373 , + WIFIVHT_SIG_B_MU80_INFO_E = 374 , + WIFIVHT_SIG_B_MU160_INFO_E = 375 , + WIFISERVICE_INFO_E = 376 , + WIFIHE_SIG_A_SU_INFO_E = 377 , + WIFIHE_SIG_A_MU_DL_INFO_E = 378 , + WIFIHE_SIG_A_MU_UL_INFO_E = 379 , + WIFIHE_SIG_B1_MU_INFO_E = 380 , + WIFIHE_SIG_B2_MU_INFO_E = 381 , + WIFIHE_SIG_B2_OFDMA_INFO_E = 382 , + WIFIPDG_SW_MODE_BW_START_E = 383 , + WIFIPDG_SW_MODE_BW_END_E = 384 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 , + WIFISCHEDULER_END_E = 387 , + WIFIPEER_TABLE_ENTRY_E = 388 , + WIFISW_PEER_INFO_E = 389 , + WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 , + WIFITCL_CCE_CLASSIFY_INFO_E = 391 , + WIFIRXOLE_CCE_INFO_E = 392 , + WIFITCL_CCE_INFO_E = 393 , + WIFITCL_CCE_SUPERRULE_E = 394 , + WIFICCE_RULE_E = 395 , + WIFIRX_PPDU_START_DROPPED_E = 396 , + WIFIRX_PPDU_END_DROPPED_E = 397 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 , + WIFIRX_MPDU_START_DROPPED_E = 399 , + WIFIRX_MSDU_START_DROPPED_E = 400 , + WIFIRX_MSDU_END_DROPPED_E = 401 , + WIFIRX_MPDU_END_DROPPED_E = 402 , + WIFIRX_ATTENTION_DROPPED_E = 403 , + WIFITXPCU_USER_SETUP_E = 404 , + WIFIRXPCU_USER_SETUP_EXT_E = 405 , + WIFICE_SRC_DESC_E = 406 , + WIFICE_STAT_DESC_E = 407 , + WIFIRXOLE_CCE_SUPERRULE_E = 408 , + WIFITX_RATE_STATS_INFO_E = 409 , + WIFICMD_PART_0_END_E = 410 , + WIFIMACTX_SYNTH_ON_E = 411 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 , + WIFITQM_MPDU_GLOBAL_START_E = 413 , + WIFIEXAMPLE_TLV_32_E = 414 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 , + WIFICE_DST_DESC_E = 420 , + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 , + WIFIPDG_TRIG_RESPONSE_E = 423 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 424 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 425 , + WIFISCH_TQM_CMD_WRAPPER_E = 426 , + WIFIMPDUS_AVAILABLE_E = 427 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 , + WIFIPHYRX_PKT_END_INFO_E = 429 , + WIFIPHYRX_TX_START_TIMING_E = 430 , + WIFITXPCU_PREAMBLE_DONE_E = 431 , + WIFINDP_PREAMBLE_DONE_E = 432 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 , + WIFITX_PUNCTURE_SETUP_E = 436 , + WIFITX_PUNCTURE_PATTERN_E = 437 , + WIFIR2R_STATUS_END_E = 438 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 439 , + WIFIEND_OF_FLUSH_MARKER_E = 440 , + WIFIUPLINK_COMMON_INFO_PUNC_E = 441 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 , + WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 , + WIFITX_LOOPBACK_SETUP_E = 450 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 452 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 , + WIFITX_WUR_DATA_E = 456 , + WIFIRX_PPDU_END_START_E = 457 , + WIFIRX_PPDU_END_MIDDLE_E = 458 , + WIFIRX_PPDU_END_LAST_E = 459 , + WIFIRECEIVE_USER_INFO_L1_E = 460 , + WIFIMIMO_CONTROL_INFO_L1_E = 461 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 , + WIFISRP_INFO_E = 464 , + WIFIOBSS_SR_INFO_E = 465 , + WIFISCHEDULER_SW_MSG_STATUS_E = 466 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 , + WIFIRXPCU_SETUP_COMPLETE_E = 468 , + WIFISNOOP_PPDU_START_E = 469 , + WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 , + WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 , + WIFISNOOP_MSDU_USR_DATA_E = 472 , + WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 , + WIFISNOOP_PPDU_END_E = 474 , + WIFISNOOP_SPARE_E = 475 , + WIFIMACTX_PREFETCH_CV_BULK_E = 476 , + WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 , + WIFISW_MONITOR_RING_E = 481 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 , + WIFISCH_TLV_WRAPPER_E = 483 , + WIFISCHEDULER_STATUS_WRAPPER_E = 484 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EXPECT_RX_E = 485 , + WIFITX_HW_MPDU_LINK_E = 486 , + WIFITX_HW_MPDU_LINK_PTR_E = 487 , + WIFITX_HW_MPDU_QUEUE_EXT_E = 488 , + WIFITX_HW_MPDU_QUEUE_HEAD_E = 489 , + WIFITQM_ADD_MPDUS_E = 490 , + WIFITQM_WRITE_BACK_MPDU_INFO_E = 491 , + WIFIUNIFORM_TQM_LITE_STATUS_HEADER_E = 492 , + WIFITQM_ADD_MPDUS_STATUS_E = 493 , + WIFITQM_MPDU_RELEASE_STATUS_E = 494 , + WIFITQM_WRITE_BACK_MPDU_INFO_STATUS_E = 495 , + WIFITX_HW_MPDU_DETAILS_E = 496 , + WIFITLV_BASE_E = 511 + +} tlv_tag_def__e; + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/wcn6450/v1/tx_msdu_extension.h new file mode 100644 index 000000000000..f4822ae285f4 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tx_msdu_extension.h @@ -0,0 +1,247 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + reserved_7a : 8, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + reserved_9a : 8, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + reserved_11a : 8, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +}; + +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_WDS_LSB 16 +#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 +#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 +#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/tx_rate_stats_info.h new file mode 100644 index 000000000000..0e18d62733c1 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/tx_rate_stats_info.h @@ -0,0 +1,87 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 2, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + reserved_0a : 4; + uint32_t ppdu_transmission_tsf : 32; +}; + +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800 + +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000 + +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000 + +#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000 + +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_descriptor_header.h new file mode 100644 index 000000000000..d68432fde385 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_descriptor_header.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { + uint32_t owner : 4, + buffer_type : 4, + reserved_0a : 24; +}; + +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_cmd_header.h b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..fdc8da7a9a5b --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_cmd_header.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +}; + +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_status_header.h b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_status_header.h new file mode 100644 index 000000000000..0f6014b64e0a --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/uniform_reo_status_header.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +}; + +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/wcn6450/v1/vht_sig_a_info.h new file mode 100644 index 000000000000..16bc396179ad --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/vht_sig_a_info.h @@ -0,0 +1,117 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 8; +}; + +#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_STBC_LSB 3 +#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_N_STS_LSB 10 +#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_MCS_LSB 4 +#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_CRC_LSB 10 +#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_TAIL_LSB 18 +#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_buffer_ring.h new file mode 100644 index 000000000000..bfb268f6fbf1 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_buffer_ring.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { + struct buffer_addr_info buf_addr_info; +}; + +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..70820a174c64 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { + struct buffer_addr_info desc_addr_info; +}; + +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_release_ring.h new file mode 100644 index 000000000000..37e37b06e1cc --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wbm_release_ring.h @@ -0,0 +1,217 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "tx_rate_stats_info.h" + +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + msdu_continuation : 1; + uint32_t ack_frame_rssi : 8, + sw_release_details_valid : 1, + first_msdu : 1, + last_msdu : 1, + msdu_part_of_amsdu : 1, + fw_tx_notify_frame : 1, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + ring_id : 8, + looping_count : 4; +}; + +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31 +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000 + +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 + +#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 +#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 +#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 + +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 + +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 + +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000 + +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_TID_LSB 16 +#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_RING_ID_LSB 20 +#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..65de18e53ae3 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_seq_hwiobase.h @@ -0,0 +1,609 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __WCSS_SEQ_BASE_H__ +#define __WCSS_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + +#ifndef SOC_WCSS_BASE_ADDR + #if defined(WCSS_BASE) + #if ( WCSS_BASE != 0x0 ) + #error WCSS_BASE incorrectly redefined! + #endif + #endif + + #define SOC_WCSS_BASE_ADDR 0x0 +#else + #if ( SOC_WCSS_BASE_ADDR != 0x0 ) + #error SOC_WCSS_BASE_ADDR incorrectly redefined! + #endif +#endif + +#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 +#define SEQ_WCSS_PHYA_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00338000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00338400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00338800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00338c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00339000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00339400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00339800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0033f400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0033f600 +#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 +#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 +#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 +#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 +#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x005c5000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x005d1038 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x005d10cc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x005cb000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x005d41fc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x005d4204 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d43c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d4424 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d5c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d69c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d7040 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d7100 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d7140 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d7180 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d71c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x005d7400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x005d7400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x005d7438 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x005d74cc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x005d8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x005d8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x005d8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x005d8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x005d8940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x005d8980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x005dc400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x005dc800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x005dcc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x005dd000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x005dd400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005dd800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005dd980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005dd9c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005ddac0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x005dfd40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x005e021c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e21b8 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x005e821c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 +#define SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 +#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 +#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 +#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 +#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 +#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 +#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 +#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 +#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 +#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 +#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 +#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 +#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 +#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 +#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 +#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 +#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 +#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 +#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 +#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 +#define SEQ_WCSS_MSIP_OFFSET 0x00b80000 +#define SEQ_WCSS_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 +#define SEQ_WCSS_MSIP_WL_DAC_CH0_OFFSET 0x00b80180 +#define SEQ_WCSS_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190 +#define SEQ_WCSS_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200 +#define SEQ_WCSS_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0 +#define SEQ_WCSS_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 +#define SEQ_WCSS_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80434 +#define SEQ_WCSS_MSIP_MSIP_SHD_OTP_OFFSET 0x00b8d000 +#define SEQ_WCSS_MSIP_MSIP_TMUX_OFFSET 0x00b8d040 +#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET 0x00b8d080 +#define SEQ_WCSS_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4 +#define SEQ_WCSS_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 +#define SEQ_WCSS_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 +#define SEQ_WCSS_MSIP_BBPLL_OFFSET 0x00b8f000 +#define SEQ_WCSS_MSIP_WL_CLKGEN_OFFSET 0x00b8f800 +#define SEQ_WCSS_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 +#define SEQ_WCSS_DBG_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 +#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 +#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 +#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 +#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 +#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 +#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 +#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 +#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 +#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 +#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 +#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 +#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 +#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 +#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 +#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 +#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 +#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 +#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 +#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 +#define SEQ_WCSS_DBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00bc9000 +#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 +#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 +#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 +#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 +#define SEQ_WCSS_CC_OFFSET 0x00cb0000 +#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 + +#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00038000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00038400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00038800 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00038c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00039000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00039400 +#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00039800 +#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0003f400 +#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0003f600 +#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 +#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 +#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 +#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x002c5000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x002d1038 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x002d10cc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x002cb000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x002d41fc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x002d4204 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d43c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d4424 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d5c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d69c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d7040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d7100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d7140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d7180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d71c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x002d7400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x002d7400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x002d7438 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x002d74cc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x002d8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x002d8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x002d8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x002d8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x002d8880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x002d88c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x002d8940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x002d8980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x002dc400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x002dc800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x002dcc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x002dd000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x002dd400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002dd800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002dd980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002dd9c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002ddac0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x002dfd40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x002e021c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e21b8 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x002e821c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000 + +#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OFFSET 0x000110cc +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SW_RST_OFFSET 0x000141fc +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_RAH_OFFSET 0x00014204 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000143c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x00014424 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014880 +#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00015c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016840 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016900 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016940 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016980 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000169c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00017000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00017040 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00017100 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00017140 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00017180 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000171c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET 0x00017400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00017400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00017438 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000174cc +#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET 0x00018000 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET 0x00018000 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET 0x00018400 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET 0x00018800 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00018880 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000188c0 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET 0x00018940 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET 0x00018980 +#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DRM_REG_OFFSET 0x0001c400 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET 0x0001c800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_OFFSET 0x0001cc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_OFFSET 0x0001d000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_OFFSET 0x0001d400 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001d800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001d980 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001d9c0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001dac0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x0001fd40 +#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0002021c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000221b8 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0002821c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00028400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00028800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 + +#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000 +#define SEQ_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000 +#define SEQ_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038 +#define SEQ_RFA_SOC_PMU_PMU_OFFSET 0x000110cc +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000 + +#define SEQ_PMU_TOP_PMU_SHD_OTP_OFFSET 0x00000000 +#define SEQ_PMU_TOP_PMU_OTP_OFFSET 0x00000038 +#define SEQ_PMU_TOP_PMU_OFFSET 0x000000cc + +#define SEQ_SECURITY_CONTROL_BT_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 +#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_RAW_FUSE_OFFSET 0x00000000 +#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_CORR_FUSE_OFFSET 0x00004000 + +#define SEQ_RFA_CMN_AON_OFFSET 0x00000000 +#define SEQ_RFA_CMN_RFA_SW_RST_OFFSET 0x000001fc +#define SEQ_RFA_CMN_WL_RAH_OFFSET 0x00000204 +#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 +#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000003c0 +#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x00000424 +#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000800 +#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000880 +#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000c00 +#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00001c00 +#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002800 +#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002840 +#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002900 +#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002940 +#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002980 +#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000029c0 +#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00003000 +#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00003040 +#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00003100 +#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00003140 +#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00003180 +#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000031c0 +#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 +#define SEQ_RFA_CMN_PMU_TEST_OFFSET 0x00003400 +#define SEQ_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00003400 +#define SEQ_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00003438 +#define SEQ_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000034cc + +#define SEQ_RFA_FM_FM_MC_OFFSET 0x00000000 +#define SEQ_RFA_FM_FM_RX_OFFSET 0x00000400 +#define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET 0x00000800 +#define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00000880 +#define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000008c0 +#define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET 0x00000940 +#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET 0x00000980 + +#define SEQ_RFA_BT_BT_TOP_OFFSET 0x00000000 +#define SEQ_RFA_BT_BT_DRM_REG_OFFSET 0x00000400 +#define SEQ_RFA_BT_BT_TXBB_OFFSET 0x00000800 +#define SEQ_RFA_BT_BT_TXFE_OFFSET 0x00000c00 +#define SEQ_RFA_BT_BT_RXBB_OFFSET 0x00001000 +#define SEQ_RFA_BT_BT_RXFE_OFFSET 0x00001400 +#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00001800 +#define SEQ_RFA_BT_BT_DAC_OFFSET 0x00001980 +#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000019c0 +#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00001ac0 +#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 +#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 +#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 +#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 +#define SEQ_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x00003d40 + +#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 +#define SEQ_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0000021c +#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 +#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 +#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000021b8 +#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 +#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 +#define SEQ_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0000821c +#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00008400 +#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00008800 +#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 +#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 +#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 +#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 + +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 +#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 +#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 +#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 + +#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 + +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 + +#define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 +#define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180 +#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190 +#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200 +#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0 +#define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 +#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000434 +#define SEQ_MSIP_MSIP_SHD_OTP_OFFSET 0x0000d000 +#define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d040 +#define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 +#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4 +#define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 +#define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 +#define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 +#define SEQ_MSIP_WL_CLKGEN_OFFSET 0x0000f800 +#define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 + +#define SEQ_WCSSDBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00000000 +#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 +#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 +#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 +#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 +#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 +#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 +#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 +#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 +#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 +#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 +#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 +#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 +#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 +#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 +#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 +#define SEQ_WCSSDBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00039000 +#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 +#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 + +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 + +#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 +#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 +#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 +#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 + +#endif + diff --git a/drivers/staging/fw-api/hw/wcn6450/v1/wcss_version.h b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_version.h new file mode 100644 index 000000000000..1fe87c66bad5 --- /dev/null +++ b/drivers/staging/fw-api/hw/wcn6450/v1/wcss_version.h @@ -0,0 +1,20 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 33