A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 16:46:15 -04:00
Code Issues Projects Releases Packages Wiki Activity

ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors

Browse source 
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.

The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.

The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi.

Until the OV5652 sensor module compatible with the SabreSD becomes
available for testing, the ov5642 node is currently disabled.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Steve Longerbeam 2017-06-12 11:24:00 -07:00 • committed by Shawn Guo
commit 545fb52e53
3 changed files with 123 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/boot/dts/imx6dl-sabresd.dts
View file

@ -15,3 +15,8 @@
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
&ipu1_csi1_from_ipu1_csi1_mux {
clock-lanes = <0>;
data-lanes = <1 2>;
};

5
arch/arm/boot/dts/imx6q-sabresd.dts
View file

@ -23,3 +23,8 @@
&sata {
status = "okay";
};
&ipu1_csi1_from_mipi_vc1 {
clock-lanes = <0>;
data-lanes = <1 2>;
};

114
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View file

@ -10,6 +10,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -146,6 +147,36 @@
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
data-shift = <12>; /* Lines 19:12 used */
hsync-active = <1>;
vsync-active = <1>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@ -213,7 +244,32 @@
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
ov5642: camera@3c {
compatible = "ovti,ov5642";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5642>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
reg = <0x3c>;
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
status = "disabled";
port {
ov5642_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;
};
};
};
};
&i2c2 {
@ -222,6 +278,32 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clks IMX6QDL_CLK_CKO>;
clock-names = "xclk";
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
rev B board is VGEN5 */
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
port {
#address-cells = <1>;
#size-cells = <0>;
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
@ -425,6 +507,36 @@
>;
};
pinctrl_ipu1_csi0: ipu1csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
>;
};
pinctrl_ov5642: ov5642grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0