diff --git a/qcom/sa8195-usb.dtsi b/qcom/sa8195-usb.dtsi index 72f24f8fb7cc..e0af3a9f5973 100644 --- a/qcom/sa8195-usb.dtsi +++ b/qcom/sa8195-usb.dtsi @@ -1,5 +1,5 @@ #include - +#include &soc { /* Primary USB port related controller */ usb0: ssusb@a600000 { @@ -183,7 +183,7 @@ usb2_phy1: hsphy@88e3000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x88e3000 0x110>, - <0x007801f8 0x4>; + <0x007801f8 0x4>; reg-names = "hsusb_phy_base", "phy_rcal_reg"; @@ -200,4 +200,384 @@ qcom,param-override-seq = <0x43 0x70>; qcom,rcal-mask = <0x1e00000>; }; + + /* Tertiary USB port related controller */ + usb2: ssusb@a400000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a400000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "atomic"; + qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + dma-ranges; + interrupts-extended = <&pdc 59 IRQ_TYPE_EDGE_RISING>, + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 46 IRQ_TYPE_EDGE_RISING>, + <&pdc 71 IRQ_TYPE_EDGE_RISING>, + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 68 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq1", + "ss_phy_irq1", "dm_hs_phy_irq1"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_mp_gdsc>; + clocks = <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&gcc GCC_USB30_MP_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,ignore-wakeup-src-in-hostmode; + qcom,dual-port; + + interconnect-names = "usb-ddr", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_2>; + + dwc3@a400000 { + compatible = "snps,dwc3"; + reg = <0x0a400000 0xcd00>; + interrupts = ; + usb-phy = <&usb2_phy2>, <&usb_qmp_phy0>, + <&usb2_phy3>, <&usb_qmp_phy1>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,ssp-u3-u0-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u3_susphy_quirk; + maximum-speed = "super-speed-plus"; + dr_mode = "host"; + }; + }; + + /* Tertiary USB port 0 related High Speed PHY */ + usb2_phy2: hsphy@88e4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e4000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + /* Tertiary USB port 0 related QMP PHY */ + usb_qmp_phy0: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_1_l9>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150_2_l16>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + /* Tertiary USB port 1 related High Speed PHY */ + usb2_phy3: hsphy@88e5000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e5000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + /* Tertiary USB port 1 related QMP PHY */ + usb_qmp_phy1: ssphy@88ec000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88ec000 0x1000>, + <0x088ec88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_1_l9>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150_2_l16>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; }; + diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi index 13616c51d925..10532f45caff 100644 --- a/qcom/sa8195p.dtsi +++ b/qcom/sa8195p.dtsi @@ -71,3 +71,25 @@ vdda18-supply = <&pm8195_1_l12>; vdda33-supply = <&pm8195_3_l16>; }; + +&usb2_phy2 { + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; +}; + +&usb_qmp_phy0 { + vdd-supply = <&pm8195_3_l9>; + core-supply = <&pm8195_1_l9>; +}; + +&usb2_phy3 { + vdd-supply = <&pm8195_3_l5>; + vdda18-supply = <&pm8195_1_l12>; + vdda33-supply = <&pm8195_3_l16>; +}; + +&usb_qmp_phy1 { + vdd-supply = <&pm8195_3_l9>; + core-supply = <&pm8195_1_l9>; +};