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watchdog: s3c2410_wdt: Fix the mask bit offset for Exynos7

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The watchdog mask bit offset listed for Exynos7 is incorrect.
Fix this.

Signed-off-by: Abhilash Kesavan <[email protected]>
Acked-by: Naveen Krishna Chatradhi <[email protected]
Reviewd-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
This commit is contained in:
Abhilash Kesavan 2014-10-17 21:42:53 +05:30 • committed by Wim Van Sebroeck
commit 5476b2b77d
1 changed files with 1 additions and 1 deletions
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drivers/watchdog/s3c2410_wdt.c
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@ -161,7 +161,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
static const struct s3c2410_wdt_variant drv_data_exynos7 = {
.disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
.mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
.mask_bit = 0,
.mask_bit = 23,
.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
.rst_stat_bit = 23, /* A57 WDTRESET */
.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,