diff --git a/drivers/clk/qcom/gcc-lahaina.c b/drivers/clk/qcom/gcc-lahaina.c index 2132cc75256d..2b6136c1aa76 100644 --- a/drivers/clk/qcom/gcc-lahaina.c +++ b/drivers/clk/qcom/gcc-lahaina.c @@ -177,13 +177,6 @@ static const struct clk_parent_data gcc_parent_data_0[] = { { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, }; -static const struct clk_parent_data gcc_parent_data_0_ao[] = { - { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, - { .hw = &gcc_gpll0.clkr.hw }, - { .hw = &gcc_gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, -}; - static const struct parent_map gcc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, @@ -591,30 +584,6 @@ static struct clk_dummy usb3_uni_phy_sec_gcc_usb30_pipe_clk = { }, }; -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0), - F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x4800c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .enable_safe_config = true, - .flags = HW_CLK_CTRL_MODE, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_data = gcc_parent_data_0_ao, - .num_parents = 4, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), @@ -1816,21 +1785,6 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { }, }; -static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { - .reg = 0x48024, - .shift = 0, - .width = 4, - .clkr.hw.init = &(struct clk_init_data) { - .name = "gcc_cpuss_ahb_postdiv_clk_src", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_regmap_div_ro_ops, - }, -}; - static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { .reg = 0xf050, .shift = 0, @@ -2137,26 +2091,6 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { }, }; -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48000, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_ddrss_gpu_axi_clk = { .halt_reg = 0x71154, .halt_check = BRANCH_HALT_SKIP, @@ -3353,26 +3287,6 @@ static struct clk_branch gcc_sdcc4_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x48178, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48178, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_data = &(const struct clk_parent_data){ - .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_throttle_pcie_ahb_clk = { .halt_reg = 0x9044, .halt_check = BRANCH_HALT, @@ -4159,9 +4073,6 @@ static struct clk_regmap *gcc_lahaina_clocks[] = { [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, @@ -4273,7 +4184,6 @@ static struct clk_regmap *gcc_lahaina_clocks[] = { [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr, [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr, [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, diff --git a/include/dt-bindings/clock/qcom,gcc-lahaina.h b/include/dt-bindings/clock/qcom,gcc-lahaina.h index ec5d8699e28d..ba28f26d027f 100644 --- a/include/dt-bindings/clock/qcom,gcc-lahaina.h +++ b/include/dt-bindings/clock/qcom,gcc-lahaina.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H @@ -36,188 +36,184 @@ #define GCC_CAMERA_XO_CLK 24 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26 -#define GCC_CPUSS_AHB_CLK 27 -#define GCC_CPUSS_AHB_CLK_SRC 28 -#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 29 -#define GCC_DDRSS_GPU_AXI_CLK 30 -#define GCC_DDRSS_PCIE_SF_TBU_CLK 31 -#define GCC_DISP_AHB_CLK 32 -#define GCC_DISP_HF_AXI_CLK 33 -#define GCC_DISP_SF_AXI_CLK 34 -#define GCC_DISP_XO_CLK 35 -#define GCC_GP1_CLK 36 -#define GCC_GP1_CLK_SRC 37 -#define GCC_GP2_CLK 38 -#define GCC_GP2_CLK_SRC 39 -#define GCC_GP3_CLK 40 -#define GCC_GP3_CLK_SRC 41 -#define GCC_GPLL0 42 -#define GCC_GPLL0_OUT_EVEN 43 -#define GCC_GPLL4 44 -#define GCC_GPLL9 45 -#define GCC_GPU_CFG_AHB_CLK 46 -#define GCC_GPU_GPLL0_CLK_SRC 47 -#define GCC_GPU_GPLL0_DIV_CLK_SRC 48 -#define GCC_GPU_IREF_EN 49 -#define GCC_GPU_MEMNOC_GFX_CLK 50 -#define GCC_GPU_SNOC_DVM_GFX_CLK 51 -#define GCC_PCIE0_PHY_RCHNG_CLK 52 -#define GCC_PCIE1_PHY_RCHNG_CLK 53 -#define GCC_PCIE_0_AUX_CLK 54 -#define GCC_PCIE_0_AUX_CLK_SRC 55 -#define GCC_PCIE_0_CFG_AHB_CLK 56 -#define GCC_PCIE_0_CLKREF_EN 57 -#define GCC_PCIE_0_MSTR_AXI_CLK 58 -#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 59 -#define GCC_PCIE_0_PIPE_CLK 60 -#define GCC_PCIE_0_PIPE_CLK_SRC 61 -#define GCC_PCIE_0_SLV_AXI_CLK 62 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 63 -#define GCC_PCIE_1_AUX_CLK 64 -#define GCC_PCIE_1_AUX_CLK_SRC 65 -#define GCC_PCIE_1_CFG_AHB_CLK 66 -#define GCC_PCIE_1_CLKREF_EN 67 -#define GCC_PCIE_1_MSTR_AXI_CLK 68 -#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 69 -#define GCC_PCIE_1_PIPE_CLK 70 -#define GCC_PCIE_1_PIPE_CLK_SRC 71 -#define GCC_PCIE_1_SLV_AXI_CLK 72 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 73 -#define GCC_PDM2_CLK 74 -#define GCC_PDM2_CLK_SRC 75 -#define GCC_PDM_AHB_CLK 76 -#define GCC_PDM_XO4_CLK 77 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 78 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 79 -#define GCC_QMIP_DISP_AHB_CLK 80 -#define GCC_QMIP_VIDEO_CVP_AHB_CLK 81 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 82 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 83 -#define GCC_QUPV3_WRAP0_CORE_CLK 84 -#define GCC_QUPV3_WRAP0_S0_CLK 85 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 86 -#define GCC_QUPV3_WRAP0_S1_CLK 87 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 88 -#define GCC_QUPV3_WRAP0_S2_CLK 89 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 90 -#define GCC_QUPV3_WRAP0_S3_CLK 91 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 92 -#define GCC_QUPV3_WRAP0_S4_CLK 93 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 94 -#define GCC_QUPV3_WRAP0_S5_CLK 95 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 96 -#define GCC_QUPV3_WRAP0_S6_CLK 97 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 98 -#define GCC_QUPV3_WRAP0_S7_CLK 99 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 100 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 101 -#define GCC_QUPV3_WRAP1_CORE_CLK 102 -#define GCC_QUPV3_WRAP1_S0_CLK 103 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 104 -#define GCC_QUPV3_WRAP1_S1_CLK 105 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 106 -#define GCC_QUPV3_WRAP1_S2_CLK 107 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 108 -#define GCC_QUPV3_WRAP1_S3_CLK 109 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 110 -#define GCC_QUPV3_WRAP1_S4_CLK 111 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 112 -#define GCC_QUPV3_WRAP1_S5_CLK 113 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 114 -#define GCC_QUPV3_WRAP2_CORE_2X_CLK 115 -#define GCC_QUPV3_WRAP2_CORE_CLK 116 -#define GCC_QUPV3_WRAP2_S0_CLK 117 -#define GCC_QUPV3_WRAP2_S0_CLK_SRC 118 -#define GCC_QUPV3_WRAP2_S1_CLK 119 -#define GCC_QUPV3_WRAP2_S1_CLK_SRC 120 -#define GCC_QUPV3_WRAP2_S2_CLK 121 -#define GCC_QUPV3_WRAP2_S2_CLK_SRC 122 -#define GCC_QUPV3_WRAP2_S3_CLK 123 -#define GCC_QUPV3_WRAP2_S3_CLK_SRC 124 -#define GCC_QUPV3_WRAP2_S4_CLK 125 -#define GCC_QUPV3_WRAP2_S4_CLK_SRC 126 -#define GCC_QUPV3_WRAP2_S5_CLK 127 -#define GCC_QUPV3_WRAP2_S5_CLK_SRC 128 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 129 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 130 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 131 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 132 -#define GCC_QUPV3_WRAP_2_M_AHB_CLK 133 -#define GCC_QUPV3_WRAP_2_S_AHB_CLK 134 -#define GCC_SDCC2_AHB_CLK 135 -#define GCC_SDCC2_APPS_CLK 136 -#define GCC_SDCC2_APPS_CLK_SRC 137 -#define GCC_SDCC4_AHB_CLK 138 -#define GCC_SDCC4_APPS_CLK 139 -#define GCC_SDCC4_APPS_CLK_SRC 140 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 141 -#define GCC_THROTTLE_PCIE_AHB_CLK 142 -#define GCC_UFS_1_CLKREF_EN 143 -#define GCC_UFS_CARD_AHB_CLK 144 -#define GCC_UFS_CARD_AXI_CLK 145 -#define GCC_UFS_CARD_AXI_CLK_SRC 146 -#define GCC_UFS_CARD_AXI_HW_CTL_CLK 147 -#define GCC_UFS_CARD_ICE_CORE_CLK 148 -#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 149 -#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 150 -#define GCC_UFS_CARD_PHY_AUX_CLK 151 -#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 152 -#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 153 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 154 -#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 155 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 156 -#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 157 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158 -#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 159 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK 160 -#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 161 -#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 162 -#define GCC_UFS_PHY_AHB_CLK 163 -#define GCC_UFS_PHY_AXI_CLK 164 -#define GCC_UFS_PHY_AXI_CLK_SRC 165 -#define GCC_UFS_PHY_AXI_HW_CTL_CLK 166 -#define GCC_UFS_PHY_ICE_CORE_CLK 167 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 168 -#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 169 -#define GCC_UFS_PHY_PHY_AUX_CLK 170 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 171 -#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 172 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 173 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 174 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 175 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 176 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 177 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 178 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 179 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 180 -#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 181 -#define GCC_USB30_PRIM_MASTER_CLK 182 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 183 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 184 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 185 -#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 186 -#define GCC_USB30_PRIM_SLEEP_CLK 187 -#define GCC_USB30_SEC_MASTER_CLK 188 -#define GCC_USB30_SEC_MASTER_CLK_SRC 189 -#define GCC_USB30_SEC_MOCK_UTMI_CLK 190 -#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 191 -#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 192 -#define GCC_USB30_SEC_SLEEP_CLK 193 -#define GCC_USB3_PRIM_PHY_AUX_CLK 194 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 195 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 196 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 197 -#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 198 -#define GCC_USB3_SEC_CLKREF_EN 199 -#define GCC_USB3_SEC_PHY_AUX_CLK 200 -#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 201 -#define GCC_USB3_SEC_PHY_COM_AUX_CLK 202 -#define GCC_USB3_SEC_PHY_PIPE_CLK 203 -#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 204 -#define GCC_VIDEO_AHB_CLK 205 -#define GCC_VIDEO_AXI0_CLK 206 -#define GCC_VIDEO_AXI1_CLK 207 -#define GCC_VIDEO_XO_CLK 208 +#define GCC_DDRSS_GPU_AXI_CLK 27 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 28 +#define GCC_DISP_AHB_CLK 29 +#define GCC_DISP_HF_AXI_CLK 30 +#define GCC_DISP_SF_AXI_CLK 31 +#define GCC_DISP_XO_CLK 32 +#define GCC_GP1_CLK 33 +#define GCC_GP1_CLK_SRC 34 +#define GCC_GP2_CLK 35 +#define GCC_GP2_CLK_SRC 36 +#define GCC_GP3_CLK 37 +#define GCC_GP3_CLK_SRC 38 +#define GCC_GPLL0 39 +#define GCC_GPLL0_OUT_EVEN 40 +#define GCC_GPLL4 41 +#define GCC_GPLL9 42 +#define GCC_GPU_CFG_AHB_CLK 43 +#define GCC_GPU_GPLL0_CLK_SRC 44 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 45 +#define GCC_GPU_IREF_EN 46 +#define GCC_GPU_MEMNOC_GFX_CLK 47 +#define GCC_GPU_SNOC_DVM_GFX_CLK 48 +#define GCC_PCIE0_PHY_RCHNG_CLK 49 +#define GCC_PCIE1_PHY_RCHNG_CLK 50 +#define GCC_PCIE_0_AUX_CLK 51 +#define GCC_PCIE_0_AUX_CLK_SRC 52 +#define GCC_PCIE_0_CFG_AHB_CLK 53 +#define GCC_PCIE_0_CLKREF_EN 54 +#define GCC_PCIE_0_MSTR_AXI_CLK 55 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 56 +#define GCC_PCIE_0_PIPE_CLK 57 +#define GCC_PCIE_0_PIPE_CLK_SRC 58 +#define GCC_PCIE_0_SLV_AXI_CLK 59 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 60 +#define GCC_PCIE_1_AUX_CLK 61 +#define GCC_PCIE_1_AUX_CLK_SRC 62 +#define GCC_PCIE_1_CFG_AHB_CLK 63 +#define GCC_PCIE_1_CLKREF_EN 64 +#define GCC_PCIE_1_MSTR_AXI_CLK 65 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 66 +#define GCC_PCIE_1_PIPE_CLK 67 +#define GCC_PCIE_1_PIPE_CLK_SRC 68 +#define GCC_PCIE_1_SLV_AXI_CLK 69 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 70 +#define GCC_PDM2_CLK 71 +#define GCC_PDM2_CLK_SRC 72 +#define GCC_PDM_AHB_CLK 73 +#define GCC_PDM_XO4_CLK 74 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 75 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 76 +#define GCC_QMIP_DISP_AHB_CLK 77 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 78 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 79 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 80 +#define GCC_QUPV3_WRAP0_CORE_CLK 81 +#define GCC_QUPV3_WRAP0_S0_CLK 82 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 83 +#define GCC_QUPV3_WRAP0_S1_CLK 84 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 85 +#define GCC_QUPV3_WRAP0_S2_CLK 86 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 87 +#define GCC_QUPV3_WRAP0_S3_CLK 88 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 89 +#define GCC_QUPV3_WRAP0_S4_CLK 90 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 91 +#define GCC_QUPV3_WRAP0_S5_CLK 92 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 93 +#define GCC_QUPV3_WRAP0_S6_CLK 94 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 95 +#define GCC_QUPV3_WRAP0_S7_CLK 96 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 98 +#define GCC_QUPV3_WRAP1_CORE_CLK 99 +#define GCC_QUPV3_WRAP1_S0_CLK 100 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 101 +#define GCC_QUPV3_WRAP1_S1_CLK 102 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 103 +#define GCC_QUPV3_WRAP1_S2_CLK 104 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 105 +#define GCC_QUPV3_WRAP1_S3_CLK 106 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 107 +#define GCC_QUPV3_WRAP1_S4_CLK 108 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 109 +#define GCC_QUPV3_WRAP1_S5_CLK 110 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 111 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 112 +#define GCC_QUPV3_WRAP2_CORE_CLK 113 +#define GCC_QUPV3_WRAP2_S0_CLK 114 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 115 +#define GCC_QUPV3_WRAP2_S1_CLK 116 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 117 +#define GCC_QUPV3_WRAP2_S2_CLK 118 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 119 +#define GCC_QUPV3_WRAP2_S3_CLK 120 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 121 +#define GCC_QUPV3_WRAP2_S4_CLK 122 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 123 +#define GCC_QUPV3_WRAP2_S5_CLK 124 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 125 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 126 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 127 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 128 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 129 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 130 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 131 +#define GCC_SDCC2_AHB_CLK 132 +#define GCC_SDCC2_APPS_CLK 133 +#define GCC_SDCC2_APPS_CLK_SRC 134 +#define GCC_SDCC4_AHB_CLK 135 +#define GCC_SDCC4_APPS_CLK 136 +#define GCC_SDCC4_APPS_CLK_SRC 137 +#define GCC_THROTTLE_PCIE_AHB_CLK 138 +#define GCC_UFS_1_CLKREF_EN 139 +#define GCC_UFS_CARD_AHB_CLK 140 +#define GCC_UFS_CARD_AXI_CLK 141 +#define GCC_UFS_CARD_AXI_CLK_SRC 142 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 143 +#define GCC_UFS_CARD_ICE_CORE_CLK 144 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 145 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 146 +#define GCC_UFS_CARD_PHY_AUX_CLK 147 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 148 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 149 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 150 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 151 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 152 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 153 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 154 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 155 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 156 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 157 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 158 +#define GCC_UFS_PHY_AHB_CLK 159 +#define GCC_UFS_PHY_AXI_CLK 160 +#define GCC_UFS_PHY_AXI_CLK_SRC 161 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 162 +#define GCC_UFS_PHY_ICE_CORE_CLK 163 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 164 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 165 +#define GCC_UFS_PHY_PHY_AUX_CLK 166 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 168 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 169 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 170 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 171 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 172 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 173 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 174 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 175 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 176 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 177 +#define GCC_USB30_PRIM_MASTER_CLK 178 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 179 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 180 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 181 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 182 +#define GCC_USB30_PRIM_SLEEP_CLK 183 +#define GCC_USB30_SEC_MASTER_CLK 184 +#define GCC_USB30_SEC_MASTER_CLK_SRC 185 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 186 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 187 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 188 +#define GCC_USB30_SEC_SLEEP_CLK 189 +#define GCC_USB3_PRIM_PHY_AUX_CLK 190 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 191 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 192 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 193 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 194 +#define GCC_USB3_SEC_CLKREF_EN 195 +#define GCC_USB3_SEC_PHY_AUX_CLK 196 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 197 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 198 +#define GCC_USB3_SEC_PHY_PIPE_CLK 199 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 200 +#define GCC_VIDEO_AHB_CLK 201 +#define GCC_VIDEO_AXI0_CLK 202 +#define GCC_VIDEO_AXI1_CLK 203 +#define GCC_VIDEO_XO_CLK 204 /* GCC resets */ #define GCC_CAMERA_BCR 0