mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
== Changes to existing drivers ==
- Checkpatch fixes throughout the subsystem
- Use Regmap to handle IRQs in max77686, extcon-max77693 and mc13xxx-core
- Use DMA in rtsx_pcr
- Restrict building on unsupported architectures on timberdale, cs5535
- SPI hardening in cros_ec_spi
- More robust error handing in asic3, cros_ec, ab8500-debugfs,
max77686 and pcf50633-core
- Reorder PM runtime and regulator handing during shutdown in arizona
- Enable wakeup in cros_ec_spi
- Unused variable/code clean-up in pm8921-core, cros_ec, htc-i2cpld,
tps65912-spi, wm5110-tables and ab8500-debugfs
- Add regulator handing into suspend() in sec-core
- Remove pointless wrapper functions in extcon-max77693 and i2c-cros-ec-tunnel
- Use cross-architecture friendly data sizes in stmpe-i2c, arizona,
max77686 and tps65910
- Device Tree documentation updates throughout
- Provide power management support in max77686
- Few OF clean-ups in max77686
- Use manged resources in tps6105x
== New drivers/supported devices ==
- Add support for s2mpu02 to sec-core
- Add support for Allwinner A32 to sun6i-prcm
- Add support for Maxim 77802 in max77686
- Add support for DA9063 AD in da9063
- Add new driver for Intel PMICs (generic) and specifically Crystal Cove
== (Re-)moved drivers ==
- Move out keyboard functionality cros_ec ==> input/keyboard/cros_ec_keyb
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Merge tag 'mfd-for-linus-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD update from Lee Jones:
"Changes to existing drivers:
- checkpatch fixes throughout the subsystem
- use Regmap to handle IRQs in max77686, extcon-max77693 and
mc13xxx-core
- use DMA in rtsx_pcr
- restrict building on unsupported architectures on timberdale,
cs5535
- SPI hardening in cros_ec_spi
- more robust error handing in asic3, cros_ec, ab8500-debugfs,
max77686 and pcf50633-core
- reorder PM runtime and regulator handing during shutdown in arizona
- enable wakeup in cros_ec_spi
- unused variable/code clean-up in pm8921-core, cros_ec, htc-i2cpld,
tps65912-spi, wm5110-tables and ab8500-debugfs
- add regulator handing into suspend() in sec-core
- remove pointless wrapper functions in extcon-max77693 and
i2c-cros-ec-tunnel
- use cross-architecture friendly data sizes in stmpe-i2c, arizona,
max77686 and tps65910
- devicetree documentation updates throughout
- provide power management support in max77686
- few OF clean-ups in max77686
- use manged resources in tps6105x
New drivers/supported devices:
- add support for s2mpu02 to sec-core
- add support for Allwinner A32 to sun6i-prcm
- add support for Maxim 77802 in max77686
- add support for DA9063 AD in da9063
- new driver for Intel PMICs (generic) and specifically Crystal Cove
(Re-)moved drivers ==
- move out keyboard functionality cros_ec ==> input/keyboard/cros_ec_keyb"
* tag 'mfd-for-linus-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (101 commits)
MAINTAINERS: Update MFD repo location
mfd: omap-usb-host: Fix improper mask use.
mfd: arizona: Only free the CTRLIF_ERR IRQ if we requested it
mfd: arizona: Add missing handling for ISRC3 under/overclocked
mfd: wm5110: Add new interrupt register definitions
mfd: arizona: Rename thermal shutdown interrupt
mfd: wm5110: Add in the output done interrupts
mfd: wm5110: Remove non-existant interrupts
mfd: tps65912-spi: Remove unused variable
mfd: htc-i2cpld: Remove unused code
mfd: da9063: Add support for AD silicon variant
mfd: arizona: Map MICVDD from extcon device to the Arizona core
mfd: arizona: Add MICVDD to mapped regulators for wm8997
mfd: max77686: Ensure device type IDs are architecture agnostic
mfd: max77686: Add Maxim 77802 PMIC support
mfd: tps6105x: Use managed resources when allocating memory
mfd: wm8997-tables: Suppress 'line over 80 chars' warnings
mfd: kempld-core: Correct a variety of checkpatch warnings
mfd: ipaq-micro: Fix coding style errors/warnings reported by checkpatch
mfd: si476x-cmd: Remedy checkpatch style complains
...
This commit is contained in:
Linus Torvalds
commit
54c72d5987
94 changed files with 4309 additions and 1437 deletions
|
|
@ -450,6 +450,19 @@ config GPIO_ARIZONA
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help
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Support for GPIOs on Wolfson Arizona class devices.
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config GPIO_CRYSTAL_COVE
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tristate "GPIO support for Crystal Cove PMIC"
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depends on INTEL_SOC_PMIC
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select GPIOLIB_IRQCHIP
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help
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Support for GPIO pins on Crystal Cove PMIC.
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Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC
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inside.
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This driver can also be built as a module. If so, the module will be
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called gpio-crystalcove.
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config GPIO_LP3943
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tristate "TI/National Semiconductor LP3943 GPIO expander"
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depends on MFD_LP3943
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|
|
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|||
|
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@ -20,6 +20,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
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obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
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obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
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obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o
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obj-$(CONFIG_GPIO_CRYSTAL_COVE) += gpio-crystalcove.o
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obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o
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obj-$(CONFIG_GPIO_DA9055) += gpio-da9055.o
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obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
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|
|
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380
drivers/gpio/gpio-crystalcove.c
Normal file
380
drivers/gpio/gpio-crystalcove.c
Normal file
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@ -0,0 +1,380 @@
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/*
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* gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
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*
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* Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/seq_file.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#define CRYSTALCOVE_GPIO_NUM 16
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#define UPDATE_IRQ_TYPE BIT(0)
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#define UPDATE_IRQ_MASK BIT(1)
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#define GPIO0IRQ 0x0b
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#define GPIO1IRQ 0x0c
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#define MGPIO0IRQS0 0x19
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#define MGPIO1IRQS0 0x1a
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#define MGPIO0IRQSX 0x1b
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#define MGPIO1IRQSX 0x1c
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#define GPIO0P0CTLO 0x2b
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#define GPIO0P0CTLI 0x33
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#define GPIO1P0CTLO 0x3b
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#define GPIO1P0CTLI 0x43
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#define CTLI_INTCNT_DIS (0)
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#define CTLI_INTCNT_NE (1 << 1)
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#define CTLI_INTCNT_PE (2 << 1)
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#define CTLI_INTCNT_BE (3 << 1)
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#define CTLO_DIR_IN (0)
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#define CTLO_DIR_OUT (1 << 5)
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#define CTLO_DRV_CMOS (0)
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#define CTLO_DRV_OD (1 << 4)
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#define CTLO_DRV_REN (1 << 3)
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#define CTLO_RVAL_2KDW (0)
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#define CTLO_RVAL_2KUP (1 << 1)
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#define CTLO_RVAL_50KDW (2 << 1)
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#define CTLO_RVAL_50KUP (3 << 1)
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#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
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#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
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enum ctrl_register {
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CTRL_IN,
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CTRL_OUT,
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};
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/**
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* struct crystalcove_gpio - Crystal Cove GPIO controller
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* @buslock: for bus lock/sync and unlock.
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* @chip: the abstract gpio_chip structure.
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* @regmap: the regmap from the parent device.
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* @update: pending IRQ setting update, to be written to the chip upon unlock.
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* @intcnt_value: the Interrupt Detect value to be written.
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* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
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*/
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struct crystalcove_gpio {
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struct mutex buslock; /* irq_bus_lock */
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struct gpio_chip chip;
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struct regmap *regmap;
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int update;
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int intcnt_value;
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bool set_irq_mask;
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};
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static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc)
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{
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return container_of(gc, struct crystalcove_gpio, chip);
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}
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static inline int to_reg(int gpio, enum ctrl_register reg_type)
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{
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int reg;
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if (reg_type == CTRL_IN) {
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if (gpio < 8)
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reg = GPIO0P0CTLI;
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else
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reg = GPIO1P0CTLI;
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} else {
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if (gpio < 8)
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reg = GPIO0P0CTLO;
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else
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reg = GPIO1P0CTLO;
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}
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return reg + gpio % 8;
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}
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static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
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int gpio)
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{
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u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
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int mask = BIT(gpio % 8);
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if (cg->set_irq_mask)
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regmap_update_bits(cg->regmap, mirqs0, mask, mask);
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else
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regmap_update_bits(cg->regmap, mirqs0, mask, 0);
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}
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static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
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{
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int reg = to_reg(gpio, CTRL_IN);
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regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
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}
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static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
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{
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struct crystalcove_gpio *cg = to_cg(chip);
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return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
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CTLO_INPUT_SET);
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}
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static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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struct crystalcove_gpio *cg = to_cg(chip);
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return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),
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CTLO_OUTPUT_SET | value);
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}
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static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
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{
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struct crystalcove_gpio *cg = to_cg(chip);
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int ret;
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unsigned int val;
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ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);
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if (ret)
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return ret;
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return val & 0x1;
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}
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static void crystalcove_gpio_set(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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struct crystalcove_gpio *cg = to_cg(chip);
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if (value)
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regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
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else
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regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
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}
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static int crystalcove_irq_type(struct irq_data *data, unsigned type)
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{
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struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
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switch (type) {
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case IRQ_TYPE_NONE:
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cg->intcnt_value = CTLI_INTCNT_DIS;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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cg->intcnt_value = CTLI_INTCNT_BE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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cg->intcnt_value = CTLI_INTCNT_PE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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cg->intcnt_value = CTLI_INTCNT_NE;
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break;
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default:
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return -EINVAL;
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}
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cg->update |= UPDATE_IRQ_TYPE;
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return 0;
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}
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static void crystalcove_bus_lock(struct irq_data *data)
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{
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struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
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|
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mutex_lock(&cg->buslock);
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}
|
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static void crystalcove_bus_sync_unlock(struct irq_data *data)
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{
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struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
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int gpio = data->hwirq;
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|
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if (cg->update & UPDATE_IRQ_TYPE)
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crystalcove_update_irq_ctrl(cg, gpio);
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if (cg->update & UPDATE_IRQ_MASK)
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crystalcove_update_irq_mask(cg, gpio);
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cg->update = 0;
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mutex_unlock(&cg->buslock);
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}
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static void crystalcove_irq_unmask(struct irq_data *data)
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{
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struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
|
||||
|
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cg->set_irq_mask = false;
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cg->update |= UPDATE_IRQ_MASK;
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||||
}
|
||||
|
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static void crystalcove_irq_mask(struct irq_data *data)
|
||||
{
|
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struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));
|
||||
|
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cg->set_irq_mask = true;
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cg->update |= UPDATE_IRQ_MASK;
|
||||
}
|
||||
|
||||
static struct irq_chip crystalcove_irqchip = {
|
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.name = "Crystal Cove",
|
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.irq_mask = crystalcove_irq_mask,
|
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.irq_unmask = crystalcove_irq_unmask,
|
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.irq_set_type = crystalcove_irq_type,
|
||||
.irq_bus_lock = crystalcove_bus_lock,
|
||||
.irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
|
||||
};
|
||||
|
||||
static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
|
||||
{
|
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struct crystalcove_gpio *cg = data;
|
||||
unsigned int p0, p1;
|
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int pending;
|
||||
int gpio;
|
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unsigned int virq;
|
||||
|
||||
if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
|
||||
regmap_read(cg->regmap, GPIO1IRQ, &p1))
|
||||
return IRQ_NONE;
|
||||
|
||||
regmap_write(cg->regmap, GPIO0IRQ, p0);
|
||||
regmap_write(cg->regmap, GPIO1IRQ, p1);
|
||||
|
||||
pending = p0 | p1 << 8;
|
||||
|
||||
for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
|
||||
if (pending & BIT(gpio)) {
|
||||
virq = irq_find_mapping(cg->chip.irqdomain, gpio);
|
||||
generic_handle_irq(virq);
|
||||
}
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void crystalcove_gpio_dbg_show(struct seq_file *s,
|
||||
struct gpio_chip *chip)
|
||||
{
|
||||
struct crystalcove_gpio *cg = to_cg(chip);
|
||||
int gpio, offset;
|
||||
unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
|
||||
|
||||
for (gpio = 0; gpio < cg->chip.ngpio; gpio++) {
|
||||
regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
|
||||
regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
|
||||
regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
|
||||
&mirqs0);
|
||||
regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
|
||||
&mirqsx);
|
||||
regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
|
||||
&irq);
|
||||
|
||||
offset = gpio % 8;
|
||||
seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
|
||||
gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
|
||||
ctli & 0x1 ? "hi" : "lo",
|
||||
ctli & CTLI_INTCNT_NE ? "fall" : " ",
|
||||
ctli & CTLI_INTCNT_PE ? "rise" : " ",
|
||||
ctlo,
|
||||
mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
|
||||
mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
|
||||
irq & BIT(offset) ? "pending" : " ");
|
||||
}
|
||||
}
|
||||
|
||||
static int crystalcove_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
int irq = platform_get_irq(pdev, 0);
|
||||
struct crystalcove_gpio *cg;
|
||||
int retval;
|
||||
struct device *dev = pdev->dev.parent;
|
||||
struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
|
||||
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
|
||||
if (!cg)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, cg);
|
||||
|
||||
mutex_init(&cg->buslock);
|
||||
cg->chip.label = KBUILD_MODNAME;
|
||||
cg->chip.direction_input = crystalcove_gpio_dir_in;
|
||||
cg->chip.direction_output = crystalcove_gpio_dir_out;
|
||||
cg->chip.get = crystalcove_gpio_get;
|
||||
cg->chip.set = crystalcove_gpio_set;
|
||||
cg->chip.base = -1;
|
||||
cg->chip.ngpio = CRYSTALCOVE_GPIO_NUM;
|
||||
cg->chip.can_sleep = true;
|
||||
cg->chip.dev = dev;
|
||||
cg->chip.dbg_show = crystalcove_gpio_dbg_show;
|
||||
cg->regmap = pmic->regmap;
|
||||
|
||||
retval = gpiochip_add(&cg->chip);
|
||||
if (retval) {
|
||||
dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
|
||||
return retval;
|
||||
}
|
||||
|
||||
gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
|
||||
handle_simple_irq, IRQ_TYPE_NONE);
|
||||
|
||||
retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
|
||||
IRQF_ONESHOT, KBUILD_MODNAME, cg);
|
||||
|
||||
if (retval) {
|
||||
dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
|
||||
goto out_remove_gpio;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out_remove_gpio:
|
||||
WARN_ON(gpiochip_remove(&cg->chip));
|
||||
return retval;
|
||||
}
|
||||
|
||||
static int crystalcove_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
|
||||
int irq = platform_get_irq(pdev, 0);
|
||||
int err;
|
||||
|
||||
err = gpiochip_remove(&cg->chip);
|
||||
|
||||
if (irq >= 0)
|
||||
free_irq(irq, cg);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct platform_driver crystalcove_gpio_driver = {
|
||||
.probe = crystalcove_gpio_probe,
|
||||
.remove = crystalcove_gpio_remove,
|
||||
.driver = {
|
||||
.name = "crystal_cove_gpio",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(crystalcove_gpio_driver);
|
||||
|
||||
MODULE_AUTHOR("Yang, Bin <[email protected]>");
|
||||
MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue