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mfd: db8500: Update BML clock register for db8580
BML clock register address in DB8580 has changed.Defined a new address under different name for DB8580. Signed-off-by: Philippe Begnic <[email protected]> Acked-by: Lee Jones <[email protected]> Signed-off-by: Mike Turquette <[email protected]>
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3 changed files with 3 additions and 0 deletions
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@ -480,6 +480,7 @@ struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
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CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
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CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
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CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
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CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
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CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
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CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
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CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
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@ -32,6 +32,7 @@
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#define PRCM_PER7CLK_MGT (0x040)
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#define PRCM_LCDCLK_MGT (0x044)
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#define PRCM_BMLCLK_MGT (0x04C)
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#define PRCM_BML8580CLK_MGT (0x108)
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#define PRCM_HSITXCLK_MGT (0x050)
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#define PRCM_HSIRXCLK_MGT (0x054)
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#define PRCM_HDMICLK_MGT (0x058)
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