diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi
index 653b5282f60d..ad80f4f9aedc 100644
--- a/qcom/lahaina-rumi.dtsi
+++ b/qcom/lahaina-rumi.dtsi
@@ -72,6 +72,10 @@
 	status = "disabled";
 };
 
+&usb_qmp_phy {
+	status = "disabled";
+};
+
 &usb0 {
 	/delete-property/ extcon;
 	dwc3@a600000 {
diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi
index 8c335892a4bc..371cb78b761b 100644
--- a/qcom/lahaina-usb.dtsi
+++ b/qcom/lahaina-usb.dtsi
@@ -354,7 +354,7 @@
 			compatible = "snps,dwc3";
 			reg = <0xa800000 0xcd00>;
 			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-			usb-phy = <&usb2_phy1>, <&usb_nop_phy>;
+			usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
 			linux,sysdev_is_parent;
 			snps,disable-clk-gating;
 			snps,has-lpm-erratum;
@@ -365,7 +365,7 @@
 			snps,dis_enblslpm_quirk;
 			usb-core-id = <1>;
 			tx-fifo-resize;
-			maximum-speed = "high-speed";
+			maximum-speed = "super-speed";
 			dr_mode = "drd";
 		};
 	};
@@ -392,4 +392,132 @@
 	usb_nop_phy: usb_nop_phy {
 		compatible = "usb-nop-xceiv";
 	};
+
+	/* Secondary USB port related QMP PHY */
+	usb_qmp_phy: ssphy@88eb000 {
+		compatible = "qcom,usb-ssphy-qmp-v2";
+		reg = <0x88eb000 0x2000>,
+			<0x088eb28c 0x4>;
+		reg-names = "qmp_phy_base",
+				"pcs_clamp_enable_reg";
+		vdd-supply = <&pm8350_l1>;
+		qcom,vdd-voltage-level = <0 912000 912000>;
+		qcom,vdd-max-load-uA = <47000>;
+		core-supply = <&pm8350_l6>;
+
+		clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+				<&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+				<&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
+				<&clock_gcc USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK>,
+				<&clock_rpmh RPMH_CXO_CLK>,
+				<&clock_gcc GCC_USB3_SEC_CLKREF_EN>,
+				<&clock_gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+				"pipe_clk_ext_src", "ref_clk_src",
+				"ref_clk", "com_aux_clk";
+
+		resets = <&clock_gcc GCC_USB3_DP_PHY_SEC_BCR>,
+				<&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>;
+		reset-names = "phy_reset", "phy_phy_reset";
+		qcom,qmp-phy-reg-offset =
+				<USB3_UNI_PCS_PCS_STATUS1
+				USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+				USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+				USB3_UNI_PCS_POWER_DOWN_CONTROL
+				USB3_UNI_PCS_SW_RESET
+				USB3_UNI_PCS_START_CONTROL>;
+
+		qcom,qmp-phy-init-seq =
+				/* <reg_offset, value, delay> */
+				<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+				USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
+				USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
+				USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+				USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+				USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+				USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+				USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+				USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+				USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+				USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+				USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+				USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
+				USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
+				USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+				USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+				USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xB8 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xFF 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xBF 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0
+				USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7F 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xB4 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5C 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xDC 0
+				USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xDC 0
+				USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
+				USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+				USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+				USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
+				USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0C 0
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+				USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+				USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
+				USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+				USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
+				USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0E 0
+				USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+				USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
+				USB3_UNI_QSERDES_RX_GM_CAL 0x1F 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_1 0xD5 0
+				USB3_UNI_QSERDES_TX_LANE_MODE_2 0x80 0
+				USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
+				USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
+				USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
+				USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
+				USB3_UNI_PCS_RX_SIGDET_LVL 0xA9 0
+				USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0C 0
+				USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+				USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+				USB3_UNI_PCS_CDR_RESET_TIME 0x0A 0
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+				USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+				USB3_UNI_PCS_EQ_CONFIG1 0x4B 0
+				USB3_UNI_PCS_EQ_CONFIG5 0x10 0
+				USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
+				0xffffffff 0xffffffff 0x00>;
+	};
 };