diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 85b2a7958bff..e5d16d2541b1 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -101,6 +101,9 @@ SoCs: - HOLI compatible = "qcom,holi" +- BLAIR + compatible = "qcom,blair" + - MONACO compatible = "qcom,monaco" @@ -284,6 +287,7 @@ compatible = "qcom,holi-mtp" compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" +compatible = "qcom,blair-rumi" compatible = "qcom,scuba-idp" compatible = "qcom,monaco-rumi" compatible = "qcom,sdxnightjar-mtp" diff --git a/bindings/pinctrl/qcom,blair-pinctrl.yaml b/bindings/pinctrl/qcom,blair-pinctrl.yaml new file mode 100644 index 000000000000..1b1ce0249781 --- /dev/null +++ b/bindings/pinctrl/qcom,blair-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,blair-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. BLAIR TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + HOLI platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,blair-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@400000 { + compatible = "qcom,blair-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/Makefile b/qcom/Makefile index d7d88aff5c88..e61b0efc9314 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -125,6 +125,14 @@ dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-mtp-usbc.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_BLAIR) += blair-rumi-overlay.dtbo + +blair-rumi-overlay.dtbo-base := blair.dtb +else +dtb-$(CONFIG_ARCH_BLAIR) += blair-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo \ diff --git a/qcom/blair-pinctrl.dtsi b/qcom/blair-pinctrl.dtsi new file mode 100644 index 000000000000..9cb472d3e943 --- /dev/null +++ b/qcom/blair-pinctrl.dtsi @@ -0,0 +1,1111 @@ +&soc { + tlmm: pinctrl@400000 { + compatible = "qcom,blair-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&wakegic>; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 9: NFC Read Interrupt */ + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 9: NFC Read Interrupt */ + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* 6: Enable, 8: Firmware, 7: CLOCK */ + pins = "gpio6", "gpio8", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio8", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + /* 6: Enable, 8: Firmware, 7: CLOCK */ + pins = "gpio6", "gpio8", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio8", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_4uart_pins: qupv3_se1_4uart_pins { + qupv3_se1_default_cts: + qupv3_se1_default_cts { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_default_rtsrx: + qupv3_se1_default_rtsrx { + mux { + pins = "gpio62", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio62", "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_default_tx: + qupv3_se1_default_tx { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_ctsrx: qupv3_se1_ctsrx { + mux { + pins = "gpio61", "gpio64"; + function = "qup01"; + }; + + config { + pins = "gpio61", "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_rts: qupv3_se1_rts { + mux { + pins = "gpio62"; + function = "qup01"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_tx: qupv3_se1_tx { + mux { + pins = "gpio63"; + function = "qup01"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio45", "gpio46"; + function = "qup02"; + }; + + config { + pins = "gpio45", "gpio46"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio45", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio45", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + function = "qup02"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio13", "gpio14"; + function = "qup10"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio13", "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "qup10"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup11"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio19", "gpio20"; + function = "qup12"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { + qupv3_se9_2uart_active: qupv3_se9_2uart_active { + mux { + pins = "gpio25", "gpio26"; + function = "qup13_f2"; + }; + + config { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { + mux { + pins = "gpio25", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup14"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio94"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio94"; + bias-disable; + drive-strength = <2>; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + /* WCD reset pin */ + wcd937x_reset_active: wcd937x_reset_active { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <16>; + output-high; + }; + }; + + wcd937x_reset_sleep: wcd937x_reset_sleep { + mux { + pins = "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio83"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio23"; + function = "MDP_VSYNC"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio23"; + function = "MDP_VSYNC"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + pmx_ts_release: pmx_ts_release { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* Camera GPIOs CCI*/ + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio41", "gpio42"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio41", "gpio42"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio41", "gpio42"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio41", "gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio43", "gpio44"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio43", "gpio44"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio43", "gpio44"; + function = "CCI_I2C"; + }; + + config { + pins = "gpio43", "gpio44"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK 2*/ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK 2*/ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK 3*/ + mux { + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK 3*/ + mux { + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK 4*/ + mux { + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK 4*/ + mux { + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio34"; + function = "gpio"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active { + /* RESET1 */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend { + /* RESET1 */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_reset_active: cam_sensor_rear2_reset_active { + /* RESET2 */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_reset_suspend: cam_sensor_rear2_reset_suspend { + /* RESET2 */ + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_reset4_active: cam_sensor_reset4_active { + /* RESET4 */ + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_reset4_suspend: cam_sensor_reset4_suspend { + /* RESET4 */ + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + pm8008_active: pm8008_active { + mux { + pins = "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio58"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + }; +}; diff --git a/qcom/blair-rumi-overlay.dts b/qcom/blair-rumi-overlay.dts new file mode 100644 index 000000000000..36113587bdfb --- /dev/null +++ b/qcom/blair-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "blair-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair RUMI"; + compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi"; + qcom,msm-id = <507 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/blair-rumi.dts b/qcom/blair-rumi.dts new file mode 100644 index 000000000000..e055b7fdffa9 --- /dev/null +++ b/qcom/blair-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x50000000 0x00000100; + +#include "blair.dtsi" +#include "blair-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair RUMI"; + compatible = "qcom,blair-rumi", "qcom,blair", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi new file mode 100644 index 000000000000..3527407618aa --- /dev/null +++ b/qcom/blair-rumi.dtsi @@ -0,0 +1,122 @@ +#include +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@f420000 { + clock-frequency = <500000>; + }; + + wdog { + status = "disabled"; + }; + + usb_emu_phy_0: usb_emu_phy@0x04f20000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x04f20000 0x9500>; + + qcom,emu-init-seq = <0xffff 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x101f0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; +}; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; + +&sdhc_1 { + status = "disabled"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + cap-mmc-highspeed; + + vdd-supply = <&L7E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L12A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; +}; + +&sdhc_2 { + status = "ok"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cap-sd-highspeed; + + vdd-supply = <&L9E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L6E>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L18A>; + vdda-pll-supply = <&L22A>; + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + limit-rate = <1>; /* HS Rate-B */ + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7E>; + vcc-max-microamp = <800000>; + + vccq2-supply = <&L12A>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&L22A>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; + +/* Debug UART Console */ +&qupv3_se9_2uart { + qcom,rumi_platform; +}; + +&qupv3_se10_i2c { + status = "disabled"; +}; diff --git a/qcom/blair.dts b/qcom/blair.dts new file mode 100644 index 000000000000..57b1e25b8c40 --- /dev/null +++ b/qcom/blair.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "blair.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Blair SoC"; + compatible = "qcom,blair"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi new file mode 100644 index 000000000000..96d87849cfe1 --- /dev/null +++ b/qcom/blair.dtsi @@ -0,0 +1,3426 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. Blair "; + compatible = "qcom,blair"; + qcom,msm-id = <507 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off"; + }; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; + }; + + reserved_memory: reserved-memory { }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + + sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/ + sdhc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &qupv3_se9_2uart; + hsuart0 = &qupv3_se1_4uart; + swr0 = &swr0; + swr1 = &swr1; + }; + + firmware: firmware {}; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + + }; + }; + + soc: soc { }; +}; + +&firmware { + scm { + compatible = "qcom,scm"; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi: reserved_xbl_uefi@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + smem_mem: smem@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + fw_mem: fw_mem@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x1e00000>; + }; + + pil_wlan_mem: wlan@86500000 { + no-map; + reg = <0x0 0x86500000 0x0 0x200000>; + }; + + pil_adsp_mem: adsp@86700000 { + no-map; + reg = <0x0 0x86700000 0x0 0x2800000>; + }; + + pil_cdsp_mem: cdsp@88f00000 { + no-map; + reg = <0x0 0x88f00000 0x0 0x1e00000>; + }; + + pil_camera_mem: camera@8ad00000 { + no-map; + reg = <0x0 0x8ad00000 0x0 0x500000>; + }; + + pil_video_mem: video@8b200000 { + no-map; + reg = <0x0 0x8b200000 0x0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi@8b710000 { + no-map; + reg = <0x0 0x8b710000 0x0 0xa000>; + }; + + pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 { + no-map; + reg = <0x0 0x8b71a000 0x0 0x2000>; + }; + + pil_mpss_wlan_mem: mpss_wlan@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + removed_mem: removed_region@c0000000 { + no-map; + reg = <0x0 0xc0000000 0x0 0x5100000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + splash_memory: splash_region@0x85200000 { + reg = <0x0 0x85200000 0x0 0x00c00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@85e00000 { + reg = <0x0 0x85e00000 0x0 0x00100000>; + label = "dfps_data_region"; + }; + + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xd0000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + #gpio-cells = <2>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical", "slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x3b0>; + status = "ok"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qcom,wcn3990"; + qcom,bt-sw-ctrl-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; + qcom,bt-vdd-io-supply = <&L11A>; /* IO */ + qcom,bt-vdd-core-supply = <&L2E>; /* RFA */ + qcom,bt-vdd-pa-supply = <&L10E>; /* CH0 */ + qcom,bt-vdd-xtal-supply = <&L7A>; /* XO */ + + qcom,bt-vdd-io-config = <1700000 1900000 1 0>; + qcom,bt-vdd-core-config = <1304000 1304000 1 0>; + qcom,bt-vdd-pa-config = <3000000 3312000 1 0>; + qcom,bt-vdd-xtal-config = <1700000 1900000 1 0>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf240000 0x100000>; /* GICR * 8 */ + interrupts = ; + #gpio-cells = <0>; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + thermal_zones: thermal-zones {}; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f420000 0x1000>; + clock-frequency = <19200000>; + + frame@f421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + }; + + frame@f423000 { + frame-number = <1>; + interrupts = ; + reg = <0xf243000 0x1000>; + status = "disabled"; + }; + + frame@f425000 { + frame-number = <2>; + interrupts = ; + reg = <0xf425000 0x1000>; + status = "disabled"; + }; + + frame@f427000 { + frame-number = <3>; + interrupts = ; + reg = <0xf427000 0x1000>; + status = "disabled"; + }; + + frame@f429000 { + frame-number = <4>; + interrupts = ; + reg = <0xf429000 0x1000>; + status = "disabled"; + }; + + frame@f42b000 { + frame-number = <5>; + interrupts = ; + reg = <0xf42b000 0x1000>; + status = "disabled"; + }; + + frame@f42d000 { + frame-number = <6>; + interrupts = ; + reg = <0xf42d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + c100_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x4>; + }; + + c101_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x5>; + }; + + c102_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x6>; + }; + + c103_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x7>; + }; + + c0_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x130>; + }; + + c1_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x131>; + }; + + c2_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x132>; + }; + + c3_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x133>; + }; + + c100_scandump: c100_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x134>; + }; + + c101_scandump: c101_scandump { + qcom,dump-size = <0x10100>; + qcom,dump-id = <0x135>; + }; + + c102_scandump: c102_scandump { + qcom,dump-size = <0x25900>; + qcom,dump-id = <0x136>; + }; + + c103_scandump: c103_scandump { + qcom,dump-size = <0x25900>; + qcom,dump-id = <0x137>; + }; + + l1_icache0 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x63>; + }; + + l1_icache100 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x64>; + }; + + l1_icache101 { + qcom,dump-size = <0x10800>; + qcom,dump-id = <0x65>; + }; + + l1_icache102 { + qcom,dump-size = <0x21000>; + qcom,dump-id = <0x66>; + }; + + l1_icache103 { + qcom,dump-size = <0x21000>; + qcom,dump-id = <0x67>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x83>; + }; + + l1_dcache100 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x84>; + }; + + l1_dcache101 { + qcom,dump-size = <0x9000>; + qcom,dump-id = <0x85>; + }; + + l1_dcache102 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x86>; + }; + + l1_dcache103 { + qcom,dump-size = <0x12000>; + qcom,dump-id = <0x87>; + }; + + l2_tlb0 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x123>; + }; + + l2_tlb100 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x124>; + }; + + l2_tlb101 { + qcom,dump-size = <0x5a00>; + qcom,dump-id = <0x125>; + }; + + l2_tlb102 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x126>; + }; + + l2_tlb103 { + qcom,dump-size = <0x7800>; + qcom,dump-id = <0x127>; + }; + + cpuss_reg { + qcom,dump-size = <0x30000>; + qcom,dump-id = <0xef>; + }; + + rpm_sw { + qcom,dump-size = <0x2c000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + + pcu_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x164>; + }; + + fsm_data { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x165>; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@0x4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + wdog: qcom,wdt@f410000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf410000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-holi", "qcom,mpm"; + interrupts = ; + reg = <0x45f01b8 0x1000>, + <0x0f40000c 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + system_pm_rpm { + compatible = "qcom,system-pm-rpm"; + }; + + ipcc_mproc: qcom,ipcc@208000 { + compatible = "qcom,ipcc"; + reg = <0x208000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + clk_virt: interconnect { + compatible = "qcom,holi-clk_virt"; + #interconnect-cells = <1>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_QUP_CLK>, + <&rpmcc RPM_SMD_QUP_A_CLK>; + }; + + mmnrt_virt: interconnect@0 { + compatible = "qcom,holi-mmnrt_virt"; + #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, + <&rpmcc RPM_SMD_MMNRT_A_CLK>; + }; + + mmrt_virt: interconnect@1 { + compatible = "qcom,holi-mmrt_virt"; + #interconnect-cells = <1>; + qcom,util-factor = <142>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_MMRT_CLK>, + <&rpmcc RPM_SMD_MMRT_A_CLK>; + }; + + system_noc: interconnect@1880000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01880000 0x5f080>; + compatible = "qcom,holi-system_noc"; + #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; + }; + + config_noc: interconnect@1900000 { + reg = <0x01900000 0x6200>; + compatible = "qcom,holi-config_noc"; + #interconnect-cells = <1>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_CNOC_CLK>, + <&rpmcc RPM_SMD_CNOC_A_CLK>; + }; + + bimc: interconnect@4480000 { + reg = <0x04480000 0x80000>; + compatible = "qcom,holi-bimc"; + #interconnect-cells = <1>; + qcom,util-factor = <151>; + qcom,keepalive; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + + cpucp_l3_cpu: l3_cpu@fd90000 { + reg = <0x0fd90000 0x3000>; + compatible = "qcom,holi-cpucp-l3-cpu"; + #interconnect-cells = <1>; + clock-names = "xo", "alternate"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@9440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@9540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@9640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@9740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <0>; + }; + }; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-holi"; + qcom,bimc-log-stop; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,holi-gcc", "syscon"; + reg = <0x1400000 0x1f0000>; + reg_names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,holi-dispcc", "syscon"; + reg = <0x5f00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", "gcc_disp_gpll0_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,holi-gpucc", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_gx-supply = <&VDD_GFX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src", + "gcc_gpu_snoc_dvm_gfx_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cpucc: syscon@faa0018 { + compatible = "syscon"; + reg = <0x0faa0018 0x4>; + }; + + mccc: syscon@0447d200 { + compatible = "syscon"; + reg = <0x0447d200 0x100>; + }; + + debugcc: clock-controller@0 { + compatible = "qcom,holi-debugcc"; + qcom,gcc = <&gcc>; + qcom,dispcc = <&dispcc>; + qcom,gpucc = <&gpucc>; + qcom,cpucc = <&cpucc>; + qcom,mccc = <&mccc>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + cpufreq_hw: qcom,cpufreq-hw { + compatible = "qcom,cpufreq-hw-epss"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>, + <0x0fd04504 0x4>, <0x0fd04508 0x4>; + reg-names = "freq-domain0", "freq-domain1", + "pdmem-domain0", "pdmem-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + qcom,lut-row-size = <4>; + qcom,max-lut-entries = <12>; + qcom,skip-enable-check; + qcom,perf-lock-support; + interrupts = , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int"; + #freq-domain-cells = <2>; + }; + + qcom,cpufreq-hw-debug@0fd91000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x0fd91000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY( 1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY( 1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY( 1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY( 1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY( 2092, 4); /* 7980 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devfreq-icc"; + governor = "bw_hwmon"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@4520300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x4520300 0x300>, <0x4520200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU0>; + }; + + cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU1>; + }; + + cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU2>; + }; + + cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU3>; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU4>; + }; + + cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU5>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devfreq-icc"; + governor = "mem_latency"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU6>; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "qcom,devfreq-icc-l3"; + reg = <0xFD90100 0xa0>; + reg-names = "ftbl-base"; + governor = "mem_latency"; + interconnects = + <&cpucp_l3_cpu MASTER_CPUCP_L3_APPS + &cpucp_l3_cpu SLAVE_CPUCP_L3_CPU7>; + }; + + cpu6_cpu_ddr_lat: qcom,cpu6-cpu-ddr-lat { + compatible = "qcom,devfreq-icc"; + governor = "mem_latency"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devfreq-icc"; + governor = "compute"; + interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl { + qcom,core-dev-table = + < 710400 300000000 >, + < 940800 518400000 >, + < 1190400 748800000 >, + < 1478400 921600000 >, + < 1574400 1305600000 >, + < 1804800 1459000000 >; + }; + + cpu6_cpu_l3_tbl: qcom,cpu6-cpu-l3-tbl { + qcom,core-dev-table = + < 1017600 518400000 >, + < 1248000 748800000 >, + < 1536000 921600000 >, + < 1651200 1171200000 >, + < 1804800 1305600000 >, + < 2035200 1459000000 >; + }; + + cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU1>; + qcom,target-dev = <&cpu1_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU2>; + qcom,target-dev = <&cpu2_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU3>; + qcom,target-dev = <&cpu3_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU5>; + qcom,target-dev = <&cpu5_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = <&cpu0_cpu_l3_tbl>; + }; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 710400 MHZ_TO_MBPS( 300, 4) >, + < 940800 MHZ_TO_MBPS( 451, 4) >, + < 1190400 MHZ_TO_MBPS( 547, 4) >, + < 1478400 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS( 1017, 4) >; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 710400 MHZ_TO_MBPS( 300, 4) >, + < 1190400 MHZ_TO_MBPS( 451, 4) >, + < 1478400 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + }; + + cpu6_memlat_cpugrp: qcom,cpu6-cpugrp { + compatible = "qcom,arm-memlat-cpugrp"; + qcom,cpulist = <&CPU6 &CPU7>; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,access-ev = <0x2B>; + qcom,wb-ev = <0x18>; + qcom,core-dev-table = <&cpu6_cpu_l3_tbl>; + }; + + cpu6_cpu_ddr_latmon: qcom,cpu6-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 1017600 MHZ_TO_MBPS( 547, 4) >, + < 1248000 MHZ_TO_MBPS(1017, 4) >, + < 1536000 MHZ_TO_MBPS(1555, 4) >, + < 1804800 MHZ_TO_MBPS(1804, 4) >, + < 2035200 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1248800 MHZ_TO_MBPS( 547, 4) >, + < 1401600 MHZ_TO_MBPS( 768, 4) >, + < 1536000 MHZ_TO_MBPS(1017, 4) >, + < 1651200 MHZ_TO_MBPS(1555, 4) >, + < 1804800 MHZ_TO_MBPS(1804, 4) >, + < 2035200 MHZ_TO_MBPS(2092, 4) >; + }; + }; + + tcsr_mutex_block: syscon@340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + dcc: dcc_v2@16db000 { + compatible = "qcom,dcc-v2"; + reg = <0x16db000 0x1000>, + <0x1662000 0x2000>; + + qcom,transaction_timeout = <0>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x6000>; + + link_list1 { + qcom,curr-link-list = <6>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + link_list2 { + qcom,curr-link-list = <4>; + qcom,data-sink = "sram"; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "rpm_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + + qcom,pmic_glink_rpmsg { + qcom,glink-channels = "PMIC_RTR_ADSP_APPS"; + }; + + qcom,pmic_glink_log_rpmsg { + qcom,glink-channels = "PMIC_LOGS_ADSP_APPS"; + qcom,intents = <0x800 5 + 0xc00 3>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "dsps_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "core"; + qcom,threshold-arr = <0x0F800058 0x0F810058 0x0F820058 0x0F830058 + 0x0F840058 0x0F850058 0x0F860058 0x0F870058>; + qcom,config-arr = <0x0F800060 0x0F810060 0x0F820060 0x0F830060 + 0x0F840060 0x0F850060 0x0F860060 0x0F870060>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + ; + interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + qcom,venus@5ab0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ab0000 0x20000>; + + vdd-supply = <&gcc_venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>; + clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk"; + + qcom,core-freq = <240000000>; + qcom,ahb-freq = <240000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 + &bimc SLAVE_EBI>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,vm-nav-path; + }; + + ufsphy_mem: ufsphy_mem@4807000 { + reg = <0x4807000 0xDDC>; + reg-names = "phy_mem"; + #phy-cells = <0>; + lanes-per-direction = <1>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1001 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1002 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1006 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1009 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A3 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A4 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A5 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A6 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x00A7 0x0000>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable", "HUPCF"; + }; + }; + + ufshc_mem: ufshc@4804000 { + compatible = "qcom,ufshc"; + reg = <0x4804000 0x3000>, + <0x4808000 0x8000>, + <0x4810000 0x9000>; + reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + limit-phy-submode = <0>; + spm-level = <5>; + rpm-level = <3>; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + + interconnects = <&system_noc MASTER_UFS_MEM &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <12>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "fastmap"; + + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; + reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <59>; + }; + + qos1 { + mask = <0xc0>; + vote = <65>; + }; + }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, + <0x04748000 0x8000>, <0x04750000 0x9000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice", + "cqhci_ice_hwkm"; + + iommus = <&apps_smmu 0x20 0x0>; + qcom,iommu-dma = "fastmap"; + + /* + * iommu-dma-addr-pool- Indicate the range of data addresses which will be + * used in dma allocation. + * + * iommu-geometry - This is specific for fastmap which Allow clients + * to save SMMU page table memory. + * + * The 2nd parameter indicates size of the smmu page table memory. + * If its exceeds beyond this size, last unused entry from page table + * memory will be invalidated. + * + * It's better to provide range of dma address, hence provide + * iommu-dma-addr-pool property along with iommu-geometry property. + */ + + qcom,iommu-dma-addr-pool = <0x40000000 0x40000000>; + qcom,iommu-geometry = <0x40000000 0x40000000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "core", "iface", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + interconnects = <&system_noc MASTER_EMMC &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_EMMC_CFG>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 1600>, <1600 1600>, + /* 25 MB/s */ + <25600 250000>, <50000 133320>, + /* 50 MB/s */ + <51200 250000>, <65000 133320>, + /* 100 MB/s */ + <102400 250000>, <65000 133320>, + /* 200 MB/s */ + <204800 800000>, <200000 300000>, + /* 400 MB/s */ + <204800 800000>, <200000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 400000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + cap-mmc-hw-reset; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + max-frequency = <192000000>; + + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <61>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x04784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + + interconnects = <&system_noc MASTER_SDCC_2 &bimc SLAVE_EBI>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No Vote */ + <0 0>, <0 0>, + /* 400 KB/s*/ + <1046 3200>, <1600 1600>, + /* 25 MB/s */ + <65360 250000>, <100000 133320>, + /* 50 MB/s */ + <130718 250000>, <133320 133320>, + /* 100 MB/s */ + <261438 250000>, <150000 133320>, + /* 200 MB/s */ + <261438 800000>, <300000 300000>, + /* Max. bandwidth */ + <1338562 4096000>, <1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000 + 100000000 200000000 4294967295>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>; + + bus-width = <4>; + + iommus = <&apps_smmu 0x40 0x0>; + qcom,iommu-dma = "bypass"; + + no-mmc; + no-sdio; + max-frequency = <202000000>; + + qcom,devfreq,freq-table = <50000000 202000000>; + + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <61>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; + }; + + qcom,lpass@a400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xa400000 0x00100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>; + qcom,vdd_lpi_cx-uV-uA = ; + vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>; + qcom,vdd_lpi_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,minidump-id = <5>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom,turing@b000000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xb000000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,minidump-id = <7>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + qcom,minidump-as-elf32; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + pil_modem: qcom,mss@06000000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x06000000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_mpss_wlan_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom_qseecom: qseecom@c1800000 { + compatible = "qcom,qseecom"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_cedev: qcedev@1b20000 { + compatible = "qcom,qcedev"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,ce-opp-freq = <192000000>; + qcom,smmu-s1-enable; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + iommus = <&apps_smmu 0x0486 0x0011>; + qcom,iommu-dma = "atomic"; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x492 0>, + <&apps_smmu 0x498 0x0001>, + <&apps_smmu 0x49F 0>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x493 0>, + <&apps_smmu 0x49C 0x0001>, + <&apps_smmu 0x49E 0>; + qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */ + qcom,secure-context-bank; + }; + }; + + qcom_crypto: qcrypto@1b20000 { + compatible = "qcom,qcrypto"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = ; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>, + <&rpmcc RPM_SMD_CE1_CLK>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + interconnect-names = "data_path"; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 &bimc SLAVE_EBI>; + iommus = <&apps_smmu 0x0484 0x0011>; + qcom,iommu-dma = "atomic"; + }; + + qcom_rng: qrng@4453000 { + compatible = "qcom,msm-rng"; + reg = <0x4453000 0x1000>; + qcom,no-qrng-config; + interconnect-names = "data_path"; + interconnects = <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_HWKM>; + clock-names = "km_clk_src"; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + }; + + qcom_hwkm: hwkm@4440000 { + compatible = "qcom,hwkm"; + reg = <0x4440000 0x9000>, <0x04810000 0x9000>; + reg-names = "km_master", "ice_slave"; + qcom,enable-hwkm-clk; + clock-names = "km_clk_src"; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + qcom,op-freq-hz = <75000000>; + }; + + qcom_tzlog: tz-log@c125720 { + compatible = "qcom,tz-log"; + reg = <0xc125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + eud: qcom,msm-eud@1628000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1628000 0x2000>, + <0x162A000 0x1000>, + <0x3E5018 0x4>; + reg-names = "eud_base", "eud_mode_mgr2", + "eud_tcsr_check_reg"; + qcom,secure-eud-en; + qcom,eud-tcsr-check-enable; + status = "ok"; + }; + + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x80 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,iommu-dma = "fastmap"; + qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; + qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; + qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; + vdd-cx-mx-supply = <&L4A>; + vdd-1.8-xo-supply = <&L7A>; + vdd-1.3-rfa-supply = <&L2E>; + vdd-3.3-ch1-supply = <&L11E>; + vdd-3.3-ch0-supply = <&L10E>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch1-config = <3000000 3312000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + ipa_hw: qcom,ipa@0x5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x84000>, + <0x5804000 0x23000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = , + ; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <20>; /* IPA core version = IPAv4.11 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <1>; /* MSM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,arm-smmu; + qcom,use-64-bit-dma-mask; + qcom,lan-rx-napi; + qcom,wan-use-skb-page; + qcom,rmnet-ctl-enable; + qcom,ipa-endp-delay-wa; + qcom,tx-wrapper-cache-max-size = <400>; + clock-names = "core_clk"; + clocks = <&rpmcc RPM_SMD_IPA_CLK>; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <3>; + interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI>, + <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, + <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_IPA_CFG>; + interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0>; + + /* SVS2 */ + qcom,svs2 = + <80000 465000 80000 68570 80000 30>; + + /* SVS */ + qcom,svs = + <80000 2000000 80000 267461 80000 109890>; + + /* NOMINAL */ + qcom,nominal = + <206000 4000000 206000 712961 206000 491520>; + + /* TURBO */ + qcom,turbo = + <206000 5598900 206000 1436481 206000 491520>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x04A0 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x0C123000 0x0C123000 0x2000>; + qcom,iommu-dma = "fastmap"; + qcom,ipa-q6-smem-size = <36864>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x04A1 0x0>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x04A2 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "atomic"; + }; + + ipa_smmu_11ad: ipa_smmu_11ad { + compatible = "qcom,ipa-smmu-11ad-cb"; + iommus = <&apps_smmu 0x04A3 0x0>; + qcom,shared-cb; + qcom,iommu-group = <>; + }; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + + gpu_speed_bin: gpu_speed_bin@6015 { + reg = <0x6015 0x1>; + bits = <0 8>; + }; + + adsp_variant: adsp_variant@1E6 { + reg = <0x1E6 0x2>; + bits = <6 4>; + }; + + feat_conf8: feat_conf8@6024 { + reg = <0x6024 0x4>; + }; + + gpu_gaming_bin: gpu_gaming_bin@6026 { + reg = <0x6026 0x1>; + bits = <5 1>; + }; + + feat_conf9: feat_conf9@6028 { + reg = <0x6028 0x4>; + }; + }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&gpu_speed_bin>, + <&adsp_variant>, + <&feat_conf8>, + <&gpu_gaming_bin>, + <&feat_conf9>; + nvmem-cell-names = "gpu_speed_bin", + "adsp_variant", + "feat_conf8", + "gpu_gaming_bin", + "feat_conf9"; + }; +}; + +#include "holi-gpu.dtsi" +#include "blair-pinctrl.dtsi" +#include "pm6350-rpm-regulator.dtsi" +#include "pm6150l-rpm-regulator.dtsi" +#include "holi-regulators.dtsi" +#include "holi-gdsc.dtsi" +#include "holi-ion.dtsi" +#include "msm-arm-smmu-holi.dtsi" +#include "holi-coresight.dtsi" +#include "holi-pm.dtsi" +#include "holi-vidc.dtsi" +#include "camera/holi-camera.dtsi" +#include "holi-thermal.dtsi" +#include "holi-qupv3.dtsi" +#include "display/holi-sde.dtsi" +#include "holi-audio.dtsi" +#include "ipcc-test-holi.dtsi" + +&gcc_camss_top_gdsc { + status = "ok"; +}; + +&gcc_ufs_phy_gdsc { + status = "ok"; +}; + +&gcc_usb30_prim_gdsc { + status = "ok"; +}; + +&gcc_vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gcc_venus_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; + status = "ok"; +}; + +&qupv3_se1_4uart { + status = "ok"; +}; + +&qupv3_se9_2uart { + status = "ok"; +}; + +#include "msm-rdbg.dtsi"