From 551af1de3530b9a855dde0455b741bfc5d9fc4db Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 23 Mar 2020 17:29:59 -0700 Subject: [PATCH] msm: pcie: correct PCIe1 and PCIe2 clock order PCIe1 and PCIe2 default clock structure needs to have same clock order as PCIe0. Update the order of PCIe1 and PCIe2 to be the same as PCIe0. Change-Id: Icefb0f85e301cb3ba9ee4c07d01cf4110137d489 Signed-off-by: Tony Truong --- drivers/pci/controller/pci-msm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c index b27d28f65595..bc24411dc5c7 100644 --- a/drivers/pci/controller/pci-msm.c +++ b/drivers/pci/controller/pci-msm.c @@ -886,9 +886,9 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_1_sleep_clk", 0, false, false}, {NULL, "pcie_phy_refgen_clk", 0, false, true}, {NULL, "pcie_tbu_clk", 0, false, true}, + {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, {NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false}, {NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false}, - {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, {NULL, "pcie_phy_aux_clk", 0, false, false}, {NULL, "pcie_pipe_clk_mux", 0, false, false}, @@ -906,9 +906,9 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_2_sleep_clk", 0, false, false}, {NULL, "pcie_phy_refgen_clk", 0, false, true}, {NULL, "pcie_tbu_clk", 0, false, true}, + {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, {NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false}, {NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false}, - {NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true}, {NULL, "pcie_phy_cfg_ahb_clk", 0, false, false}, {NULL, "pcie_phy_aux_clk", 0, false, false}, {NULL, "pcie_pipe_clk_mux", 0, false, false},