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[PATCH] powerpc: G4+ oprofile support
This patch adds oprofile support for the 7450 and all its multitudinous derivatives. * Added 7450 (and derivatives) support for oprofile * Changed e500 cputable to have oprofile model and cpu_type fields * Added support for classic 32-bit performance monitor interrupt * Cleaned up common powerpc oprofile code to be as common as possible * Cleaned up oprofile_impl.h to reflect 32 bit classic code * Added 32-bit MMCRx bitfield definitions and SPR numbers Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Andy Fleming
Paul Mackerras
parent
e5cd040409
commit
555d97ac87
9 changed files with 344 additions and 84 deletions
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@ -22,24 +22,22 @@ struct op_counter_config {
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unsigned long enabled;
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unsigned long event;
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unsigned long count;
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/* Classic doesn't support per-counter user/kernel selection */
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unsigned long kernel;
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#ifdef __powerpc64__
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/* We dont support per counter user/kernel selection */
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#endif
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unsigned long user;
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unsigned long unit_mask;
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};
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/* System-wide configuration as set via oprofilefs. */
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struct op_system_config {
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#ifdef __powerpc64__
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#ifdef CONFIG_PPC64
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unsigned long mmcr0;
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unsigned long mmcr1;
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unsigned long mmcra;
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#endif
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unsigned long enable_kernel;
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unsigned long enable_user;
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#ifdef __powerpc64__
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#ifdef CONFIG_PPC64
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unsigned long backtrace_spinlocks;
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#endif
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};
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@ -49,9 +47,7 @@ struct op_powerpc_model {
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void (*reg_setup) (struct op_counter_config *,
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struct op_system_config *,
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int num_counters);
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#ifdef __powerpc64__
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void (*cpu_setup) (void *);
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#endif
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void (*start) (struct op_counter_config *);
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void (*stop) (void);
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void (*handle_interrupt) (struct pt_regs *,
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@ -59,10 +55,19 @@ struct op_powerpc_model {
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int num_counters;
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};
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#ifdef __powerpc64__
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#ifdef CONFIG_FSL_BOOKE
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extern struct op_powerpc_model op_model_fsl_booke;
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#else /* Otherwise, it's classic */
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#ifdef CONFIG_PPC64
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extern struct op_powerpc_model op_model_rs64;
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extern struct op_powerpc_model op_model_power4;
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#else /* Otherwise, CONFIG_PPC32 */
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extern struct op_powerpc_model op_model_7450;
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#endif
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/* All the classic PPC parts use these */
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static inline unsigned int ctr_read(unsigned int i)
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{
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switch(i) {
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@ -78,10 +83,14 @@ static inline unsigned int ctr_read(unsigned int i)
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return mfspr(SPRN_PMC5);
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case 5:
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return mfspr(SPRN_PMC6);
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/* No PPC32 chip has more than 6 so far */
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#ifdef CONFIG_PPC64
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case 6:
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return mfspr(SPRN_PMC7);
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case 7:
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return mfspr(SPRN_PMC8);
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#endif
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default:
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return 0;
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}
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@ -108,16 +117,20 @@ static inline void ctr_write(unsigned int i, unsigned int val)
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case 5:
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mtspr(SPRN_PMC6, val);
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break;
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/* No PPC32 chip has more than 6, yet */
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#ifdef CONFIG_PPC64
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case 6:
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mtspr(SPRN_PMC7, val);
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break;
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case 7:
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mtspr(SPRN_PMC8, val);
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break;
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#endif
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default:
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break;
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}
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}
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#endif /* __powerpc64__ */
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#endif /* !CONFIG_FSL_BOOKE */
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#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
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@ -443,12 +443,35 @@
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#define SPRN_SDAR 781
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#else /* 32-bit */
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#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
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#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
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#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
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#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
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#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
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#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
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#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
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#define MMCR0_FC 0x80000000UL /* freeze counters */
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#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
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#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
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#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
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#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
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#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
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#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
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#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
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#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
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#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
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#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
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#define SPRN_MMCR1 956
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#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
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#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
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#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
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#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
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#define SPRN_MMCR2 944
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#define SPRN_PMC1 953 /* Performance Counter Register 1 */
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#define SPRN_PMC2 954 /* Performance Counter Register 2 */
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#define SPRN_PMC3 957 /* Performance Counter Register 3 */
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#define SPRN_PMC4 958 /* Performance Counter Register 4 */
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#define SPRN_PMC5 945 /* Performance Counter Register 5 */
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#define SPRN_PMC6 946 /* Performance Counter Register 6 */
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#define SPRN_SIAR 955 /* Sampled Instruction Address Register */
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/* Bit definitions for MMCR0 and PMC1 / PMC2. */
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#define MMCR0_PMC1_CYCLES (1 << 7)
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@ -458,7 +481,6 @@
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#define MMCR0_PMC2_CYCLES 0x1
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#define MMCR0_PMC2_ITLB 0x7
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#define MMCR0_PMC2_LOADMISSTIME 0x5
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#define MMCR0_PMXE (1 << 26)
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#endif
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/* Processor Version Register (PVR) field extraction */
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