From 557c875ada3489885bca234a7c5d99cbbf507ddc Mon Sep 17 00:00:00 2001
From: Vijayavardhan Vennapusa <vvreddy@qti.qualcomm.com>
Date: Tue, 9 Mar 2021 12:03:21 +0530
Subject: [PATCH] ARM: dts: msm: Enable PCIe0 nodes only for iot variant

Enable PCIe0 nodes only for iot variant as HSP attach over PCIe
is required to support for IOT variants.

Change-Id: I6bc3b5325b40381f4fa4bfc3631a9bbaccba5265
---
 qcom/yupik-iot-idp.dtsi  | 8 ++++++++
 qcom/yupik-pcie.dtsi     | 5 +++++
 qcom/yupikp-iot-idp.dtsi | 8 ++++++++
 3 files changed, 21 insertions(+)

diff --git a/qcom/yupik-iot-idp.dtsi b/qcom/yupik-iot-idp.dtsi
index 31da5af1d4e3..55e5d0e3bf91 100644
--- a/qcom/yupik-iot-idp.dtsi
+++ b/qcom/yupik-iot-idp.dtsi
@@ -1,2 +1,10 @@
 #include "yupik-idp.dtsi"
 #include "qcx6490-cnss.dtsi"
+
+&pcie0 {
+	status = "ok";
+};
+
+&pcie0_msi {
+	status = "ok";
+};
diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi
index a724fab080a6..72baf84b90a6 100644
--- a/qcom/yupik-pcie.dtsi
+++ b/qcom/yupik-pcie.dtsi
@@ -226,6 +226,8 @@
 				0x0800 0x00 0x0
 				0x0844 0x03 0x0>;
 
+		status = "disabled";
+
 		pcie0_rp: pcie0_rp {
 			reg = <0 0 0 0 0>;
 		};
@@ -268,5 +270,8 @@
 			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
 			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
 			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+
+		status = "disabled";
+
 	};
 };
diff --git a/qcom/yupikp-iot-idp.dtsi b/qcom/yupikp-iot-idp.dtsi
index 90377734afa9..bc2beeb0b0ff 100644
--- a/qcom/yupikp-iot-idp.dtsi
+++ b/qcom/yupikp-iot-idp.dtsi
@@ -1,2 +1,10 @@
 #include "yupikp-idp.dtsi"
 #include "qcx6490-cnss.dtsi"
+
+&pcie0 {
+	status = "ok";
+};
+
+&pcie0_msi {
+	status = "ok";
+};