A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-08 21:22:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

disp: msm: dp: add support for 7nm pll

Browse source 
Add support for 7nm pll. Only some offsets are different from 5nm
pll while the rest are same.

Change-Id: If61cd604d7f8221c659f1b83761647e86e3b6627
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
This commit is contained in:
Rajat Gupta 2021-01-12 15:51:08 +05:30
commit 557d8d3fa5
3 changed files with 89 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

6
msm/dp/dp_pll.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/err.h>
@ -52,6 +52,7 @@ static int dp_pll_clock_register(struct dp_pll *pll)
switch (pll->revision) {
case DP_PLL_5NM_V1:
case DP_PLL_5NM_V2:
case DP_PLL_7NM:
rc = dp_pll_clock_register_5nm(pll);
break;
default:
@ -67,6 +68,7 @@ static void dp_pll_clock_unregister(struct dp_pll *pll)
switch (pll->revision) {
case DP_PLL_5NM_V1:
case DP_PLL_5NM_V2:
case DP_PLL_7NM:
dp_pll_clock_unregister_5nm(pll);
break;
default:
@ -102,6 +104,8 @@ struct dp_pll *dp_pll_get(struct dp_pll_in *in)
pll->revision = DP_PLL_5NM_V1;
} else if (!strcmp(label, "5nm-v2")) {
pll->revision = DP_PLL_5NM_V2;
} else if (!strcmp(label, "7nm")) {
pll->revision = DP_PLL_7NM;
} else {
DP_ERR("Unsupported pll revision\n");
rc = -ENOTSUPP;

4
msm/dp/dp_pll.h
View file

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
#ifndef __DP_PLL_H
@ -34,6 +34,7 @@ enum dp_pll_revision {
DP_PLL_UNKNOWN,
DP_PLL_5NM_V1,
DP_PLL_5NM_V2,
DP_PLL_7NM,
};
static inline const char *dp_pll_get_revision(enum dp_pll_revision rev)
@ -42,6 +43,7 @@ static inline const char *dp_pll_get_revision(enum dp_pll_revision rev)
case DP_PLL_UNKNOWN: return "DP_PLL_UNKNOWN";
case DP_PLL_5NM_V1: return "DP_PLL_5NM_V1";
case DP_PLL_5NM_V2: return "DP_PLL_5NM_V2";
case DP_PLL_7NM: return "DP_PLL_7NM";
default: return "???";
}
}

113
msm/dp/dp_pll_5nm.c
View file

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
/*
@ -146,10 +146,13 @@
/* Tx tran offsets */
#define DP_TRAN_DRVR_EMP_EN 0x00C0
#define DP_TRAN_DRVR_EMP_EN_7nm 0x00B8
#define DP_TX_INTERFACE_MODE 0x00C4
#define DP_TX_INTERFACE_MODE_7nm 0x00BC
/* Tx VMODE offsets */
#define DP_VMODE_CTRL1 0x00C8
#define DP_VMODE_CTRL1_7nm 0x00E8
#define DP_PHY_PLL_POLL_SLEEP_US 500
#define DP_PHY_PLL_POLL_TIMEOUT_US 10000
@ -241,6 +244,79 @@ static int dp_vco_pll_init_db_5nm(struct dp_pll_db *pdb,
return 0;
}
static void dp_pll_config_tx_7nm(struct dp_pll *pll)
{
/* TX-0 register configuration */
dp_pll_write(dp_phy, DP_PHY_TX0_TX1_LANE_CTL, 0x05);
dp_pll_write(dp_ln_tx0, DP_VMODE_CTRL1_7nm, 0x40);
dp_pll_write(dp_ln_tx0, TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
dp_pll_write(dp_ln_tx0, TXn_INTERFACE_SELECT, 0x3b);
dp_pll_write(dp_ln_tx0, TXn_CLKBUF_ENABLE, 0x0f);
dp_pll_write(dp_ln_tx0, TXn_RESET_TSYNC_EN, 0x03);
dp_pll_write(dp_ln_tx0, DP_TRAN_DRVR_EMP_EN_7nm, 0xf);
dp_pll_write(dp_ln_tx0, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
dp_pll_write(dp_ln_tx0, DP_TX_INTERFACE_MODE_7nm, 0x00);
dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
dp_pll_write(dp_ln_tx0, TXn_TX_BAND, 0x04);
/* Make sure the PLL register writes are done */
wmb();
/* TX-1 register configuration */
dp_pll_write(dp_phy, DP_PHY_TX2_TX3_LANE_CTL, 0x05);
dp_pll_write(dp_ln_tx1, DP_VMODE_CTRL1_7nm, 0x40);
dp_pll_write(dp_ln_tx1, TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
dp_pll_write(dp_ln_tx1, TXn_INTERFACE_SELECT, 0x3b);
dp_pll_write(dp_ln_tx1, TXn_CLKBUF_ENABLE, 0x0f);
dp_pll_write(dp_ln_tx1, TXn_RESET_TSYNC_EN, 0x03);
dp_pll_write(dp_ln_tx1, DP_TRAN_DRVR_EMP_EN_7nm, 0xf);
dp_pll_write(dp_ln_tx1, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
dp_pll_write(dp_ln_tx1, DP_TX_INTERFACE_MODE_7nm, 0x00);
dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
dp_pll_write(dp_ln_tx1, TXn_TX_BAND, 0x04);
/* Make sure the PHY register writes are done */
wmb();
}
static void dp_pll_config_tx_5nm(struct dp_pll *pll)
{
/* TX-0 register configuration */
dp_pll_write(dp_phy, DP_PHY_TX0_TX1_LANE_CTL, 0x05);
dp_pll_write(dp_ln_tx0, DP_VMODE_CTRL1, 0x40);
dp_pll_write(dp_ln_tx0, TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
dp_pll_write(dp_ln_tx0, TXn_INTERFACE_SELECT, 0x3b);
dp_pll_write(dp_ln_tx0, TXn_CLKBUF_ENABLE, 0x0f);
dp_pll_write(dp_ln_tx0, TXn_RESET_TSYNC_EN, 0x03);
dp_pll_write(dp_ln_tx0, DP_TRAN_DRVR_EMP_EN, 0xf);
dp_pll_write(dp_ln_tx0, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
dp_pll_write(dp_ln_tx0, DP_TX_INTERFACE_MODE, 0x00);
dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
dp_pll_write(dp_ln_tx0, TXn_TX_BAND, 0x04);
/* Make sure the PLL register writes are done */
wmb();
/* TX-1 register configuration */
dp_pll_write(dp_phy, DP_PHY_TX2_TX3_LANE_CTL, 0x05);
dp_pll_write(dp_ln_tx1, DP_VMODE_CTRL1, 0x40);
dp_pll_write(dp_ln_tx1, TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
dp_pll_write(dp_ln_tx1, TXn_INTERFACE_SELECT, 0x3b);
dp_pll_write(dp_ln_tx1, TXn_CLKBUF_ENABLE, 0x0f);
dp_pll_write(dp_ln_tx1, TXn_RESET_TSYNC_EN, 0x03);
dp_pll_write(dp_ln_tx1, DP_TRAN_DRVR_EMP_EN, 0xf);
dp_pll_write(dp_ln_tx1, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
dp_pll_write(dp_ln_tx1, DP_TX_INTERFACE_MODE, 0x00);
dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
dp_pll_write(dp_ln_tx1, TXn_TX_BAND, 0x04);
/* Make sure the PHY register writes are done */
wmb();
}
static int dp_config_vco_rate_5nm(struct dp_pll_vco_clk *vco,
unsigned long rate)
{
@ -340,37 +416,10 @@ static int dp_config_vco_rate_5nm(struct dp_pll_vco_clk *vco,
/* Make sure the PLL register writes are done */
wmb();
/* TX-0 register configuration */
dp_pll_write(dp_phy, DP_PHY_TX0_TX1_LANE_CTL, 0x05);
dp_pll_write(dp_ln_tx0, DP_VMODE_CTRL1, 0x40);
dp_pll_write(dp_ln_tx0, TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
dp_pll_write(dp_ln_tx0, TXn_INTERFACE_SELECT, 0x3b);
dp_pll_write(dp_ln_tx0, TXn_CLKBUF_ENABLE, 0x0f);
dp_pll_write(dp_ln_tx0, TXn_RESET_TSYNC_EN, 0x03);
dp_pll_write(dp_ln_tx0, DP_TRAN_DRVR_EMP_EN, 0xf);
dp_pll_write(dp_ln_tx0, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
dp_pll_write(dp_ln_tx0, DP_TX_INTERFACE_MODE, 0x00);
dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
dp_pll_write(dp_ln_tx0, TXn_TX_BAND, 0x04);
/* Make sure the PLL register writes are done */
wmb();
/* TX-1 register configuration */
dp_pll_write(dp_phy, DP_PHY_TX2_TX3_LANE_CTL, 0x05);
dp_pll_write(dp_ln_tx1, DP_VMODE_CTRL1, 0x40);
dp_pll_write(dp_ln_tx1, TXn_PRE_STALL_LDO_BOOST_EN, 0x30);
dp_pll_write(dp_ln_tx1, TXn_INTERFACE_SELECT, 0x3b);
dp_pll_write(dp_ln_tx1, TXn_CLKBUF_ENABLE, 0x0f);
dp_pll_write(dp_ln_tx1, TXn_RESET_TSYNC_EN, 0x03);
dp_pll_write(dp_ln_tx1, DP_TRAN_DRVR_EMP_EN, 0xf);
dp_pll_write(dp_ln_tx1, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
dp_pll_write(dp_ln_tx1, DP_TX_INTERFACE_MODE, 0x00);
dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
dp_pll_write(dp_ln_tx1, TXn_TX_BAND, 0x04);
/* Make sure the PHY register writes are done */
wmb();
if (pll->revision == DP_PLL_7NM)
dp_pll_config_tx_7nm(pll);
else
dp_pll_config_tx_5nm(pll);
return res;
}