mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: mfd: early init for MFD running regulators mfd: fix tmio related warnings mfd: asic3: enable SD/SDIO cell mfd: asic3: enable DS1WM cell mfd: asic3: remove SD/SDIO controller register definitions mfd: asic3: use resource_size macro instead of local variable mfd: add ASIC3 IRQ numbers mfd: asic3: add clock handling for MFD cells mfd: asic3: add asic3_set_register common operation mfd: Fix Kconfig help text for WM8350 mfd: add PCAP driver mfd: add U300 AB3100 core support drivers/mfd: remove obsolete irq_desc_t typedef mfd/pcf50633-gpio.c: add MODULE_LICENSE mfd: Mark WM8350 mask revision as readable to match silicon mfd: Mark clocks_init as non-init in twl4030-core.c mfd: Correct readability of WM8350 register 227
This commit is contained in:
Linus Torvalds
commit
55a6fbf8fc
19 changed files with 2219 additions and 238 deletions
103
include/linux/mfd/ab3100.h
Normal file
103
include/linux/mfd/ab3100.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright (C) 2007-2009 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* AB3100 core access functions
|
||||
* Author: Linus Walleij <linus.walleij@stericsson.com>
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
|
||||
#ifndef MFD_AB3100_H
|
||||
#define MFD_AB3100_H
|
||||
|
||||
#define ABUNKNOWN 0
|
||||
#define AB3000 1
|
||||
#define AB3100 2
|
||||
|
||||
/*
|
||||
* AB3100, EVENTA1, A2 and A3 event register flags
|
||||
* these are catenated into a single 32-bit flag in the code
|
||||
* for event notification broadcasts.
|
||||
*/
|
||||
#define AB3100_EVENTA1_ONSWA (0x01<<16)
|
||||
#define AB3100_EVENTA1_ONSWB (0x02<<16)
|
||||
#define AB3100_EVENTA1_ONSWC (0x04<<16)
|
||||
#define AB3100_EVENTA1_DCIO (0x08<<16)
|
||||
#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
|
||||
#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
|
||||
#define AB3100_EVENTA1_VBUS (0x40<<16)
|
||||
#define AB3100_EVENTA1_VSET_USB (0x80<<16)
|
||||
|
||||
#define AB3100_EVENTA2_READY_TX (0x01<<8)
|
||||
#define AB3100_EVENTA2_READY_RX (0x02<<8)
|
||||
#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
|
||||
#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
|
||||
#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
|
||||
#define AB3100_EVENTA2_MIDR (0x20<<8)
|
||||
#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
|
||||
#define AB3100_EVENTA2_ALARM (0x80<<8)
|
||||
|
||||
#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
|
||||
#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
|
||||
#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
|
||||
#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
|
||||
#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
|
||||
#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
|
||||
#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
|
||||
#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
|
||||
|
||||
/* AB3100, STR register flags */
|
||||
#define AB3100_STR_ONSWA (0x01)
|
||||
#define AB3100_STR_ONSWB (0x02)
|
||||
#define AB3100_STR_ONSWC (0x04)
|
||||
#define AB3100_STR_DCIO (0x08)
|
||||
#define AB3100_STR_BOOT_MODE (0x10)
|
||||
#define AB3100_STR_SIM_OFF (0x20)
|
||||
#define AB3100_STR_BATT_REMOVAL (0x40)
|
||||
#define AB3100_STR_VBUS (0x80)
|
||||
|
||||
/**
|
||||
* struct ab3100
|
||||
* @access_mutex: lock out concurrent accesses to the AB3100 registers
|
||||
* @dev: pointer to the containing device
|
||||
* @i2c_client: I2C client for this chip
|
||||
* @testreg_client: secondary client for test registers
|
||||
* @chip_name: name of this chip variant
|
||||
* @chip_id: 8 bit chip ID for this chip variant
|
||||
* @work: an event handling worker
|
||||
* @event_subscribers: event subscribers are listed here
|
||||
* @startup_events: a copy of the first reading of the event registers
|
||||
* @startup_events_read: whether the first events have been read
|
||||
*
|
||||
* This struct is PRIVATE and devices using it should NOT
|
||||
* access ANY fields. It is used as a token for calling the
|
||||
* AB3100 functions.
|
||||
*/
|
||||
struct ab3100 {
|
||||
struct mutex access_mutex;
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c_client;
|
||||
struct i2c_client *testreg_client;
|
||||
char chip_name[32];
|
||||
u8 chip_id;
|
||||
struct work_struct work;
|
||||
struct blocking_notifier_head event_subscribers;
|
||||
u32 startup_events;
|
||||
bool startup_events_read;
|
||||
};
|
||||
|
||||
int ab3100_set_register(struct ab3100 *ab3100, u8 reg, u8 regval);
|
||||
int ab3100_get_register(struct ab3100 *ab3100, u8 reg, u8 *regval);
|
||||
int ab3100_get_register_page(struct ab3100 *ab3100,
|
||||
u8 first_reg, u8 *regvals, u8 numregs);
|
||||
int ab3100_mask_and_set_register(struct ab3100 *ab3100,
|
||||
u8 reg, u8 andmask, u8 ormask);
|
||||
u8 ab3100_get_chip_type(struct ab3100 *ab3100);
|
||||
int ab3100_event_register(struct ab3100 *ab3100,
|
||||
struct notifier_block *nb);
|
||||
int ab3100_event_unregister(struct ab3100 *ab3100,
|
||||
struct notifier_block *nb);
|
||||
int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
|
||||
u32 *fatevent);
|
||||
|
||||
#endif
|
||||
|
|
@ -30,6 +30,13 @@ struct asic3_platform_data {
|
|||
#define ASIC3_NUM_GPIOS 64
|
||||
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
|
||||
|
||||
#define ASIC3_IRQ_LED0 64
|
||||
#define ASIC3_IRQ_LED1 65
|
||||
#define ASIC3_IRQ_LED2 66
|
||||
#define ASIC3_IRQ_SPI 67
|
||||
#define ASIC3_IRQ_SMBUS 68
|
||||
#define ASIC3_IRQ_OWM 69
|
||||
|
||||
#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
|
||||
|
||||
#define ASIC3_GPIO_BANK_A 0
|
||||
|
|
@ -227,8 +234,8 @@ struct asic3_platform_data {
|
|||
|
||||
|
||||
/* Basic control of the SD ASIC */
|
||||
#define ASIC3_SDHWCTRL_Base 0x0E00
|
||||
#define ASIC3_SDHWCTRL_SDConf 0x00
|
||||
#define ASIC3_SDHWCTRL_BASE 0x0E00
|
||||
#define ASIC3_SDHWCTRL_SDCONF 0x00
|
||||
|
||||
#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
|
||||
#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
|
||||
|
|
@ -242,10 +249,10 @@ struct asic3_platform_data {
|
|||
/* SD card power supply ctrl 1=enable */
|
||||
#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
|
||||
|
||||
#define ASIC3_EXTCF_Base 0x1100
|
||||
#define ASIC3_EXTCF_BASE 0x1100
|
||||
|
||||
#define ASIC3_EXTCF_Select 0x00
|
||||
#define ASIC3_EXTCF_Reset 0x04
|
||||
#define ASIC3_EXTCF_SELECT 0x00
|
||||
#define ASIC3_EXTCF_RESET 0x04
|
||||
|
||||
#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
|
||||
#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
|
||||
|
|
@ -279,222 +286,9 @@ struct asic3_platform_data {
|
|||
* SDIO_CTRL Control registers for SDIO operations
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */
|
||||
|
||||
#define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */
|
||||
|
||||
/* [0:8] SD Control Register Base Address */
|
||||
#define ASIC3_SD_CONFIG_Addr0 0x20
|
||||
|
||||
/* [9:31] SD Control Register Base Address */
|
||||
#define ASIC3_SD_CONFIG_Addr1 0x24
|
||||
|
||||
/* R/O: interrupt assigned to pin */
|
||||
#define ASIC3_SD_CONFIG_IntPin 0x78
|
||||
|
||||
/*
|
||||
* Set to 0x1f to clock SD controller, 0 otherwise.
|
||||
* At 0x82 - Gated Clock Ctrl
|
||||
*/
|
||||
#define ASIC3_SD_CONFIG_ClkStop 0x80
|
||||
|
||||
/* Control clock of SD controller */
|
||||
#define ASIC3_SD_CONFIG_ClockMode 0x84
|
||||
#define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
|
||||
#define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
|
||||
|
||||
/* auto power up after card inserted */
|
||||
#define ASIC3_SD_CONFIG_SDHC_Power2 0x92
|
||||
|
||||
/* auto power down when card removed */
|
||||
#define ASIC3_SD_CONFIG_SDHC_Power3 0x94
|
||||
#define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
|
||||
#define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
|
||||
#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
|
||||
#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
|
||||
|
||||
/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
|
||||
#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
|
||||
#define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
|
||||
|
||||
/* Bit 1: double buffer/single buffer */
|
||||
#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
|
||||
|
||||
/* Memory access enable (set to 1 to access SD Controller) */
|
||||
#define SD_CONFIG_COMMAND_MAE (1<<1)
|
||||
|
||||
#define SD_CONFIG_CLK_ENABLE_ALL 0x1f
|
||||
|
||||
#define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
|
||||
#define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
|
||||
|
||||
/* two bits - number of cycles for card detection */
|
||||
#define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
|
||||
|
||||
|
||||
#define ASIC3_SD_CTRL_Base 0x1000
|
||||
|
||||
#define ASIC3_SD_CTRL_Cmd 0x00
|
||||
#define ASIC3_SD_CTRL_Arg0 0x08
|
||||
#define ASIC3_SD_CTRL_Arg1 0x0C
|
||||
#define ASIC3_SD_CTRL_StopInternal 0x10
|
||||
#define ASIC3_SD_CTRL_TransferSectorCount 0x14
|
||||
#define ASIC3_SD_CTRL_Response0 0x18
|
||||
#define ASIC3_SD_CTRL_Response1 0x1C
|
||||
#define ASIC3_SD_CTRL_Response2 0x20
|
||||
#define ASIC3_SD_CTRL_Response3 0x24
|
||||
#define ASIC3_SD_CTRL_Response4 0x28
|
||||
#define ASIC3_SD_CTRL_Response5 0x2C
|
||||
#define ASIC3_SD_CTRL_Response6 0x30
|
||||
#define ASIC3_SD_CTRL_Response7 0x34
|
||||
#define ASIC3_SD_CTRL_CardStatus 0x38
|
||||
#define ASIC3_SD_CTRL_BufferCtrl 0x3C
|
||||
#define ASIC3_SD_CTRL_IntMaskCard 0x40
|
||||
#define ASIC3_SD_CTRL_IntMaskBuffer 0x44
|
||||
#define ASIC3_SD_CTRL_CardClockCtrl 0x48
|
||||
#define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
|
||||
#define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
|
||||
#define ASIC3_SD_CTRL_ErrorStatus0 0x58
|
||||
#define ASIC3_SD_CTRL_ErrorStatus1 0x5C
|
||||
#define ASIC3_SD_CTRL_DataPort 0x60
|
||||
#define ASIC3_SD_CTRL_TransactionCtrl 0x68
|
||||
#define ASIC3_SD_CTRL_SoftwareReset 0x1C0
|
||||
|
||||
#define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
|
||||
|
||||
#define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
|
||||
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
|
||||
#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
|
||||
|
||||
#define MEM_CARD_OPTION_REQUIRED 0x000e
|
||||
#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
|
||||
#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
|
||||
#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
|
||||
#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
|
||||
|
||||
#define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
|
||||
#define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
|
||||
#define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
|
||||
#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
|
||||
#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
|
||||
#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
|
||||
#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
|
||||
#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
|
||||
#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
|
||||
#define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
|
||||
#define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
|
||||
#define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
|
||||
#define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
|
||||
#define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
|
||||
|
||||
#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
|
||||
#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
|
||||
|
||||
#define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
|
||||
#define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
|
||||
#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
|
||||
#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
|
||||
#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
|
||||
#define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
|
||||
#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
|
||||
#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
|
||||
#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
|
||||
|
||||
#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
|
||||
#define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
|
||||
#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
|
||||
#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
|
||||
#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
|
||||
#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
|
||||
#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
|
||||
#define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
|
||||
#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
|
||||
#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
|
||||
#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
|
||||
#define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
|
||||
#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
|
||||
|
||||
#define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
|
||||
#define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
|
||||
#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
|
||||
#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
|
||||
#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
|
||||
#define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
|
||||
#define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
|
||||
#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
|
||||
#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
|
||||
#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
|
||||
|
||||
#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
|
||||
#define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
|
||||
#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
|
||||
#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
|
||||
#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
|
||||
#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
|
||||
#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
|
||||
#define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
|
||||
#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
|
||||
#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
|
||||
#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
|
||||
#define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
|
||||
#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
|
||||
|
||||
#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
|
||||
#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
|
||||
#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
|
||||
#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
|
||||
#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
|
||||
#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
|
||||
#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
|
||||
#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
|
||||
#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
|
||||
|
||||
#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
|
||||
#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
|
||||
#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
|
||||
#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
|
||||
|
||||
#define ASIC3_SDIO_CTRL_Base 0x1200
|
||||
|
||||
#define ASIC3_SDIO_CTRL_Cmd 0x00
|
||||
#define ASIC3_SDIO_CTRL_CardPortSel 0x04
|
||||
#define ASIC3_SDIO_CTRL_Arg0 0x08
|
||||
#define ASIC3_SDIO_CTRL_Arg1 0x0C
|
||||
#define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
|
||||
#define ASIC3_SDIO_CTRL_Response0 0x18
|
||||
#define ASIC3_SDIO_CTRL_Response1 0x1C
|
||||
#define ASIC3_SDIO_CTRL_Response2 0x20
|
||||
#define ASIC3_SDIO_CTRL_Response3 0x24
|
||||
#define ASIC3_SDIO_CTRL_Response4 0x28
|
||||
#define ASIC3_SDIO_CTRL_Response5 0x2C
|
||||
#define ASIC3_SDIO_CTRL_Response6 0x30
|
||||
#define ASIC3_SDIO_CTRL_Response7 0x34
|
||||
#define ASIC3_SDIO_CTRL_CardStatus 0x38
|
||||
#define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
|
||||
#define ASIC3_SDIO_CTRL_IntMaskCard 0x40
|
||||
#define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
|
||||
#define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
|
||||
#define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
|
||||
#define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
|
||||
#define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
|
||||
#define ASIC3_SDIO_CTRL_DataPort 0x60
|
||||
#define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
|
||||
#define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
|
||||
#define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
|
||||
#define ASIC3_SDIO_CTRL_HostInformation 0x74
|
||||
#define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
|
||||
#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
|
||||
#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
|
||||
#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
|
||||
#define ASIC3_SD_CTRL_BASE 0x1000
|
||||
#define ASIC3_SDIO_CTRL_BASE 0x1200
|
||||
|
||||
#define ASIC3_MAP_SIZE_32BIT 0x2000
|
||||
#define ASIC3_MAP_SIZE_16BIT 0x1000
|
||||
|
|
|
|||
256
include/linux/mfd/ezx-pcap.h
Normal file
256
include/linux/mfd/ezx-pcap.h
Normal file
|
|
@ -0,0 +1,256 @@
|
|||
/*
|
||||
* Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
|
||||
*
|
||||
* For further information, please see http://wiki.openezx.org/PCAP2
|
||||
*/
|
||||
|
||||
#ifndef EZX_PCAP_H
|
||||
#define EZX_PCAP_H
|
||||
|
||||
struct pcap_subdev {
|
||||
int id;
|
||||
const char *name;
|
||||
void *platform_data;
|
||||
};
|
||||
|
||||
struct pcap_platform_data {
|
||||
unsigned int irq_base;
|
||||
unsigned int config;
|
||||
void (*init) (void *); /* board specific init */
|
||||
int num_subdevs;
|
||||
struct pcap_subdev *subdevs;
|
||||
};
|
||||
|
||||
struct pcap_chip;
|
||||
|
||||
int ezx_pcap_write(struct pcap_chip *, u8, u32);
|
||||
int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
|
||||
int pcap_to_irq(struct pcap_chip *, int);
|
||||
int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
|
||||
int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
|
||||
|
||||
#define PCAP_SECOND_PORT 1
|
||||
#define PCAP_CS_AH 2
|
||||
|
||||
#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
|
||||
#define PCAP_REGISTER_READ_OP_BIT 0x00000000
|
||||
|
||||
#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
|
||||
#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
|
||||
#define PCAP_REGISTER_ADDRESS_SHIFT 26
|
||||
#define PCAP_REGISTER_NUMBER 32
|
||||
#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
|
||||
#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
|
||||
|
||||
/* registers acessible by both pcap ports */
|
||||
#define PCAP_REG_ISR 0x0 /* Interrupt Status */
|
||||
#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
|
||||
#define PCAP_REG_PSTAT 0x2 /* Processor Status */
|
||||
#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
|
||||
#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
|
||||
#define PCAP_REG_BATT 0x8 /* Battery Control */
|
||||
#define PCAP_REG_ADC 0x9 /* AD Control */
|
||||
#define PCAP_REG_ADR 0xa /* AD Result */
|
||||
#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
|
||||
#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
|
||||
#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
|
||||
#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
|
||||
#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
|
||||
#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
|
||||
#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
|
||||
#define PCAP_REG_GP 0x1b /* General Purpose */
|
||||
#define PCAP_REG_TEST1 0x1c
|
||||
#define PCAP_REG_TEST2 0x1d
|
||||
#define PCAP_REG_VENDOR_TEST1 0x1e
|
||||
#define PCAP_REG_VENDOR_TEST2 0x1f
|
||||
|
||||
/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
|
||||
#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
|
||||
#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
|
||||
#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
|
||||
#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
|
||||
#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
|
||||
#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
|
||||
#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
|
||||
#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
|
||||
#define PCAP_REG_PWR 0x13 /* Power Control */
|
||||
#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
|
||||
#define PCAP_REG_VENDOR_REV 0x17
|
||||
#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
|
||||
|
||||
/* PCAP2 Interrupts */
|
||||
#define PCAP_NIRQS 23
|
||||
#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
|
||||
#define PCAP_IRQ_TS 1 /* Touch Screen */
|
||||
#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
|
||||
#define PCAP_IRQ_WH 3 /* ADC above high limit */
|
||||
#define PCAP_IRQ_WL 4 /* ADC below low limit */
|
||||
#define PCAP_IRQ_TODA 5 /* Time of day alarm */
|
||||
#define PCAP_IRQ_USB4V 6 /* USB above 4V */
|
||||
#define PCAP_IRQ_ONOFF 7 /* On/Off button */
|
||||
#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
|
||||
#define PCAP_IRQ_USB1V 9 /* USB above 1V */
|
||||
#define PCAP_IRQ_MOBPORT 10
|
||||
#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
|
||||
#define PCAP_IRQ_HS 12 /* Headset attach */
|
||||
#define PCAP_IRQ_ST 13
|
||||
#define PCAP_IRQ_PC 14 /* Power Cut */
|
||||
#define PCAP_IRQ_WARM 15
|
||||
#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
|
||||
#define PCAP_IRQ_CLK 17
|
||||
#define PCAP_IRQ_SYSRST 18 /* System Reset */
|
||||
#define PCAP_IRQ_DUMMY 19
|
||||
#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
|
||||
#define PCAP_IRQ_SOFTRESET 21
|
||||
#define PCAP_IRQ_MNEXB 22
|
||||
|
||||
/* voltage regulators */
|
||||
#define V1 0
|
||||
#define V2 1
|
||||
#define V3 2
|
||||
#define V4 3
|
||||
#define V5 4
|
||||
#define V6 5
|
||||
#define V7 6
|
||||
#define V8 7
|
||||
#define V9 8
|
||||
#define V10 9
|
||||
#define VAUX1 10
|
||||
#define VAUX2 11
|
||||
#define VAUX3 12
|
||||
#define VAUX4 13
|
||||
#define VSIM 14
|
||||
#define VSIM2 15
|
||||
#define VVIB 16
|
||||
#define SW1 17
|
||||
#define SW2 18
|
||||
#define SW3 19
|
||||
#define SW1S 20
|
||||
#define SW2S 21
|
||||
|
||||
#define PCAP_BATT_DAC_MASK 0x000000ff
|
||||
#define PCAP_BATT_DAC_SHIFT 0
|
||||
#define PCAP_BATT_B_FDBK (1 << 8)
|
||||
#define PCAP_BATT_EXT_ISENSE (1 << 9)
|
||||
#define PCAP_BATT_V_COIN_MASK 0x00003c00
|
||||
#define PCAP_BATT_V_COIN_SHIFT 10
|
||||
#define PCAP_BATT_I_COIN (1 << 14)
|
||||
#define PCAP_BATT_COIN_CH_EN (1 << 15)
|
||||
#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
|
||||
#define PCAP_BATT_EOL_SEL_SHIFT 17
|
||||
#define PCAP_BATT_EOL_CMP_EN (1 << 20)
|
||||
#define PCAP_BATT_BATT_DET_EN (1 << 21)
|
||||
#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
|
||||
|
||||
#define PCAP_ADC_ADEN (1 << 0)
|
||||
#define PCAP_ADC_RAND (1 << 1)
|
||||
#define PCAP_ADC_AD_SEL1 (1 << 2)
|
||||
#define PCAP_ADC_AD_SEL2 (1 << 3)
|
||||
#define PCAP_ADC_ADA1_MASK 0x00000070
|
||||
#define PCAP_ADC_ADA1_SHIFT 4
|
||||
#define PCAP_ADC_ADA2_MASK 0x00000380
|
||||
#define PCAP_ADC_ADA2_SHIFT 7
|
||||
#define PCAP_ADC_ATO_MASK 0x00003c00
|
||||
#define PCAP_ADC_ATO_SHIFT 10
|
||||
#define PCAP_ADC_ATOX (1 << 14)
|
||||
#define PCAP_ADC_MTR1 (1 << 15)
|
||||
#define PCAP_ADC_MTR2 (1 << 16)
|
||||
#define PCAP_ADC_TS_M_MASK 0x000e0000
|
||||
#define PCAP_ADC_TS_M_SHIFT 17
|
||||
#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
|
||||
#define PCAP_ADC_TS_REFENB (1 << 21)
|
||||
#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
|
||||
#define PCAP_ADC_BATT_I_ADC (1 << 23)
|
||||
|
||||
#define PCAP_ADC_BANK_0 0
|
||||
#define PCAP_ADC_BANK_1 1
|
||||
/* ADC bank 0 */
|
||||
#define PCAP_ADC_CH_COIN 0
|
||||
#define PCAP_ADC_CH_BATT 1
|
||||
#define PCAP_ADC_CH_BPLUS 2
|
||||
#define PCAP_ADC_CH_MOBPORTB 3
|
||||
#define PCAP_ADC_CH_TEMPERATURE 4
|
||||
#define PCAP_ADC_CH_CHARGER_ID 5
|
||||
#define PCAP_ADC_CH_AD6 6
|
||||
/* ADC bank 1 */
|
||||
#define PCAP_ADC_CH_AD7 0
|
||||
#define PCAP_ADC_CH_AD8 1
|
||||
#define PCAP_ADC_CH_AD9 2
|
||||
#define PCAP_ADC_CH_TS_X1 3
|
||||
#define PCAP_ADC_CH_TS_X2 4
|
||||
#define PCAP_ADC_CH_TS_Y1 5
|
||||
#define PCAP_ADC_CH_TS_Y2 6
|
||||
|
||||
#define PCAP_ADC_T_NOW 0
|
||||
#define PCAP_ADC_T_IN_BURST 1
|
||||
#define PCAP_ADC_T_OUT_BURST 2
|
||||
|
||||
#define PCAP_ADC_ATO_IN_BURST 6
|
||||
#define PCAP_ADC_ATO_OUT_BURST 0
|
||||
|
||||
#define PCAP_ADC_TS_M_XY 1
|
||||
#define PCAP_ADC_TS_M_PRESSURE 2
|
||||
#define PCAP_ADC_TS_M_PLATE_X 3
|
||||
#define PCAP_ADC_TS_M_PLATE_Y 4
|
||||
#define PCAP_ADC_TS_M_STANDBY 5
|
||||
#define PCAP_ADC_TS_M_NONTS 6
|
||||
|
||||
#define PCAP_ADR_ADD1_MASK 0x000003ff
|
||||
#define PCAP_ADR_ADD1_SHIFT 0
|
||||
#define PCAP_ADR_ADD2_MASK 0x000ffc00
|
||||
#define PCAP_ADR_ADD2_SHIFT 10
|
||||
#define PCAP_ADR_ADINC1 (1 << 20)
|
||||
#define PCAP_ADR_ADINC2 (1 << 21)
|
||||
#define PCAP_ADR_ASC (1 << 22)
|
||||
#define PCAP_ADR_ONESHOT (1 << 23)
|
||||
|
||||
#define PCAP_BUSCTRL_FSENB (1 << 0)
|
||||
#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
|
||||
#define PCAP_BUSCTRL_USB_PU (1 << 2)
|
||||
#define PCAP_BUSCTRL_USB_PD (1 << 3)
|
||||
#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
|
||||
#define PCAP_BUSCTRL_USB_PS (1 << 5)
|
||||
#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
|
||||
#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
|
||||
#define PCAP_BUSCTRL_CURRLIM (1 << 8)
|
||||
#define PCAP_BUSCTRL_RS232ENB (1 << 9)
|
||||
#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
|
||||
#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
|
||||
#define PCAP_BUSCTRL_USB_PDM (1 << 12)
|
||||
#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
|
||||
|
||||
/* leds */
|
||||
#define PCAP_LED0 0
|
||||
#define PCAP_LED1 1
|
||||
#define PCAP_BL0 2
|
||||
#define PCAP_BL1 3
|
||||
#define PCAP_VIB 4
|
||||
#define PCAP_LED_3MA 0
|
||||
#define PCAP_LED_4MA 1
|
||||
#define PCAP_LED_5MA 2
|
||||
#define PCAP_LED_9MA 3
|
||||
#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
|
||||
#define PCAP_LED_GPIO_EN 0x01000000
|
||||
#define PCAP_LED_GPIO_INVERT 0x02000000
|
||||
#define PCAP_LED_T_MASK 0xf
|
||||
#define PCAP_LED_C_MASK 0x3
|
||||
#define PCAP_BL_MASK 0x1f
|
||||
#define PCAP_BL0_SHIFT 0
|
||||
#define PCAP_LED0_EN (1 << 5)
|
||||
#define PCAP_LED1_EN (1 << 6)
|
||||
#define PCAP_LED0_T_SHIFT 7
|
||||
#define PCAP_LED1_T_SHIFT 11
|
||||
#define PCAP_LED0_C_SHIFT 15
|
||||
#define PCAP_LED1_C_SHIFT 17
|
||||
#define PCAP_BL1_SHIFT 20
|
||||
#define PCAP_VIB_MASK 0x3
|
||||
#define PCAP_VIB_SHIFT 20
|
||||
#define PCAP_VIB_EN (1 << 19)
|
||||
|
||||
/* RTC */
|
||||
#define PCAP_RTC_DAY_MASK 0x3fff
|
||||
#define PCAP_RTC_TOD_MASK 0xffff
|
||||
#define PCAP_RTC_PC_MASK 0x7
|
||||
#define SEC_PER_DAY 86400
|
||||
|
||||
#endif
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
* data for the MMC controller
|
||||
*/
|
||||
struct tmio_mmc_data {
|
||||
unsigned int hclk;
|
||||
const unsigned int hclk;
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue