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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge "interconnect: qcom: Add QoS config support for BIMC masters"
This commit is contained in:
commit
55ab5d8dd6
4 changed files with 114 additions and 3 deletions
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@ -15,6 +15,7 @@
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#include <linux/soc/qcom/smd-rpm.h>
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#include "icc-rpm.h"
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#include "qnoc-qos.h"
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static int qcom_icc_rpm_smd_send_msg(int ctx, int rsc_type, int rpm_id, u64 val)
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{
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@ -77,6 +78,9 @@ int qcom_icc_rpm_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
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}
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}
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*agg_avg += avg_bw;
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*agg_peak = max_t(u32, *agg_peak, peak_bw);
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qn->dirty = true;
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return 0;
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@ -209,6 +213,22 @@ int qcom_icc_rpm_set(struct icc_node *src, struct icc_node *dst)
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}
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}
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qn = node->data;
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/* Defer setting QoS until the first non-zero bandwidth request. */
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if (qn && qn->qosbox && !qn->qosbox->initialized &&
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(node->avg_bw || node->peak_bw)) {
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ret = clk_bulk_prepare_enable(qp->num_qos_clks, qp->qos_clks);
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if (ret) {
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pr_err("%s: Clock enable failed for node %s\n",
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__func__, node->name);
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return ret;
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}
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qn->noc_ops->set_qos(qn);
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clk_bulk_disable_unprepare(qp->num_qos_clks, qp->qos_clks);
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qn->qosbox->initialized = true;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(qcom_icc_rpm_set);
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@ -46,6 +46,8 @@ enum qcom_icc_rpm_context {
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* struct qcom_icc_provider - QTI specific interconnect provider
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* @provider: generic interconnect provider
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* @dev: reference to the NoC device
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* @qos_clks: the clk_bulk_data table of QoS clocks
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* @num_qos_clks: the total number of clk_bulk_data entries
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* @bus_clks: the clk_bulk_data table of bus clocks
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* @num_clks: the total number of clk_bulk_data entries
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* @bus_clk_cur_rate: current frequency of bus clock
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@ -57,6 +59,8 @@ struct qcom_icc_provider {
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struct device *dev;
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struct regmap *regmap;
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struct list_head probe_list;
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struct clk_bulk_data *qos_clks;
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int num_qos_clks;
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struct clk_bulk_data *bus_clks;
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int num_clks;
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u32 util_factor;
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@ -8,7 +8,11 @@
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#include <linux/interconnect-provider.h>
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#include <linux/module.h>
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#ifdef CONFIG_INTERCONNECT_QCOM_RPMH
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#include "icc-rpmh.h"
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#else
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#include "icc-rpm.h"
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#endif
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#include "qnoc-qos.h"
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#define QOSGEN_MAINCTL_LO(p, qp) ((p)->offsets[qp] + \
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@ -17,6 +21,23 @@
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# define QOS_DFLT_PRIO_MASK 0x7
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# define QOS_DFLT_PRIO_SHFT 4
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#ifndef CONFIG_INTERCONNECT_QCOM_RPMH
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#define QOSGEN_M_BKE_HEALTH(p, qp, n) ((p)->offsets[qp] + ((n) * 4) + \
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(p)->regs[QOSGEN_OFF_MPORT_BKE_HEALTH])
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#define QOS_PRIOLVL_MASK 0x7
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#define QOS_PRIOLVL_SHFT 0x0
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#define QOS_AREQPRIO_MASK 0x70
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#define QOS_AREQPRIO_SHFT 0x8
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#define QOSGEN_M_BKE_EN(p, qp) ((p)->offsets[qp] + \
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(p)->regs[QOSGEN_OFF_MPORT_BKE_EN])
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#define QOS_BKE_EN_MASK 0x1
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#define QOS_BKE_EN_SHFT 0x0
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#define NUM_BKE_HEALTH_LEVELS 4
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#endif
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const u8 icc_qnoc_qos_regs[][QOSGEN_OFF_MAX_REGS] = {
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[ICC_QNOC_QOSGEN_TYPE_RPMH] = {
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[QOSGEN_OFF_MAINCTL_LO] = 0x8,
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@ -29,6 +50,15 @@ const u8 icc_qnoc_qos_regs[][QOSGEN_OFF_MAX_REGS] = {
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};
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EXPORT_SYMBOL(icc_qnoc_qos_regs);
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#ifndef CONFIG_INTERCONNECT_QCOM_RPMH
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const u8 icc_bimc_qos_regs[][QOSGEN_OFF_MAX_REGS] = {
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[ICC_QNOC_QOSGEN_TYPE_RPMH] = {
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[QOSGEN_OFF_MPORT_BKE_EN] = 0x0,
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[QOSGEN_OFF_MPORT_BKE_HEALTH] = 0x40,
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},
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};
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EXPORT_SYMBOL(icc_bimc_qos_regs);
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#endif
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/**
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* qcom_icc_set_qos - initialize static QoS configurations
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* @node: qcom icc node to operate on
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@ -49,11 +79,16 @@ static void qcom_icc_set_qos(struct qcom_icc_node *node)
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QOS_DFLT_PRIO_MASK << QOS_DFLT_PRIO_SHFT,
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qos->config->prio << QOS_DFLT_PRIO_SHFT);
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if (qos->config->urg_fwd)
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regmap_update_bits(node->regmap,
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QOSGEN_MAINCTL_LO(qos, port),
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QOS_SLV_URG_MSG_EN,
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QOS_SLV_URG_MSG_EN);
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QOSGEN_MAINCTL_LO(qos, port),
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QOS_SLV_URG_MSG_EN,
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QOS_SLV_URG_MSG_EN);
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else
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regmap_update_bits(node->regmap,
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QOSGEN_MAINCTL_LO(qos, port),
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QOS_SLV_URG_MSG_EN, 0x0);
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}
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}
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@ -62,4 +97,42 @@ const struct qcom_icc_noc_ops qcom_qnoc4_ops = {
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};
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EXPORT_SYMBOL(qcom_qnoc4_ops);
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#ifndef CONFIG_INTERCONNECT_QCOM_RPMH
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/**
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* qcom_icc_set_bimc_qos - initialize static QoS configurations
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* @node: qcom icc node to operate on
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*/
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static void qcom_icc_set_bimc_qos(struct qcom_icc_node *node)
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{
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struct qcom_icc_qosbox *qos = node->qosbox;
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int port, i;
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if (!node->regmap)
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return;
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if (!qos)
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return;
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for (port = 0; port < qos->num_ports; port++) {
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for (i = 0; i < NUM_BKE_HEALTH_LEVELS; i++) {
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regmap_update_bits(node->regmap,
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QOSGEN_M_BKE_HEALTH(qos, port, i),
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((qos->config->prio << QOS_PRIOLVL_SHFT) |
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(qos->config->prio << QOS_AREQPRIO_SHFT)),
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(QOS_PRIOLVL_MASK | QOS_AREQPRIO_MASK));
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};
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regmap_update_bits(node->regmap,
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QOSGEN_M_BKE_EN(qos, port),
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qos->config->bke_enable << QOS_BKE_EN_SHFT,
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QOS_BKE_EN_MASK);
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};
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}
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const struct qcom_icc_noc_ops qcom_bimc_ops = {
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.set_qos = qcom_icc_set_bimc_qos,
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};
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EXPORT_SYMBOL(qcom_bimc_ops);
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#endif
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MODULE_LICENSE("GPL v2");
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@ -23,6 +23,14 @@ enum {
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QOSGEN_OFF_REGUL0BW_LO,
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};
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#ifndef CONFIG_INTERCONNECT_QCOM_RPMH
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enum {
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QOSGEN_OFF_MPORT_BKE_HEALTH,
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QOSGEN_OFF_MPORT_BKE_EN,
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};
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extern const u8 icc_bimc_qos_regs[ICC_QNOC_QOS_MAX_TYPE][QOSGEN_OFF_MAX_REGS];
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#endif
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extern const u8 icc_qnoc_qos_regs[ICC_QNOC_QOS_MAX_TYPE][QOSGEN_OFF_MAX_REGS];
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struct qcom_icc_noc_ops {
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@ -32,6 +40,9 @@ struct qcom_icc_noc_ops {
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struct qos_config {
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u32 prio;
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u32 urg_fwd;
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#ifndef CONFIG_INTERCONNECT_QCOM_RPMH
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u32 bke_enable;
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#endif
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};
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struct qcom_icc_qosbox {
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@ -55,5 +66,8 @@ struct qcom_icc_qosbox {
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} \
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extern const struct qcom_icc_noc_ops qcom_qnoc4_ops;
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#ifndef CONFIG_INTERCONNECT_QCOM_RPMH
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extern const struct qcom_icc_noc_ops qcom_bimc_ops;
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#endif
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#endif
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