mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 19:51:31 -04:00
soc/tegra: Core SoC changes for v4.12-rc1
This contains PMC support for Tegra186 as well as a proper driver for the flow controller found on SoCs up to Tegra210. This also turns the fuse driver into an explicitly non-modular driver. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljmx1ITHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoWt2D/9hNQqNgxW+6QOq3EuxWHDPs6hWOHRy v13TM7cQg7Qc6zXnmc+SzEp5eT7+GbNNgtrQ7ukfzKPeDwbPXf+NwsprS+STayvF dxqtcem/6tID3WJxzYJRJY3d8hH3BCvQhJf+uF8V2za1F/f4f6mHDtUboPVO2LIa L4IdtXQEwoVyPdnH2GDdKG6uOHnufBLVsS+DFXWeuY/nPiTgFcBQAgOuNwFZK1/V FisKON2QIg0yh6Y7UjDGh5X9ODR2OC+9g1kGV7hY3tlvz/JovZxc8CPnQsPg2QR7 1heGwNTHEOkAeClvRdAr+guV1wDvY4vA+2U1XeQeSLg3gq4lIfRKp8+xrwfnkyS+ rmllTA/85LCiTO9slKoSdv6vSSgb7K549z/dYdIqwDTPU0GE1xzFF4DTvs2OwmtF y4ziCDM+6H1EgesZDcVZikVFjof+q8h2j1FEsloe6HjmhcJ42lQWRLFbEPk1XMec cWNynVMjRxaQP/8cJTHYpnpa6e6/Eqv1GhWYWl+9yqodJhBJtrzPZLaGKfYiaG2R QcG48WsBGDtV5zYKUEG5/LKNWaFvcAjhfi9JXh44FMBlBNZ+EyWThJPTvL06glk4 SKaBx69Ft5fOHlIQG9/lT+u0RmLmmMkSNHeW/Zh9s08xeJhK3lHLnpT8s6kDxui5 Nhid59CnZh8SnQ== =n4aM -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers soc/tegra: Core SoC changes for v4.12-rc1 This contains PMC support for Tegra186 as well as a proper driver for the flow controller found on SoCs up to Tegra210. This also turns the fuse driver into an explicitly non-modular driver. * tag 'tegra-for-4.12-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header soc: tegra: make fuse-tegra explicitly non-modular soc/tegra: Fix link errors with PMC disabled soc/tegra: Implement Tegra186 PMC support Signed-off-by: Olof Johansson <[email protected]>
This commit is contained in:
Olof Johansson
commit
55de807595
17 changed files with 353 additions and 47 deletions
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@ -12,6 +12,8 @@ config ARCH_TEGRA_2x_SOC
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select PINCTRL_TEGRA20
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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@ -23,6 +25,8 @@ config ARCH_TEGRA_3x_SOC
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select ARM_ERRATA_764369 if SMP
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select PINCTRL_TEGRA30
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select PL310_ERRATA_769419 if CACHE_L2X0
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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@ -33,6 +37,8 @@ config ARCH_TEGRA_114_SOC
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select ARM_ERRATA_798181 if SMP
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA114
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T114 processor family, based on the
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@ -42,6 +48,8 @@ config ARCH_TEGRA_124_SOC
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bool "Enable support for Tegra124 family"
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select HAVE_ARM_ARCH_TIMER
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select PINCTRL_TEGRA124
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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select TEGRA_TIMER
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help
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Support for NVIDIA Tegra T124 processor family, based on the
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@ -55,6 +63,8 @@ if ARM64
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config ARCH_TEGRA_132_SOC
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bool "NVIDIA Tegra132 SoC"
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select PINCTRL_TEGRA124
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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help
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Enable support for NVIDIA Tegra132 SoC, based on the Denver
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ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
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@ -64,6 +74,8 @@ config ARCH_TEGRA_132_SOC
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config ARCH_TEGRA_210_SOC
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bool "NVIDIA Tegra210 SoC"
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select PINCTRL_TEGRA210
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select SOC_TEGRA_FLOWCTRL
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select SOC_TEGRA_PMC
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help
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Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
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the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
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@ -83,6 +95,7 @@ config ARCH_TEGRA_186_SOC
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select TEGRA_BPMP
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select TEGRA_HSP_MBOX
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select TEGRA_IVC
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select SOC_TEGRA_PMC_TEGRA186
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help
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Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
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combination of Denver and Cortex-A57 CPU cores and a GPU based on
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@ -93,3 +106,12 @@ config ARCH_TEGRA_186_SOC
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endif
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endif
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config SOC_TEGRA_FLOWCTRL
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bool
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config SOC_TEGRA_PMC
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bool
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config SOC_TEGRA_PMC_TEGRA186
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bool
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@ -1,4 +1,6 @@
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obj-y += fuse/
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obj-y += common.o
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obj-y += pmc.o
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obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o
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obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
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obj-$(CONFIG_SOC_TEGRA_PMC_TEGRA186) += pmc-tegra186.o
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224
drivers/soc/tegra/flowctrl.c
Normal file
224
drivers/soc/tegra/flowctrl.c
Normal file
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@ -0,0 +1,224 @@
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/*
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* drivers/soc/tegra/flowctrl.c
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*
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* Functions and macros to control the flowcontroller
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*
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/common.h>
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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static u8 flowctrl_offset_halt_cpu[] = {
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FLOW_CTRL_HALT_CPU0_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS,
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FLOW_CTRL_HALT_CPU1_EVENTS + 8,
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FLOW_CTRL_HALT_CPU1_EVENTS + 16,
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};
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static u8 flowctrl_offset_cpu_csr[] = {
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FLOW_CTRL_CPU0_CSR,
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FLOW_CTRL_CPU1_CSR,
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FLOW_CTRL_CPU1_CSR + 8,
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FLOW_CTRL_CPU1_CSR + 16,
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};
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static void __iomem *tegra_flowctrl_base;
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static void flowctrl_update(u8 offset, u32 value)
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{
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if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base),
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"Tegra flowctrl not initialised!\n"))
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return;
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writel(value, tegra_flowctrl_base + offset);
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/* ensure the update has reached the flow controller */
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wmb();
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readl_relaxed(tegra_flowctrl_base + offset);
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}
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u32 flowctrl_read_cpu_csr(unsigned int cpuid)
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{
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u8 offset = flowctrl_offset_cpu_csr[cpuid];
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if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base),
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"Tegra flowctrl not initialised!\n"))
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return 0;
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return readl(tegra_flowctrl_base + offset);
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}
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void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
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{
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return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
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}
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void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
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{
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return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
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}
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void flowctrl_cpu_suspend_enter(unsigned int cpuid)
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{
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unsigned int reg;
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int i;
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reg = flowctrl_read_cpu_csr(cpuid);
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfe */
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reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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/* pwr gating on wfi */
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reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
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break;
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}
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
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reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
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flowctrl_write_cpu_csr(cpuid, reg);
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for (i = 0; i < num_possible_cpus(); i++) {
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if (i == cpuid)
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continue;
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reg = flowctrl_read_cpu_csr(i);
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reg |= FLOW_CTRL_CSR_EVENT_FLAG;
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reg |= FLOW_CTRL_CSR_INTR_FLAG;
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flowctrl_write_cpu_csr(i, reg);
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}
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}
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void flowctrl_cpu_suspend_exit(unsigned int cpuid)
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{
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unsigned int reg;
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/* Disable powergating via flow controller for CPU0 */
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reg = flowctrl_read_cpu_csr(cpuid);
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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/* clear wfe bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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/* clear wfe bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
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/* clear wfi bitmap */
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reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
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break;
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}
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reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
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reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
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reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
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flowctrl_write_cpu_csr(cpuid, reg);
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}
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static int tegra_flowctrl_probe(struct platform_device *pdev)
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{
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void __iomem *base = tegra_flowctrl_base;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tegra_flowctrl_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(tegra_flowctrl_base))
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return PTR_ERR(base);
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iounmap(base);
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return 0;
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}
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static const struct of_device_id tegra_flowctrl_match[] = {
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{ .compatible = "nvidia,tegra210-flowctrl" },
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{ .compatible = "nvidia,tegra124-flowctrl" },
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{ .compatible = "nvidia,tegra114-flowctrl" },
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{ .compatible = "nvidia,tegra30-flowctrl" },
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{ .compatible = "nvidia,tegra20-flowctrl" },
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{ }
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};
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static struct platform_driver tegra_flowctrl_driver = {
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.driver = {
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.name = "tegra-flowctrl",
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.suppress_bind_attrs = true,
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.of_match_table = tegra_flowctrl_match,
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},
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.probe = tegra_flowctrl_probe,
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};
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builtin_platform_driver(tegra_flowctrl_driver);
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static int __init tegra_flowctrl_init(void)
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{
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struct resource res;
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struct device_node *np;
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if (!soc_is_tegra())
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return 0;
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np = of_find_matching_node(NULL, tegra_flowctrl_match);
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if (np) {
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if (of_address_to_resource(np, 0, &res) < 0) {
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pr_err("failed to get flowctrl register\n");
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return -ENXIO;
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}
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of_node_put(np);
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} else if (IS_ENABLED(CONFIG_ARM)) {
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/*
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* Hardcoded fallback for 32-bit Tegra
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* devices if device tree node is missing.
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*/
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res.start = 0x60007000;
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res.end = 0x60007fff;
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res.flags = IORESOURCE_MEM;
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} else {
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/*
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* At this point we're running on a Tegra,
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* that doesn't support the flow controller
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* (eg. Tegra186), so just return.
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*/
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return 0;
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}
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tegra_flowctrl_base = ioremap_nocache(res.start, resource_size(&res));
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if (!tegra_flowctrl_base)
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return -ENXIO;
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return 0;
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}
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early_initcall(tegra_flowctrl_init);
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@ -18,7 +18,7 @@
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/kobject.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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@ -168,7 +168,7 @@ static struct platform_driver tegra_fuse_driver = {
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},
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.probe = tegra_fuse_probe,
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};
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module_platform_driver(tegra_fuse_driver);
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builtin_platform_driver(tegra_fuse_driver);
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||||
|
||||
bool __init tegra_fuse_read_spare(unsigned int spare)
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{
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169
drivers/soc/tegra/pmc-tegra186.c
Normal file
169
drivers/soc/tegra/pmc-tegra186.c
Normal file
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@ -0,0 +1,169 @@
|
|||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "tegra-pmc: " fmt
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
|
||||
#define PMC_CNTRL 0x000
|
||||
#define PMC_CNTRL_MAIN_RST BIT(4)
|
||||
|
||||
#define PMC_RST_STATUS 0x070
|
||||
|
||||
#define WAKE_AOWAKE_CTRL 0x4f4
|
||||
#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
|
||||
|
||||
#define SCRATCH_SCRATCH0 0x2000
|
||||
#define SCRATCH_SCRATCH0_MODE_RECOVERY BIT(31)
|
||||
#define SCRATCH_SCRATCH0_MODE_BOOTLOADER BIT(30)
|
||||
#define SCRATCH_SCRATCH0_MODE_RCM BIT(1)
|
||||
#define SCRATCH_SCRATCH0_MODE_MASK (SCRATCH_SCRATCH0_MODE_RECOVERY | \
|
||||
SCRATCH_SCRATCH0_MODE_BOOTLOADER | \
|
||||
SCRATCH_SCRATCH0_MODE_RCM)
|
||||
|
||||
struct tegra_pmc {
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
void __iomem *wake;
|
||||
void __iomem *aotag;
|
||||
void __iomem *scratch;
|
||||
|
||||
void (*system_restart)(enum reboot_mode mode, const char *cmd);
|
||||
struct notifier_block restart;
|
||||
};
|
||||
|
||||
static int tegra186_pmc_restart_notify(struct notifier_block *nb,
|
||||
unsigned long action,
|
||||
void *data)
|
||||
{
|
||||
struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, restart);
|
||||
const char *cmd = data;
|
||||
u32 value;
|
||||
|
||||
value = readl(pmc->scratch + SCRATCH_SCRATCH0);
|
||||
value &= ~SCRATCH_SCRATCH0_MODE_MASK;
|
||||
|
||||
if (cmd) {
|
||||
if (strcmp(cmd, "recovery") == 0)
|
||||
value |= SCRATCH_SCRATCH0_MODE_RECOVERY;
|
||||
|
||||
if (strcmp(cmd, "bootloader") == 0)
|
||||
value |= SCRATCH_SCRATCH0_MODE_BOOTLOADER;
|
||||
|
||||
if (strcmp(cmd, "forced-recovery") == 0)
|
||||
value |= SCRATCH_SCRATCH0_MODE_RCM;
|
||||
}
|
||||
|
||||
writel(value, pmc->scratch + SCRATCH_SCRATCH0);
|
||||
|
||||
/*
|
||||
* If available, call the system restart implementation that was
|
||||
* registered earlier (typically PSCI).
|
||||
*/
|
||||
if (pmc->system_restart) {
|
||||
pmc->system_restart(reboot_mode, cmd);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
/* reset everything but SCRATCH0_SCRATCH0 and PMC_RST_STATUS */
|
||||
value = readl(pmc->regs + PMC_CNTRL);
|
||||
value |= PMC_CNTRL_MAIN_RST;
|
||||
writel(value, pmc->regs + PMC_CNTRL);
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static int tegra186_pmc_setup(struct tegra_pmc *pmc)
|
||||
{
|
||||
struct device_node *np = pmc->dev->of_node;
|
||||
bool invert;
|
||||
u32 value;
|
||||
|
||||
invert = of_property_read_bool(np, "nvidia,invert-interrupt");
|
||||
|
||||
value = readl(pmc->wake + WAKE_AOWAKE_CTRL);
|
||||
|
||||
if (invert)
|
||||
value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
|
||||
else
|
||||
value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
|
||||
|
||||
writel(value, pmc->wake + WAKE_AOWAKE_CTRL);
|
||||
|
||||
/*
|
||||
* We need to hook any system restart implementation registered
|
||||
* previously so we can write SCRATCH_SCRATCH0 before reset.
|
||||
*/
|
||||
pmc->system_restart = arm_pm_restart;
|
||||
arm_pm_restart = NULL;
|
||||
|
||||
pmc->restart.notifier_call = tegra186_pmc_restart_notify;
|
||||
pmc->restart.priority = 128;
|
||||
|
||||
return register_restart_handler(&pmc->restart);
|
||||
}
|
||||
|
||||
static int tegra186_pmc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_pmc *pmc;
|
||||
struct resource *res;
|
||||
|
||||
pmc = devm_kzalloc(&pdev->dev, sizeof(*pmc), GFP_KERNEL);
|
||||
if (!pmc)
|
||||
return -ENOMEM;
|
||||
|
||||
pmc->dev = &pdev->dev;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmc");
|
||||
pmc->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pmc->regs))
|
||||
return PTR_ERR(pmc->regs);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
|
||||
pmc->wake = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pmc->wake))
|
||||
return PTR_ERR(pmc->wake);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
|
||||
pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pmc->aotag))
|
||||
return PTR_ERR(pmc->aotag);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
|
||||
pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(pmc->scratch))
|
||||
return PTR_ERR(pmc->scratch);
|
||||
|
||||
return tegra186_pmc_setup(pmc);
|
||||
}
|
||||
|
||||
static const struct of_device_id tegra186_pmc_of_match[] = {
|
||||
{ .compatible = "nvidia,tegra186-pmc" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, tegra186_pmc_of_match);
|
||||
|
||||
static struct platform_driver tegra186_pmc_driver = {
|
||||
.driver = {
|
||||
.name = "tegra186-pmc",
|
||||
.of_match_table = tegra186_pmc_of_match,
|
||||
},
|
||||
.probe = tegra186_pmc_probe,
|
||||
};
|
||||
builtin_platform_driver(tegra186_pmc_driver);
|
||||
Loading…
Reference in a new issue