mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge b2e71fbdb8 on remote branch
Change-Id: I494533031f14846b222ccace007cdcec48b470cc
This commit is contained in:
commit
55e1a5c8a3
12 changed files with 129 additions and 21 deletions
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@ -118,6 +118,9 @@
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#define GET_TABLE_IDX_FROM_CTXID(ctxid) \
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((ctxid & FASTRPC_CTX_TABLE_IDX_MASK) >> FASTRPC_CTX_TABLE_IDX_POS)
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#define VALID_FASTRPC_CID(cid) \
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(cid >= ADSP_DOMAIN_ID && cid < NUM_CHANNELS)
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/* Reserve few entries in context table for critical kernel and static RPC
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* calls to avoid user invocations from exhausting all entries.
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*/
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@ -2066,7 +2069,11 @@ static int context_alloc(struct fastrpc_file *fl, uint32_t kernel,
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if (err)
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goto bail;
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}
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VERIFY(err, VALID_FASTRPC_CID(cid));
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if (err) {
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err = -ECHRNG;
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goto bail;
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}
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chan = &me->channel[cid];
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spin_lock_irqsave(&chan->ctxlock, irq_flags);
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@ -764,7 +764,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
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F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
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F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
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F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
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F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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@ -513,6 +513,13 @@ static void gi2c_gsi_rx_cb(void *ptr)
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struct msm_gpi_dma_async_tx_cb_param *rx_cb = ptr;
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struct geni_i2c_dev *gi2c = rx_cb->userdata;
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if (gi2c->cur == NULL) {
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GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,
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"%s: Error: unexpected callback\n", __func__);
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WARN_ON(1);
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return;
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}
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if (gi2c->cur->flags & I2C_M_RD) {
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gi2c_gsi_cb_err(rx_cb, "RX");
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complete(&gi2c->xfer);
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@ -72,6 +72,7 @@
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#define PCIE20_PARF_PHY_CTRL (0x40)
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#define PCIE20_PARF_TEST_BUS (0xe4)
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#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL (0x174)
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#define PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT (0x1a4)
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#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT (0x1a8)
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#define PCIE20_PARF_LTSSM (0x1b0)
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#define PCIE20_PARF_INT_ALL_STATUS (0x224)
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@ -845,6 +846,7 @@ struct msm_pcie_dev_t {
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uint32_t aux_clk_freq;
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bool linkdown_panic;
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uint32_t boot_option;
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bool pcie_halt_feature_dis;
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uint32_t rc_idx;
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uint32_t phy_ver;
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@ -1680,6 +1682,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
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dev->wr_halt_size);
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PCIE_DBG_FS(dev, "slv_addr_space_size: 0x%x\n",
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dev->slv_addr_space_size);
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PCIE_DBG_FS(dev, "PCIe: halt_feature_dis is %d\n",
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dev->pcie_halt_feature_dis);
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PCIE_DBG_FS(dev, "phy_status_offset: 0x%x\n",
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dev->phy_status_offset);
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PCIE_DBG_FS(dev, "phy_status_bit: %u\n",
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@ -4740,10 +4744,22 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev)
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE,
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dev->slv_addr_space_size);
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val = dev->wr_halt_size ? dev->wr_halt_size :
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readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
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if (dev->pcie_halt_feature_dis) {
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/* Disable PCIe Wr halt window */
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val = readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
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(~BIT(31)) & val);
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/* Disable PCIe Rd halt window */
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val = readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT,
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(~BIT(0)) & val);
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} else {
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val = dev->wr_halt_size ? dev->wr_halt_size :
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readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
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msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
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BIT(31) | val);
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}
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/* init tcsr */
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if (dev->tcsr_config)
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@ -6291,6 +6307,11 @@ static int msm_pcie_probe(struct platform_device *pdev)
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PCIE_DBG(pcie_dev, "RC%d: num-parf-testbus-sel: 0x%x.\n",
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pcie_dev->rc_idx, pcie_dev->num_parf_testbus_sel);
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pcie_dev->pcie_halt_feature_dis = of_property_read_bool(of_node,
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"qcom,pcie-halt-feature-dis");
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PCIE_DBG(pcie_dev, "PCIe halt feature is %s enabled.\n",
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pcie_dev->pcie_halt_feature_dis ? "not" : "");
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of_property_read_u32(of_node, "qcom,phy-status-offset",
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&pcie_dev->phy_status_offset);
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PCIE_DBG(pcie_dev, "RC%d: phy-status-offset: 0x%x.\n", pcie_dev->rc_idx,
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@ -393,6 +393,7 @@ struct ep_pcie_dev_t {
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ulong wake_counter;
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ulong msi_counter;
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ulong global_irq_counter;
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ulong perst_ast_in_enum_counter;
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bool dump_conf;
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bool config_mmio_init;
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@ -1681,6 +1681,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
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u32 val = 0;
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u32 retries = 0;
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u32 bme = 0;
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bool perst = true;
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bool ltssm_en = false;
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struct ep_pcie_dev_t *dev = &ep_pcie_dev;
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@ -1921,11 +1922,19 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt)
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if (retries % 100 == 0)
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EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE:0x%x\n",
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dev->rev, (val >> 0xC) & 0x3f);
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perst = atomic_read(&dev->perst_deast) ? 1 : 0;
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} while ((!(val & XMLH_LINK_UP) ||
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!ep_pcie_confirm_linkup(dev, false))
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&& (retries < LINK_UP_CHECK_MAX_COUNT));
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&& (retries < LINK_UP_CHECK_MAX_COUNT) && perst);
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if (retries == LINK_UP_CHECK_MAX_COUNT) {
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if (!perst) {
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dev->perst_ast_in_enum_counter++;
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EP_PCIE_ERR(dev,
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"PCIe V%d: Perst asserted No. %ld while waiting for link to be up\n",
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dev->rev, dev->perst_ast_in_enum_counter);
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ret = EP_PCIE_ERROR;
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goto link_fail;
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} else if (retries == LINK_UP_CHECK_MAX_COUNT) {
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EP_PCIE_ERR(dev, "PCIe V%d: link initialization failed\n",
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dev->rev);
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ret = EP_PCIE_ERROR;
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@ -529,12 +529,19 @@ struct mem_buf_xfer_mem *mem_buf_prep_xfer_mem(void *req_msg)
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int ret;
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struct mem_buf_xfer_mem *xfer_mem;
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struct mem_buf_alloc_req *req = req_msg;
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u32 nr_acl_entries = req->acl_desc.n_acl_entries;
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size_t alloc_req_msg_size = offsetof(struct mem_buf_alloc_req,
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acl_desc.acl_entries[nr_acl_entries]);
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void *arb_payload = req_msg + alloc_req_msg_size;
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u32 nr_acl_entries;
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size_t alloc_req_msg_size;
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void *arb_payload;
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void *mem_type_data;
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nr_acl_entries = req->acl_desc.n_acl_entries;
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if (nr_acl_entries != 1)
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return ERR_PTR(-EINVAL);
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alloc_req_msg_size = offsetof(struct mem_buf_alloc_req,
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acl_desc.acl_entries[nr_acl_entries]);
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arb_payload = req_msg + alloc_req_msg_size;
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xfer_mem = kzalloc(sizeof(*xfer_mem), GFP_KERNEL);
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if (!xfer_mem)
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return ERR_PTR(-ENOMEM);
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/thermal.h>
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@ -320,6 +321,12 @@ static int cpu_isolate_probe(struct platform_device *pdev)
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break;
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}
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}
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if (cpu_isolate_cdev->cpu_id == -1) {
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dev_err(&pdev->dev, "Invalid CPU phandle\n");
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continue;
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}
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INIT_WORK(&cpu_isolate_cdev->reg_work,
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cpu_isolate_register_cdev);
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list_add(&cpu_isolate_cdev->node, &cpu_isolate_cdev_list);
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s:%s " fmt, KBUILD_MODNAME, __func__
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@ -282,8 +283,7 @@ static int cc_init(struct device_node *np, int *cpus)
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}
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}
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snprintf(cc_cdev->cdev_name, THERMAL_NAME_LENGTH,
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"thermal-cluster-%d-%d", cc_cdev->cpu_map[0],
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cc_cdev->cpu_map[1]);
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np->name);
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cc_cdev->cdev = thermal_of_cooling_device_register(
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np, cc_cdev->cdev_name, cc_cdev,
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&cc_cooling_ops);
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@ -307,21 +307,53 @@ static int cc_cooling_probe(struct platform_device *pdev)
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struct device_node *np = dev->of_node;
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struct device_node *dev_phandle, *subsys_np = NULL;
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struct device *cpu_dev;
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int ret = 0, idx = 0, cpu;
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int ret = 0, idx = 0, count = 0, cpu;
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int cpu_count = 0;
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u32 cpu_map[CPU_MAP_CT];
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for_each_available_child_of_node(np, subsys_np) {
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for (idx = 0; idx < CPU_MAP_CT; idx++) {
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dev_phandle = of_parse_phandle(subsys_np, "qcom,cpus",
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cpu_count = of_count_phandle_with_args(subsys_np, "qcom,cluster0",
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NULL);
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for (idx = 0; idx < cpu_count; idx++) {
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dev_phandle = of_parse_phandle(subsys_np, "qcom,cluster0",
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idx);
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for_each_possible_cpu(cpu) {
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cpu_dev = get_cpu_device(cpu);
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if (cpu_dev && cpu_dev->of_node ==
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dev_phandle) {
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cpu_map[idx] = cpu;
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cpu_map[count] = cpu;
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count++;
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break;
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}
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}
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if (count)
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break;
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}
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if (!count) {
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pr_debug("Disabled as no core on cluster 0\n");
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return ret;
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}
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cpu_count = of_count_phandle_with_args(subsys_np, "qcom,cluster1",
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NULL);
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for (idx = 0; idx < cpu_count; idx++) {
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dev_phandle = of_parse_phandle(subsys_np, "qcom,cluster1",
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idx);
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for_each_possible_cpu(cpu) {
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cpu_dev = get_cpu_device(cpu);
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if (cpu_dev && cpu_dev->of_node ==
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dev_phandle) {
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cpu_map[count] = cpu;
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count++;
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break;
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}
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}
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if (count == 2)
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break;
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}
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if (count != 2) {
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pr_debug("Disabled as no core on cluster 1\n");
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return ret;
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}
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ret = cc_init(subsys_np, cpu_map);
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}
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@ -138,6 +138,7 @@ struct f_cdev {
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unsigned long nbytes_from_port_bridge;
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struct dentry *debugfs_root;
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bool setup_pending;
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/* To test remote wakeup using debugfs */
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u8 debugfs_rw_enable;
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@ -548,6 +549,7 @@ static int usb_cser_set_alt(struct usb_function *f, unsigned int intf,
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}
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static int port_notify_serial_state(struct cserial *cser);
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static void usb_cser_start_rx(struct f_cdev *port);
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static void usb_cser_resume(struct usb_function *f)
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{
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@ -566,6 +568,13 @@ static void usb_cser_resume(struct usb_function *f)
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port_notify_serial_state(&port->port_usb);
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spin_lock_irqsave(&port->port_lock, flags);
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/* process pending read request */
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if (port->setup_pending) {
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pr_info("%s: start_rx called due to rx_out error.\n", __func__);
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port->setup_pending = false;
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usb_cser_start_rx(port);
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}
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in = port->port_usb.in;
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/* process any pending requests */
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list_for_each_entry_safe(req, t, &port->write_pending, list) {
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@ -1055,7 +1064,10 @@ static void usb_cser_start_rx(struct f_cdev *port)
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pr_err("port(%d):%pK usb ep(%s) queue failed\n",
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port->port_num, port, ep->name);
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list_add(&req->list, pool);
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port->setup_pending = true;
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break;
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} else {
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port->setup_pending = false;
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}
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}
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|
|
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@ -130,7 +130,7 @@ struct ipa_wdi_hdr_info {
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*/
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struct ipa_wdi_reg_intf_in_params {
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const char *netdev_name;
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struct ipa_wdi_hdr_info hdr_info[IPA_IP_MAX];
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struct ipa_wdi_hdr_info hdr_info[IPA_IP_MAX_WLAN];
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enum ipa_client_type alt_dst_pipe;
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u8 is_meta_data_valid;
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u32 meta_data;
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|
|
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@ -698,7 +698,10 @@ enum ipa3_nat_mem_in {
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enum ipa_ip_type {
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IPA_IP_v4,
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IPA_IP_v6,
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IPA_IP_MAX
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IPA_IP_MAX,
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IPA_IP_v4_VLAN = IPA_IP_MAX,
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IPA_IP_v6_VLAN,
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IPA_IP_MAX_WLAN
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};
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#define VALID_IPA_IP_TYPE(t) \
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@ -3179,11 +3182,13 @@ enum ipa_vlan_ifaces {
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IPA_VLAN_IF_ETH0,
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IPA_VLAN_IF_ETH1,
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IPA_VLAN_IF_RNDIS,
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IPA_VLAN_IF_ECM
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IPA_VLAN_IF_ECM,
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IPA_VLAN_IF_WLAN
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};
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#define IPA_VLAN_IF_EMAC IPA_VLAN_IF_ETH
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#define IPA_VLAN_IF_MAX (IPA_VLAN_IF_ECM + 1)
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#define IPA_VLAN_IF_WLAN IPA_VLAN_IF_WLAN
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#define IPA_VLAN_IF_MAX (IPA_VLAN_IF_WLAN + 1)
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|
||||
/**
|
||||
* struct ipa_get_vlan_mode - get vlan mode of a Lan interface
|
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|
|
|
|||
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