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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Merge "msm: vidc: update hbb bit based on ddr type for shima"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
55e747f481
2 changed files with 742 additions and 9 deletions
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@ -1118,7 +1118,8 @@ int msm_vidc_decide_work_route_iris2(struct msm_vidc_inst *inst)
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u32 codec;
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uint32_t vpu;
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if (!inst || !inst->core || !inst->core->device) {
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if (!inst || !inst->core || !inst->core->device ||
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!inst->core->platform_data) {
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d_vpr_e("%s: Invalid args: Inst = %pK\n",
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__func__, inst);
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return -EINVAL;
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@ -1127,7 +1128,7 @@ int msm_vidc_decide_work_route_iris2(struct msm_vidc_inst *inst)
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vpu = inst->core->platform_data->vpu_ver;
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hdev = inst->core->device;
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is_legacy_cbr = inst->clk_data.is_legacy_cbr;
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pdata.video_work_route = 4;
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pdata.video_work_route = inst->core->platform_data->num_vpp_pipes;
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if (vpu == VPU_VERSION_IRIS2_1) {
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pdata.video_work_route = 1;
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@ -71,6 +71,15 @@ static struct msm_vidc_codec_data bengal_codec_data[] = {
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CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 440, 440),
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};
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static struct msm_vidc_codec_data shima_codec_data[] = {
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CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320),
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CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320),
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CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 0, 200, 200),
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CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 0, 200, 200),
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CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 0, 200, 200),
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CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 0, 200, 200),
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};
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static struct msm_vidc_codec_data holi_codec_data[] = {
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CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 0, 675, 320),
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CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 0, 675, 320),
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@ -95,6 +104,12 @@ static struct msm_vidc_codec bengal_codecs[] = {
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{ENC, H264}, {ENC, HEVC},
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};
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static struct msm_vidc_codec shima_codecs[] = {
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/* {domain, codec} */
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{DEC, H264}, {DEC, HEVC}, {DEC, VP9}, {DEC, MPEG2},
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{ENC, H264}, {ENC, HEVC},
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};
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static struct msm_vidc_codec holi_codecs[] = {
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/* {domain, codec} */
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{DEC, H264}, {DEC, HEVC}, {DEC, VP9},
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@ -390,6 +405,281 @@ static struct msm_vidc_codec_capability lahaina_capabilities[] = {
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V4L2_MPEG_VIDEO_HEVC_LEVEL_5},
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};
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static struct msm_vidc_codec_capability shima_capabilities_v0[] = {
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/* {cap_type, domains, codecs, min, max, step_size, default_value,} */
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{CAP_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 8192, 1, 1920},
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{CAP_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 8192, 1, 1080},
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/* (8192 * 4320) / 256 */
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{CAP_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 138240, 1, 138240},
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{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 480, 1, 30},
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/* Encode spec - 4K@60 */
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/* ((3840 * 2176) / 256) * 60 fps */
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{CAP_MBS_PER_SECOND, ENC, CODECS_ALL, 64, 1958400, 1, 489600},
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/* Decode spec - 8K@30, 4k@120*/
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/* ((8192 * 4320) / 256) * 30 fps */
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{CAP_MBS_PER_SECOND, DEC, CODECS_ALL, 64, 4147200, 1, 979200},
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{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 160000000, 1, 20000000},
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{CAP_CABAC_BITRATE, ENC, H264, 1, 160000000, 1, 20000000},
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{CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
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{CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
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{CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
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{CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
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{CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0},
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{CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0},
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{CAP_LTR_COUNT, ENC, H264|HEVC, 0, 4, 1, 0},
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/* ((1920 * 1088) / 256) * 60 fps */
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{CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL,
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0, 489600, 1, 489600},
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{CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10},
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{CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
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{CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
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/* 10 slices */
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{CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10},
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{CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10},
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{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
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/* Mpeg2 decoder specific */
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{CAP_FRAME_WIDTH, DEC, MPEG2, 128, 1920, 1, 1920},
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{CAP_FRAME_HEIGHT, DEC, MPEG2, 128, 1920, 1, 1080},
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/* (1920 * 1088) / 256 */
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{CAP_MBS_PER_FRAME, DEC, MPEG2, 64, 8160, 1, 8160},
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/* ((1920 * 1088) / 256) * 30*/
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{CAP_MBS_PER_SECOND, DEC, MPEG2, 64, 244800, 1, 244800},
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{CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30},
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{CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000},
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/* Secure usecase specific */
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{CAP_SECURE_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1920},
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{CAP_SECURE_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1080},
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/* (3840 * 2176) / 256 */
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{CAP_SECURE_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 34816, 1, 8160},
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{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000},
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/* Batch Mode Decode */
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{CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 64, 8160, 1, 8160},
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/* (1920 * 1088) / 256 */
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{CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 60, 1, 60},
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/* Lossless encoding usecase specific */
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{CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 4096, 1, 1920},
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{CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 4096, 1, 1080},
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/* (4096 * 2176) / 256 */
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{CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 34816, 1, 8160},
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/* All intra encoding usecase specific */
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{CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30},
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/* Image specific */
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{CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 1, 512},
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{CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 1, 512},
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{CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16384, 1, 16384},
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{CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16384, 1, 16384},
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/*
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* Level for AVC and HEVC encoder specific.
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* Default for levels is UNKNOWN value. But if we use unknown
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* value here to set as default, max value needs to be set to
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* unknown as well, which creates a problem of allowing client
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* to set higher level than supported.
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*/
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{CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
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V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1,
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V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
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{CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
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/* Level for AVC and HEVC decoder specific */
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{CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
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V4L2_MPEG_VIDEO_H264_LEVEL_5_2, 1,
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V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
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{CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
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};
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static struct msm_vidc_codec_capability shima_capabilities_v1[] = {
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/* {cap_type, domains, codecs, min, max, step_size, default_value,} */
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{CAP_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1920},
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{CAP_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1080},
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/* ((4096 * 2176) / 256) */
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{CAP_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 36, 34816, 1, 8160},
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/* ((3840 * 2176) / 256) * 60 fps */
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{CAP_MBS_PER_SECOND, DOMAINS_ALL, CODECS_ALL, 64, 1958400, 1, 489600},
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{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 480, 1, 30},
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{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 100000000, 1, 20000000},
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{CAP_CABAC_BITRATE, ENC, H264, 1, 100000000, 1, 20000000},
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{CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
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{CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
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{CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
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{CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
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{CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0},
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{CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0},
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{CAP_LTR_COUNT, ENC, H264|HEVC, 0, 4, 1, 0},
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/* ((1920 * 1088) / 256) * 30 fps */
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{CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL,
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0, 244800, 1, 244800},
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{CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10},
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{CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
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{CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
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/* 10 slices */
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{CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10},
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{CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10},
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{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
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/* Mpeg2 decoder specific */
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{CAP_FRAME_WIDTH, DEC, MPEG2, 128, 1920, 1, 1920},
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{CAP_FRAME_HEIGHT, DEC, MPEG2, 128, 1920, 1, 1080},
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/* (1920 * 1088) / 256 */
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{CAP_MBS_PER_FRAME, DEC, MPEG2, 64, 8160, 1, 8160},
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/* ((1920 * 1088) / 256) * 30 */
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{CAP_MBS_PER_SECOND, DEC, MPEG2, 64, 244800, 1, 244800},
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{CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30},
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{CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000},
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/* Secure usecase specific */
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{CAP_SECURE_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1920},
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{CAP_SECURE_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1080},
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/* (4096 * 2176) / 256 */
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{CAP_SECURE_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 34816, 1, 8160},
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{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000},
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/* Batch Mode Decode */
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{CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 64, 8160, 1, 8160},
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/* (1920 * 1088) / 256 */
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{CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 30, 1, 30},
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/* Lossless encoding usecase specific */
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{CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 3840, 1, 1920},
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{CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 3840, 1, 1080},
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/* (3840 * 2176) / 256 */
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{CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 32640, 1, 8160},
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/* All intra encoding usecase specific */
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{CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30},
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/* Image specific */
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{CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 1, 512},
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{CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 1, 512},
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{CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16384, 1, 16384},
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{CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16384, 1, 16384},
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/*
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* Level for AVC and HEVC encoder specific.
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* Default for levels is UNKNOWN value. But if we use unknown
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* value here to set as default, max value needs to be set to
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* unknown as well, which creates a problem of allowing client
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* to set higher level than supported.
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*/
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{CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
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V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1,
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V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
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{CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
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/* Level for AVC and HEVC decoder specific */
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{CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
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V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 1,
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V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
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{CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_5, 1,
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V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
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};
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static struct msm_vidc_codec_capability shima_capabilities_v2[] = {
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/* {cap_type, domains, codecs, min, max, step_size, default_value,} */
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{CAP_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1920},
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{CAP_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1080},
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/* (4096 * 2176) / 256 */
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{CAP_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 34816, 1, 8160},
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/* ((3840 * 2176) / 256) * 30 fps */
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{CAP_MBS_PER_SECOND, DOMAINS_ALL, CODECS_ALL, 64, 979200, 1, 244800},
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{CAP_FRAMERATE, DOMAINS_ALL, CODECS_ALL, 1, 240, 1, 30},
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{CAP_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 100000000, 1, 20000000},
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{CAP_CABAC_BITRATE, ENC, H264, 1, 100000000, 1, 20000000},
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{CAP_SCALE_X, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
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{CAP_SCALE_Y, ENC, CODECS_ALL, 8192, 65536, 1, 8192},
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{CAP_SCALE_X, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
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{CAP_SCALE_Y, DEC, CODECS_ALL, 65536, 65536, 1, 65536},
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{CAP_BFRAME, ENC, H264|HEVC, 0, 1, 1, 0},
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{CAP_HIER_P_NUM_ENH_LAYERS, ENC, H264|HEVC, 0, 6, 1, 0},
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{CAP_LTR_COUNT, ENC, H264|HEVC, 0, 2, 1, 0},
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/* ((1920 * 1088) / 256) * 60 fps */
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{CAP_MBS_PER_SECOND_POWER_SAVE, ENC, CODECS_ALL,
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0, 244800, 1, 244800},
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{CAP_I_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 10},
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{CAP_P_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
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{CAP_B_FRAME_QP, ENC, H264|HEVC, 0, 51, 1, 20},
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/* 10 slices */
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{CAP_SLICE_BYTE, ENC, H264|HEVC, 1, 10, 1, 10},
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{CAP_SLICE_MB, ENC, H264|HEVC, 1, 10, 1, 10},
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{CAP_MAX_VIDEOCORES, DOMAINS_ALL, CODECS_ALL, 0, 1, 1, 1},
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/* Mpeg2 decoder specific */
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{CAP_FRAME_WIDTH, DEC, MPEG2, 128, 1920, 1, 1920},
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{CAP_FRAME_HEIGHT, DEC, MPEG2, 128, 1920, 1, 1080},
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/* (1920 * 1088) / 256 */
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{CAP_MBS_PER_FRAME, DEC, MPEG2, 64, 8160, 1, 8160},
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/* ((1920 * 1088) / 256) * 30*/
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{CAP_MBS_PER_SECOND, DEC, MPEG2, 64, 244800, 1, 244800},
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{CAP_FRAMERATE, DEC, MPEG2, 1, 30, 1, 30},
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{CAP_BITRATE, DEC, MPEG2, 1, 40000000, 1, 20000000},
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/* Secure usecase specific */
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{CAP_SECURE_FRAME_WIDTH, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1920},
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{CAP_SECURE_FRAME_HEIGHT, DOMAINS_ALL, CODECS_ALL, 128, 4096, 1, 1080},
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/* (4096 * 2176) / 256 */
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{CAP_SECURE_MBS_PER_FRAME, DOMAINS_ALL, CODECS_ALL, 64, 34816, 1, 8160},
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{CAP_SECURE_BITRATE, DOMAINS_ALL, CODECS_ALL, 1, 40000000, 1, 20000000},
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/* Batch Mode Decode */
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{CAP_BATCH_MAX_MB_PER_FRAME, DEC, CODECS_ALL, 64, 8160, 1, 8160},
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/* (1920 * 1088) / 256 */
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{CAP_BATCH_MAX_FPS, DEC, CODECS_ALL, 1, 30, 1, 30},
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/* Lossless encoding usecase specific */
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{CAP_LOSSLESS_FRAME_WIDTH, ENC, H264|HEVC, 128, 4096, 1, 1920},
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||||
{CAP_LOSSLESS_FRAME_HEIGHT, ENC, H264|HEVC, 128, 4096, 1, 1080},
|
||||
/* (4096 * 2176) / 256 */
|
||||
{CAP_LOSSLESS_MBS_PER_FRAME, ENC, H264|HEVC, 64, 34816, 1, 8160},
|
||||
|
||||
/* All intra encoding usecase specific */
|
||||
{CAP_ALLINTRA_MAX_FPS, ENC, H264|HEVC, 1, 120, 1, 30},
|
||||
|
||||
/* Image specific */
|
||||
{CAP_HEVC_IMAGE_FRAME_WIDTH, ENC, HEVC, 128, 512, 1, 512},
|
||||
{CAP_HEVC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 128, 512, 1, 512},
|
||||
{CAP_HEIC_IMAGE_FRAME_WIDTH, ENC, HEVC, 512, 16384, 1, 16384},
|
||||
{CAP_HEIC_IMAGE_FRAME_HEIGHT, ENC, HEVC, 512, 16384, 1, 16384},
|
||||
|
||||
/*
|
||||
* Level for AVC and HEVC encoder specific.
|
||||
* Default for levels is UNKNOWN value. But if we use unknown
|
||||
* value here to set as default, max value needs to be set to
|
||||
* unknown as well, which creates a problem of allowing client
|
||||
* to set higher level than supported.
|
||||
*/
|
||||
{CAP_H264_LEVEL, ENC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
|
||||
V4L2_MPEG_VIDEO_H264_LEVEL_5_0, 1,
|
||||
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
|
||||
{CAP_HEVC_LEVEL, ENC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
|
||||
V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, 1,
|
||||
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
|
||||
|
||||
/* Level for AVC and HEVC decoder specific */
|
||||
{CAP_H264_LEVEL, DEC, H264, V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
|
||||
V4L2_MPEG_VIDEO_H264_LEVEL_5_0, 1,
|
||||
V4L2_MPEG_VIDEO_H264_LEVEL_4_0},
|
||||
{CAP_HEVC_LEVEL, DEC, HEVC, V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
|
||||
V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, 1,
|
||||
V4L2_MPEG_VIDEO_HEVC_LEVEL_4},
|
||||
};
|
||||
|
||||
/*
|
||||
* Custom conversion coefficients for resolution: 176x144 negative
|
||||
* coeffs are converted to s4.9 format
|
||||
|
|
@ -669,6 +959,334 @@ static struct msm_vidc_common_data bengal_common_data_v1[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct msm_vidc_common_data shima_common_data_v0[] = {
|
||||
{
|
||||
.key = "qcom,never-unload-fw",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,sw-power-collapse",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,domain-attr-non-fatal-faults",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-secure-instances",
|
||||
.value = 3,
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hw-load",
|
||||
.value = 4147200,
|
||||
/**
|
||||
* (3840x2176)/256)@120fps decode,
|
||||
* (8192x4320)/256)@30fps decode
|
||||
*/
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-mbpf",
|
||||
.value = 138240, /* ((8192x4320)/256) */
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hq-mbs-per-frame",
|
||||
.value = 8160, /* ((1920x1088)/256) */
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hq-mbs-per-sec",
|
||||
.value = 489600, /* ((1920x1088)/256)@60fps */
|
||||
},
|
||||
{
|
||||
.key = "qcom,power-collapse-delay",
|
||||
.value = 1500,
|
||||
},
|
||||
{
|
||||
.key = "qcom,hw-resp-timeout",
|
||||
.value = 1000,
|
||||
},
|
||||
{
|
||||
.key = "qcom,debug-timeout",
|
||||
.value = 0,
|
||||
},
|
||||
{
|
||||
.key = "qcom,decode-batching",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,batch-timeout",
|
||||
.value = 200,
|
||||
},
|
||||
{
|
||||
.key = "qcom,dcvs",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,fw-cycles",
|
||||
.value = 326389,
|
||||
},
|
||||
{
|
||||
.key = "qcom,fw-vpp-cycles",
|
||||
.value = 44156,
|
||||
},
|
||||
{
|
||||
.key = "qcom,avsync-window-size",
|
||||
.value = 40,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_non_pix_buf_count",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_non_pix_buf_size",
|
||||
/*
|
||||
* Internal buffer size is calculated for secure decode session
|
||||
* of resolution 4k (4096x2160)
|
||||
* Internal buf size = calculate_scratch_size() +
|
||||
* calculate_scratch1_size() + calculate_persist1_size()
|
||||
* Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure
|
||||
* decoder sessions
|
||||
*/
|
||||
.value = 209715200,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_pix_buf_count",
|
||||
.value = 18,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_pix_buf_size",
|
||||
/*
|
||||
* Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC
|
||||
*/
|
||||
.value = 13434880,
|
||||
},
|
||||
{
|
||||
.key = "qcom,ubwc_stats_in_fbd",
|
||||
.value = 0,
|
||||
},
|
||||
{
|
||||
.key = "qcom,vpp_delay_supported",
|
||||
.value = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_vidc_common_data shima_common_data_v1[] = {
|
||||
{
|
||||
.key = "qcom,never-unload-fw",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,sw-power-collapse",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,domain-attr-non-fatal-faults",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-secure-instances",
|
||||
.value = 3,
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hw-load",
|
||||
.value = 1958400,
|
||||
/**
|
||||
* (3840x2176)/256)@60fps decode
|
||||
*/
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-mbpf",
|
||||
.value = 130560, /* ((3840x2176)/256) x 4 */
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hq-mbs-per-frame",
|
||||
.value = 8160, /* ((1920x1088)/256) */
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hq-mbs-per-sec",
|
||||
.value = 489600, /* ((1920x1088)/256)@60fps */
|
||||
},
|
||||
{
|
||||
.key = "qcom,power-collapse-delay",
|
||||
.value = 1500,
|
||||
},
|
||||
{
|
||||
.key = "qcom,hw-resp-timeout",
|
||||
.value = 1000,
|
||||
},
|
||||
{
|
||||
.key = "qcom,debug-timeout",
|
||||
.value = 0,
|
||||
},
|
||||
{
|
||||
.key = "qcom,decode-batching",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,batch-timeout",
|
||||
.value = 200,
|
||||
},
|
||||
{
|
||||
.key = "qcom,dcvs",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,fw-cycles",
|
||||
.value = 326389,
|
||||
},
|
||||
{
|
||||
.key = "qcom,fw-vpp-cycles",
|
||||
.value = 44156,
|
||||
},
|
||||
{
|
||||
.key = "qcom,avsync-window-size",
|
||||
.value = 40,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_non_pix_buf_count",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_non_pix_buf_size",
|
||||
/*
|
||||
* Internal buffer size is calculated for secure decode session
|
||||
* of resolution 4k (4096x2160)
|
||||
* Internal buf size = calculate_scratch_size() +
|
||||
* calculate_scratch1_size() + calculate_persist1_size()
|
||||
* Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure
|
||||
* decoder sessions
|
||||
*/
|
||||
.value = 209715200,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_pix_buf_count",
|
||||
.value = 18,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_pix_buf_size",
|
||||
/*
|
||||
* Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC
|
||||
*/
|
||||
.value = 13434880,
|
||||
},
|
||||
{
|
||||
.key = "qcom,ubwc_stats_in_fbd",
|
||||
.value = 0,
|
||||
},
|
||||
{
|
||||
.key = "qcom,vpp_delay_supported",
|
||||
.value = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_vidc_common_data shima_common_data_v2[] = {
|
||||
{
|
||||
.key = "qcom,never-unload-fw",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,sw-power-collapse",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,domain-attr-non-fatal-faults",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-secure-instances",
|
||||
.value = 3,
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hw-load",
|
||||
.value = 979200,
|
||||
/**
|
||||
* (3840x2176)/256)@30fps decode
|
||||
*/
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-mbpf",
|
||||
.value = 130560, /* ((3840x2176)/256) x 4 */
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hq-mbs-per-frame",
|
||||
.value = 8160, /* ((1920x1088)/256) */
|
||||
},
|
||||
{
|
||||
.key = "qcom,max-hq-mbs-per-sec",
|
||||
.value = 489600, /* ((1920x1088)/256)@60fps */
|
||||
},
|
||||
{
|
||||
.key = "qcom,power-collapse-delay",
|
||||
.value = 1500,
|
||||
},
|
||||
{
|
||||
.key = "qcom,hw-resp-timeout",
|
||||
.value = 1000,
|
||||
},
|
||||
{
|
||||
.key = "qcom,debug-timeout",
|
||||
.value = 0,
|
||||
},
|
||||
{
|
||||
.key = "qcom,decode-batching",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,batch-timeout",
|
||||
.value = 200,
|
||||
},
|
||||
{
|
||||
.key = "qcom,dcvs",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,fw-cycles",
|
||||
.value = 326389,
|
||||
},
|
||||
{
|
||||
.key = "qcom,fw-vpp-cycles",
|
||||
.value = 44156,
|
||||
},
|
||||
{
|
||||
.key = "qcom,avsync-window-size",
|
||||
.value = 40,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_non_pix_buf_count",
|
||||
.value = 1,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_non_pix_buf_size",
|
||||
/*
|
||||
* Internal buffer size is calculated for secure decode session
|
||||
* of resolution 4k (4096x2160)
|
||||
* Internal buf size = calculate_scratch_size() +
|
||||
* calculate_scratch1_size() + calculate_persist1_size()
|
||||
* Take maximum between VP9 10bit, HEVC 10bit, AVC, MPEG2 secure
|
||||
* decoder sessions
|
||||
*/
|
||||
.value = 209715200,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_pix_buf_count",
|
||||
.value = 18,
|
||||
},
|
||||
{
|
||||
.key = "qcom,prefetch_pix_buf_size",
|
||||
/*
|
||||
* Calculated by VENUS_BUFFER_SIZE for 4096x2160 UBWC
|
||||
*/
|
||||
.value = 13434880,
|
||||
},
|
||||
{
|
||||
.key = "qcom,ubwc_stats_in_fbd",
|
||||
.value = 0,
|
||||
},
|
||||
{
|
||||
.key = "qcom,vpp_delay_supported",
|
||||
.value = 0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct msm_vidc_common_data holi_common_data[] = {
|
||||
{
|
||||
.key = "qcom,never-unload-fw",
|
||||
|
|
@ -716,11 +1334,23 @@ static struct msm_vidc_common_data holi_common_data[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct msm_vidc_efuse_data shima_efuse_data[] = {
|
||||
/* IRIS_4K60_FMAX_LIMIT_EFUSE - max 4K@60 */
|
||||
EFUSE_ENTRY(0x007801E0, 4, 0x00200000, 0x15, SKU_VERSION),
|
||||
/* IRIS_MULTIPIPE_DISABLE - max 4K@30 */
|
||||
EFUSE_ENTRY(0x007801E0, 4, 0x00001000, 0x0B, SKU_VERSION),
|
||||
};
|
||||
|
||||
/* Default UBWC config for LPDDR5 */
|
||||
static struct msm_vidc_ubwc_config_data lahaina_ubwc_data[] = {
|
||||
UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 16, 0, 0),
|
||||
};
|
||||
|
||||
/* Default UBWC config for LPDDR5 */
|
||||
static struct msm_vidc_ubwc_config_data shima_ubwc_data[] = {
|
||||
UBWC_CONFIG(1, 1, 1, 0, 0, 0, 8, 32, 15, 0, 0),
|
||||
};
|
||||
|
||||
static struct msm_vidc_platform_data default_data = {
|
||||
.codec_data = default_codec_data,
|
||||
.codec_data_length = ARRAY_SIZE(default_codec_data),
|
||||
|
|
@ -777,6 +1407,26 @@ static struct msm_vidc_platform_data bengal_data = {
|
|||
.codec_caps_count = ARRAY_SIZE(bengal_capabilities_v0),
|
||||
};
|
||||
|
||||
static struct msm_vidc_platform_data shima_data = {
|
||||
.codec_data = shima_codec_data,
|
||||
.codec_data_length = ARRAY_SIZE(shima_codec_data),
|
||||
.common_data = shima_common_data_v0,
|
||||
.common_data_length = ARRAY_SIZE(shima_common_data_v0),
|
||||
.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,
|
||||
.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,
|
||||
.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,
|
||||
.efuse_data = shima_efuse_data,
|
||||
.efuse_data_length = ARRAY_SIZE(shima_efuse_data),
|
||||
.sku_version = 0,
|
||||
.vpu_ver = VPU_VERSION_IRIS2,
|
||||
.num_vpp_pipes = 0x2,
|
||||
.ubwc_config = shima_ubwc_data,
|
||||
.codecs = shima_codecs,
|
||||
.codecs_count = ARRAY_SIZE(shima_codecs),
|
||||
.codec_caps = shima_capabilities_v0,
|
||||
.codec_caps_count = ARRAY_SIZE(shima_capabilities_v0),
|
||||
};
|
||||
|
||||
static struct msm_vidc_platform_data holi_data = {
|
||||
.codec_data = holi_codec_data,
|
||||
.codec_data_length = ARRAY_SIZE(holi_codec_data),
|
||||
|
|
@ -802,6 +1452,10 @@ static const struct of_device_id msm_vidc_dt_device[] = {
|
|||
.compatible = "qcom,lahaina-vidc",
|
||||
.data = &lahaina_data,
|
||||
},
|
||||
{
|
||||
.compatible = "qcom,shima-vidc",
|
||||
.data = &shima_data,
|
||||
},
|
||||
{
|
||||
.compatible = "qcom,bengal-vidc",
|
||||
.data = &bengal_data,
|
||||
|
|
@ -815,6 +1469,48 @@ static const struct of_device_id msm_vidc_dt_device[] = {
|
|||
|
||||
MODULE_DEVICE_TABLE(of, msm_vidc_dt_device);
|
||||
|
||||
static int msm_vidc_read_efuse(
|
||||
struct msm_vidc_platform_data *data, struct device *dev)
|
||||
{
|
||||
void __iomem *base;
|
||||
uint32_t i;
|
||||
u32 efuse = 0;
|
||||
struct msm_vidc_efuse_data *efuse_data = data->efuse_data;
|
||||
uint32_t efuse_data_count = data->efuse_data_length;
|
||||
|
||||
if (!efuse_data)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < efuse_data_count; i++) {
|
||||
switch ((efuse_data[i]).purpose) {
|
||||
case SKU_VERSION:
|
||||
base = devm_ioremap(dev, (efuse_data[i]).start_address,
|
||||
(efuse_data[i]).size);
|
||||
if (!base) {
|
||||
d_vpr_e("failed efuse: start %#x, size %d\n",
|
||||
(efuse_data[i]).start_address,
|
||||
(efuse_data[i]).size);
|
||||
return -EINVAL;
|
||||
} else {
|
||||
efuse = readl_relaxed(base);
|
||||
data->sku_version =
|
||||
(efuse & (efuse_data[i]).mask) >>
|
||||
(efuse_data[i]).shift;
|
||||
devm_iounmap(dev, base);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if (data->sku_version) {
|
||||
d_vpr_h("efuse 0x%x, platform version 0x%x\n",
|
||||
efuse, data->sku_version);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int msm_vidc_read_rank(
|
||||
struct msm_vidc_platform_data *data, struct device *dev)
|
||||
{
|
||||
|
|
@ -850,6 +1546,13 @@ void *vidc_get_drv_data(struct device *dev)
|
|||
if (!driver_data)
|
||||
goto exit;
|
||||
|
||||
/* Check for sku version */
|
||||
if (of_find_property(dev->of_node, "sku-index", NULL)) {
|
||||
rc = msm_vidc_read_efuse(driver_data, dev);
|
||||
if (rc)
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (!strcmp(match->compatible, "qcom,lahaina-vidc")) {
|
||||
ddr_type = of_fdt_get_ddrtype();
|
||||
if (ddr_type == -ENOENT) {
|
||||
|
|
@ -878,6 +1581,35 @@ void *vidc_get_drv_data(struct device *dev)
|
|||
driver_data->codec_caps_count =
|
||||
ARRAY_SIZE(bengal_capabilities_v1);
|
||||
}
|
||||
} else if (!strcmp(match->compatible, "qcom,shima-vidc")) {
|
||||
if (driver_data->sku_version == SKU_VERSION_1) {
|
||||
driver_data->common_data = shima_common_data_v1;
|
||||
driver_data->common_data_length =
|
||||
ARRAY_SIZE(shima_common_data_v1);
|
||||
driver_data->codec_caps = shima_capabilities_v1;
|
||||
driver_data->codec_caps_count =
|
||||
ARRAY_SIZE(shima_capabilities_v1);
|
||||
} else if (driver_data->sku_version == SKU_VERSION_2) {
|
||||
driver_data->common_data = shima_common_data_v2;
|
||||
driver_data->common_data_length =
|
||||
ARRAY_SIZE(shima_common_data_v2);
|
||||
driver_data->codec_caps = shima_capabilities_v2;
|
||||
driver_data->codec_caps_count =
|
||||
ARRAY_SIZE(shima_capabilities_v2);
|
||||
}
|
||||
ddr_type = of_fdt_get_ddrtype();
|
||||
if (ddr_type == -ENOENT) {
|
||||
d_vpr_e("Failed to get ddr type, use LPDDR5\n");
|
||||
}
|
||||
|
||||
if (driver_data->ubwc_config &&
|
||||
(ddr_type == DDR_TYPE_LPDDR4 ||
|
||||
ddr_type == DDR_TYPE_LPDDR4X))
|
||||
driver_data->ubwc_config->highest_bank_bit = 0xe;
|
||||
|
||||
d_vpr_h("DDR Type 0x%x hbb 0x%x\n",
|
||||
ddr_type, driver_data->ubwc_config ?
|
||||
driver_data->ubwc_config->highest_bank_bit : -1);
|
||||
}
|
||||
exit:
|
||||
return driver_data;
|
||||
|
|
|
|||
Loading…
Reference in a new issue