From 83682c0361bbf5412cf8a4326481450f40842998 Mon Sep 17 00:00:00 2001 From: gururaj chalgeri Date: Mon, 23 Nov 2020 06:53:10 +0530 Subject: [PATCH] ARM: dts: msm: Add fastrpc and cdsp/adsp device node Add fastrpc context banks, memory regions, cdsp device node adsp and also restricting dma pools. Change-Id: Ia7177230e060519256f81ff6d25576f24a78b8cd --- qcom/yupik-ion.dtsi | 9 +++ qcom/yupik.dtsi | 188 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 197 insertions(+) diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi index a79bbd58abf5..88de7176ff89 100644 --- a/qcom/yupik-ion.dtsi +++ b/qcom/yupik-ion.dtsi @@ -16,6 +16,15 @@ qcom,ion-heap-type = "SYSTEM_SECURE"; }; + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = ; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_secure_heap_mem>; + token = <0x20000000>; + }; + }; + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ reg = ; memory-region = <&secure_display_memory>; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 69063c8d6eb7..b251394d0651 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -315,6 +315,14 @@ reg = <0x0 0x88f00000 0x0 0x1e00000>; }; + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + pil_camera_mem: video@8ad00000 { no-map; reg = <0x0 0x8ad00000 0x0 0x500000>; @@ -2412,6 +2420,186 @@ qfprom_sys: qfprom@0 { compatible = "qcom,qfprom-sys"; }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,rpc-latency-us = <235>; + qcom,fastrpc-gids = <2908>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A1 0x0420>, + <&apps_smmu 0x1181 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A2 0x0420>, + <&apps_smmu 0x1182 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A3 0x0420>, + <&apps_smmu 0x1183 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A4 0x0420>, + <&apps_smmu 0x1184 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A5 0x0420>, + <&apps_smmu 0x1185 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A6 0x0420>, + <&apps_smmu 0x1186 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A7 0x0420>, + <&apps_smmu 0x1187 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11A8 0x0420>, + <&apps_smmu 0x1188 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x11A9 0x0420>, + <&apps_smmu 0x1189 0x0420>; + qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1803 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1804 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1805 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + shared-cb = <5>; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AB 0x0420>, + <&apps_smmu 0x118B 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AC 0x0420>, + <&apps_smmu 0x118C 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AD 0x0420>, + <&apps_smmu 0x118D 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + + qcom,msm_fastrpc_compute_cb16 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x11AE 0x0420>, + <&apps_smmu 0x118E 0x0420>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable" , "HUPCF"; + dma-coherent-hint-cached; + }; + }; }; #include "shima-gdsc.dtsi"