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clk: mediatek: export cpu multiplexer clock for MT8173 SoCs

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The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.

Signed-off-by: Pi-Cheng Chen <[email protected]>
Signed-off-by: Sean Wang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
This commit is contained in:
Sean Wang 2017-05-05 23:26:11 +08:00 • committed by Stephen Boyd
commit 567bf2ed86
2 changed files with 26 additions and 1 deletions
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23
drivers/clk/mediatek/clk-mt8173.c
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@ -18,6 +18,7 @@
#include "clk-mtk.h"
#include "clk-gate.h"
#include "clk-cpumux.h"
#include <dt-bindings/clock/mt8173-clk.h>
@ -525,6 +526,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
"apll2_div5"
};
static const char * const ca53_parents[] __initconst = {
"clk26m",
"armca7pll",
"mainpll",
"univpll"
};
static const char * const ca57_parents[] __initconst = {
"clk26m",
"armca15pll",
"mainpll",
"univpll"
};
static const struct mtk_composite cpu_muxes[] __initconst = {
MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
};
static const struct mtk_composite top_muxes[] __initconst = {
/* CLK_CFG_0 */
MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
@ -948,6 +968,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
clk_data);
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",