From 6cde4d7b06955de643844049b376cec8590e65b8 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Wed, 12 Aug 2020 22:50:21 -0700 Subject: [PATCH] ARM: dts: msm: Add resources for Lahaina CC runtime_pm Add necessary clock and interconnect resources for runtime_pm of CAM_CC, DISP_CC, and VIDEO_CC. Change-Id: Iadb7650c5909d276f7a4f58fb895e9d621120b6b --- qcom/lahaina.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index a5ee90add681..979c9e5ded95 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2330,8 +2330,9 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - clock-names = "cfg_ahb_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + clock-names = "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2342,8 +2343,9 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - clock-names = "cfg_ahb_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + clock-names = "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2353,8 +2355,9 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; - clock-names = "cfg_ahb_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + clock-names = "iface"; #clock-cells = <1>; #reset-cells = <1>; };