ARM: dts: msm: Add USB nodes for Blair

Add USB nodes to support USB in peripheral mode on
simulation platforms for Blair.

Change-Id: I6c0b1815ce75e8a720720024dc187d0fcc33eceb
This commit is contained in:
Ashish Bhimanpalliwar 2021-03-19 20:15:54 +05:30 • committed by Gerrit - the friendly Code Review server
commit 574998b369
3 changed files with 78 additions and 0 deletions

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@ -149,3 +149,10 @@
&gcc {
clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;
};
&usb0 {
dwc3@4e00000 {
usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
maximum-speed = "high-speed";
dr_mode = "peripheral";
};
};

70
qcom/blair-usb.dtsi Normal file
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@ -0,0 +1,70 @@
#include <dt-bindings/clock/qcom,gcc-blair.h>
&soc {
/* Primary USB port related controller */
usb0: ssusb@4e00000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x4e00000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"xo", "sleep_clk", "utmi_clk";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
qcom,core-clk-rate = <133333333>;
qcom,core-clk-rate-hs = <66666667>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
qcom,gsi-disable-io-coherency;
dwc3@4e00000 {
compatible = "snps,dwc3";
reg = <0x4e00000 0xcd00>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
tx-fifo-resize;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x10>;
snps,usb3_lpm_capable;
usb-core-id = <0>;
maximum-speed = "super-speed";
dr_mode = "drd";
};
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
};

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@ -3382,6 +3382,7 @@
#include "holi-qupv3.dtsi"
#include "display/holi-sde.dtsi"
#include "holi-audio.dtsi"
#include "blair-usb.dtsi"
#include "ipcc-test-holi.dtsi"
&gcc_camss_top_gdsc {