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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add USB nodes for Blair
Add USB nodes to support USB in peripheral mode on simulation platforms for Blair. Change-Id: I6c0b1815ce75e8a720720024dc187d0fcc33eceb
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3 changed files with 78 additions and 0 deletions
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@ -149,3 +149,10 @@
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&gcc {
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clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;
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};
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&usb0 {
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dwc3@4e00000 {
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usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
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maximum-speed = "high-speed";
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dr_mode = "peripheral";
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};
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};
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70
qcom/blair-usb.dtsi
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70
qcom/blair-usb.dtsi
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@ -0,0 +1,70 @@
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#include <dt-bindings/clock/qcom,gcc-blair.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@4e00000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x4e00000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"xo", "sleep_clk", "utmi_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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qcom,core-clk-rate = <133333333>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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qcom,gsi-disable-io-coherency;
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dwc3@4e00000 {
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compatible = "snps,dwc3";
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reg = <0x4e00000 0xcd00>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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tx-fifo-resize;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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usb-core-id = <0>;
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maximum-speed = "super-speed";
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dr_mode = "drd";
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};
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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@ -3382,6 +3382,7 @@
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#include "holi-qupv3.dtsi"
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#include "display/holi-sde.dtsi"
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#include "holi-audio.dtsi"
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#include "blair-usb.dtsi"
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#include "ipcc-test-holi.dtsi"
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&gcc_camss_top_gdsc {
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