diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi
index 1fe82f3a9f62..c828f6cc5205 100644
--- a/qcom/shima-pinctrl.dtsi
+++ b/qcom/shima-pinctrl.dtsi
@@ -7,6 +7,7 @@
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		wakeup-parent = <&pdc>;
 	};
 };
 
diff --git a/qcom/shima-pm.dtsi b/qcom/shima-pm.dtsi
new file mode 100644
index 000000000000..252937ac01bb
--- /dev/null
+++ b/qcom/shima-pm.dtsi
@@ -0,0 +1,184 @@
+&soc {
+	qcom,lpm-levels {
+		compatible = "qcom,lpm-levels";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		qcom,pm-cluster@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			idle-state-name = "L3";
+			qcom,clstr-tmr-add = <1000>;
+			qcom,psci-mode-shift = <4>;
+			qcom,psci-mode-mask = <0xfff>;
+
+			CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */
+				reg = <0>;
+				compatible = "arm,idle-state";
+				idle-state-name = "l3-wfi";
+				entry-latency-us = <660>;
+				exit-latency-us = <600>;
+				min-residency-us = <1260>;
+				arm,psci-suspend-param = <0x10>;
+				qcom,psci-mode = <0x1>;
+			};
+
+			CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */
+				reg = <1>;
+				compatible = "arm,idle-state";
+				idle-state-name = "l3-pc";
+				entry-latency-us = <2752>;
+				exit-latency-us = <3048>;
+				min-residency-us = <6118>;
+				arm,psci-suspend-param = <0x40>;
+				qcom,psci-mode = <0x4>;
+				qcom,is-reset;
+				qcom,min-child-idx = <2>;
+			};
+
+			CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */
+				reg = <2>;
+				compatible = "arm,idle-state";
+				idle-state-name = "cx-off";
+				entry-latency-us = <3263>;
+				exit-latency-us = <4562>;
+				min-residency-us = <8467>;
+				arm,psci-suspend-param = <0x2240>;
+				qcom,psci-mode = <0x224>;
+				qcom,is-reset;
+				qcom,notify-rpm;
+				qcom,min-child-idx = <2>;
+			};
+
+			LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */
+				reg = <3>;
+				compatible = "arm,idle-state";
+				idle-state-name = "llcc-off";
+				entry-latency-us = <3638>;
+				exit-latency-us = <6562>;
+				min-residency-us = <9826>;
+				arm,psci-suspend-param = <0xc240>;
+				qcom,psci-mode = <0xc24>;
+				qcom,is-reset;
+				qcom,notify-rpm;
+				qcom,min-child-idx = <2>;
+			};
+
+			qcom,pm-cpu@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,psci-mode-shift = <0>;
+				qcom,psci-mode-mask = <0xf>;
+				qcom,ref-stddev = <500>;
+				qcom,tmr-add = <1000>;
+				qcom,ref-premature-cnt = <1>;
+				qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+				SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */
+					reg = <0>;
+					compatible = "arm,idle-state";
+					idle-state-name = "wfi";
+					entry-latency-us = <61>;
+					exit-latency-us = <60>;
+					min-residency-us = <121>;
+					arm,psci-suspend-param = <0x1>;
+					qcom,psci-cpu-mode = <0x1>;
+				};
+
+				SLVR_OFF: qcom,pm-cpu-level@1 {  /* C3 */
+					reg = <1>;
+					compatible = "arm,idle-state";
+					idle-state-name = "pc";
+					entry-latency-us = <549>;
+					exit-latency-us = <901>;
+					min-residency-us = <1774>;
+					arm,psci-suspend-param = <0x40000003>;
+					qcom,psci-cpu-mode = <0x3>;
+					local-timer-stop;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+
+				SLVR_RAIL_OFF: qcom,pm-cpu-level@2 {  /* C4 */
+					reg = <2>;
+					compatible = "arm,idle-state";
+					idle-state-name = "rail-pc";
+					entry-latency-us = <702>;
+					exit-latency-us = <915>;
+					min-residency-us = <4001>;
+					arm,psci-suspend-param = <0x40000004>;
+					qcom,psci-cpu-mode = <0x4>;
+					local-timer-stop;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+			};
+
+			qcom,pm-cpu@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				qcom,psci-mode-shift = <0>;
+				qcom,psci-mode-mask = <0xf>;
+				qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+				GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */
+					reg = <0>;
+					compatible = "arm,idle-state";
+					idle-state-name = "wfi";
+					entry-latency-us = <55>;
+					exit-latency-us = <66>;
+					min-residency-us = <121>;
+					arm,psci-suspend-param = <0x1>;
+					qcom,psci-cpu-mode = <0x1>;
+				};
+
+				GOLD_OFF: qcom,pm-cpu-level@1 {  /* C3 */
+					reg = <1>;
+					compatible = "arm,idle-state";
+					idle-state-name = "pc";
+					entry-latency-us = <523>;
+					exit-latency-us = <1244>;
+					min-residency-us = <2207>;
+					arm,psci-suspend-param = <0x40000003>;
+					qcom,psci-cpu-mode = <0x3>;
+					local-timer-stop;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+
+				GOLD_RAIL_OFF: qcom,pm-cpu-level@2 {  /* C4 */
+					reg = <2>;
+					compatible = "arm,idle-state";
+					idle-state-name = "rail-pc";
+					entry-latency-us = <526>;
+					exit-latency-us = <1854>;
+					min-residency-us = <5555>;
+					arm,psci-suspend-param = <0x40000004>;
+					qcom,psci-cpu-mode = <0x4>;
+					local-timer-stop;
+					qcom,is-reset;
+					qcom,use-broadcast-timer;
+				};
+			};
+		};
+	};
+
+	rpmh-master-stats@b221200 {
+		compatible = "qcom,rpmh-master-stats-v1";
+		reg = <0xb221200 0x60>;
+	};
+
+	soc-sleep-stats@c3f0000 {
+		compatible = "qcom,rpmh-sleep-stats";
+		reg = <0xc3f0000 0x400>;
+	};
+
+	ddr-stats@c300000 {
+		compatible = "qcom,ddr-stats";
+		reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
+		reg-names = "phys_addr_base", "offset_addr";
+	};
+};
diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index da9501f6f37f..490064c4c6a1 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,videocc-shima.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Shima";
@@ -31,6 +32,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
 			next-level-cache = <&L2_0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -53,6 +55,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
 			next-level-cache = <&L2_1>;
 			L2_1: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -69,6 +72,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
 			next-level-cache = <&L2_2>;
 			L2_2: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -85,6 +89,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
 			next-level-cache = <&L2_3>;
 			L2_3: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -101,6 +106,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
 			next-level-cache = <&L2_4>;
 			L2_4: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -117,6 +123,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
 			next-level-cache = <&L2_5>;
 			L2_5: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -133,6 +140,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
 			next-level-cache = <&L2_6>;
 			L2_6: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -149,6 +157,7 @@
 			enable-method = "psci";
 			d-cache-size = <0x8000>;
 			i-cache-size = <0x8000>;
+			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
 			next-level-cache = <&L2_7>;
 			L2_7: l2-cache {
 			      compatible = "arm,arch-cache";
@@ -324,6 +333,11 @@
 	ranges = <0 0 0 0xffffffff>;
 	compatible = "simple-bus";
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	intc: interrupt-controller@17a00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
@@ -335,6 +349,19 @@
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	pdc: interrupt-controller@b220000 {
+		compatible = "qcom,shima-pdc";
+		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
+		qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+				  <55 306 4>, <59 312 3>, <62 374 2>,
+				  <64 434 2>, <66 438 3>, <69 86 1>,
+				  <70 520 54>, <124 609 31>, <155 63 1>,
+				  <156 716 12>;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&intc>;
+		interrupt-controller;
+	};
+
 	wdog: qcom,wdt@17c10000 {
 		compatible = "qcom,msm-watchdog";
 		reg = <0x17c10000 0x1000>;
@@ -772,9 +799,42 @@
 		mboxes = <&qmp_aop 0>;
 		mbox-names = "aop";
 	};
+
+	apps_rsc: rsc@18200000 {
+		label = "apps_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0x18200000 0x10000>,
+		      <0x18210000 0x10000>,
+		      <0x18220000 0x10000>;
+		reg-names = "drv-0", "drv-1", "drv-2";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0xd00>;
+		qcom,drv-id = <2>;
+		qcom,tcs-config = <ACTIVE_TCS  2>,
+				  <SLEEP_TCS   3>,
+				  <WAKE_TCS    3>,
+				  <CONTROL_TCS 1>;
+	};
+
+	disp_rsc: rsc@af20000 {
+		label = "disp_rsc";
+		compatible = "qcom,rpmh-rsc";
+		reg = <0xaf20000 0x10000>;
+		reg-names = "drv-0";
+		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,tcs-offset = <0x1c00>;
+		qcom,drv-id = <0>;
+		qcom,tcs-config = <ACTIVE_TCS  0>,
+				  <SLEEP_TCS   1>,
+				  <WAKE_TCS    1>,
+				  <CONTROL_TCS 0>;
+	};
 };
 
 #include "shima-pinctrl.dtsi"
+#include "shima-pm.dtsi"
 #include "shima-stub-regulator.dtsi"
 #include "shima-gdsc.dtsi"
 #include "shima-ion.dtsi"