A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-08 21:22:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

msm: kgsl: Add GBIF L2 CGC control with A6x CGC

Browse source 
GBIF L2 CGC is not covered in UCHE CGC control.
Hence handle GBIF L2 CGC settings separately.

Change-Id: I9f33b2a868a81a68c5957990f737a3eeab7cd6fc
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
This commit is contained in:
Hareesh Gundu 2021-01-27 15:52:36 +05:30
commit 587764ea8b
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
drivers/gpu/msm/adreno_a6xx.c
View file

@ -49,6 +49,7 @@ static u32 a6xx_pwrup_reglist[] = {
A6XX_SP_NC_MODE_CNTL,
A6XX_PC_DBG_ECO_CNTL,
A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,
A6XX_UCHE_GBIF_GX_CONFIG,
};
/* IFPC only static powerup restore list */
@ -372,6 +373,9 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
kgsl_regwrite(device, a6xx_core->hwcg[i].offset,
on ? a6xx_core->hwcg[i].value : 0);
/* GBIF L2 CGC control is not part of the UCHE */
kgsl_regrmw(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x70000, on ? 2 : 0);
/*
* Enable SP clock after programming HWCG registers.
* A612 and A610 GPU is not having the GX power domain.