From d4111cad7e166f323527498d880e40ec7ee134ed Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Wed, 8 Jul 2020 18:41:20 +0530 Subject: [PATCH 1/3] BACKPORT: mmc: sdhci-msm: Set IO pins in low power state during suspend Configure SDHC IO pins with low power configuration when the driver is in suspend state. Change-Id: Ia099d77289e8c3e2ced8fca718563ab366a4c6f5 Signed-off-by: Veerabhadrarao Badiganti Link: https://lore.kernel.org/r/1594213888-2780-2-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 920d295a99f9..f4d4bb9fd966 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" #include "cqhci.h" @@ -1489,6 +1490,20 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, sdhci_msm_hs400(host, &mmc->ios); } +/* Apply active/sleep pin config based on bus on/off state */ +static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level) +{ + struct platform_device *pdev = msm_host->pdev; + int ret; + + if (level) + ret = pinctrl_pm_select_default_state(&pdev->dev); + else + ret = pinctrl_pm_select_sleep_state(&pdev->dev); + + return ret; +} + #define MAX_PROP_SIZE 32 static int sdhci_msm_dt_parse_vreg_info(struct device *dev, struct sdhci_msm_reg_data **vreg_data, const char *vreg_name) @@ -2118,6 +2133,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) if (!ret) ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_HIGH, 0); + if (!ret) + ret = sdhci_msm_set_pincfg(msm_host, true); + if (ret) irq_ack |= CORE_PWRCTL_BUS_FAIL; else @@ -2133,6 +2151,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) if (!ret) ret = sdhci_msm_set_vdd_io_vol(msm_host->pdata, VDD_IO_LOW, 0); + if (!ret) + ret = sdhci_msm_set_pincfg(msm_host, false); + if (ret) irq_ack |= CORE_PWRCTL_BUS_FAIL; else From dfc165dfbdfcf7cc95cb902c314e1478abe79ca9 Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Fri, 7 Feb 2020 17:34:28 +0530 Subject: [PATCH 2/3] UPSTREAM: mmc: sdhci-msm: Don't enable PWRSAVE_DLL for certain sdhc hosts SDHC core with new 14lpp and later tech DLL should not enable PWRSAVE_DLL since such controller's internal gating cannot meet following MCLK requirement: When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK must be switched on for at-least 1us before DATA starts coming. Adding support for this requirement. Change-Id: I0a00ea4deb9d043db501d781860361fcac52a58a Signed-off-by: Ritesh Harjani Signed-off-by: Veerabhadrarao Badiganti Reviewed-by: Can Guo Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1581077075-26011-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson Signed-off-by: Veerabhadrarao Badiganti Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index f4d4bb9fd966..8ac9de980e1d 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1184,9 +1184,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) goto out; } - config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); - config |= CORE_PWRSAVE_DLL; - writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); + /* + * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3. + * When MCLK is gated OFF, it is not gated for less than 0.5us + * and MCLK must be switched on for at-least 1us before DATA + * starts coming. Controllers with 14lpp and later tech DLL cannot + * guarantee above requirement. So PWRSAVE_DLL should not be + * turned on for host controllers using this DLL. + */ + if (!msm_host->use_14lpp_dll_reset) { + config = readl_relaxed(host->ioaddr + + msm_offset->core_vendor_spec3); + config |= CORE_PWRSAVE_DLL; + writel_relaxed(config, host->ioaddr + + msm_offset->core_vendor_spec3); + } /* * Drain writebuffer to ensure above DLL calibration From 99d7f96ca7b01c3614a6ba4ae08732329decf460 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Fri, 10 Jul 2020 20:00:35 +0530 Subject: [PATCH 3/3] mmc: sdhci-msm: Update DDR_CONFIG reg with HSR value if supplied Update DDR_CONFIG register with HSR value if HSR value is supplied in the device tree. Change-Id: Iffabe98ae2fe2bcc74926a7527efa7fa38bedd11 Signed-off-by: Veerabhadrarao Badiganti Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 8ac9de980e1d..2f4ac0f654f5 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1158,7 +1158,13 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) ddr_cfg_offset = msm_offset->core_ddr_config; else ddr_cfg_offset = msm_offset->core_ddr_config_old; - writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset); + + if (msm_host->dll_hsr->ddr_config) + config = msm_host->dll_hsr->ddr_config; + else + config = DDR_CONFIG_POR_VAL; + + writel_relaxed(config, host->ioaddr + ddr_cfg_offset); if (mmc->ios.enhanced_strobe) { config = readl_relaxed(host->ioaddr + @@ -3545,7 +3551,7 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev) } static const struct dev_pm_ops sdhci_msm_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, sdhci_msm_runtime_resume,