From 0479f03a2be97dba257e70174654f143564c7ca7 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 13:43:53 +0530 Subject: [PATCH 1/6] defconfig: Enable devfreq support on Direwolf Enable the devfreq governor, monitor and device support on Direwolf target. Change-Id: I62a4076aaf741bab95bb61b18c7f812055fecce5 Signed-off-by: Shreyas K K --- arch/arm64/configs/vendor/direwolf_auto_QGKI.config | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/vendor/direwolf_auto_QGKI.config b/arch/arm64/configs/vendor/direwolf_auto_QGKI.config index 73a604c712fb..ac806cf94b05 100644 --- a/arch/arm64/configs/vendor/direwolf_auto_QGKI.config +++ b/arch/arm64/configs/vendor/direwolf_auto_QGKI.config @@ -10,3 +10,9 @@ CONFIG_QCOM_IOMMU_IO_PGTABLE_QUIRKS=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_QCOM_LAZY_MAPPING=y CONFIG_QCOM_MINIDUMP=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_ARM_QCOM_DEVFREQ_QOSLAT=y +CONFIG_QCOM_DEVFREQ_ICC=y From 62d5c1cb69b3bf85b0548015470ad98c1000f61e Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:28:03 +0530 Subject: [PATCH 2/6] drivers: qcom: Add LLCC driver for Direwolf platform Add Last Level Cache Controller driver for Direwolf platform. Change-Id: I489d5053495653f66ecd788faa441434d2c209dd Signed-off-by: Shreyas K K --- drivers/soc/qcom/Kconfig | 9 +++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/llcc-direwolf.c | 94 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 4 +- 4 files changed, 107 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/qcom/llcc-direwolf.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a445b42b937a..4ffdc2ad6e6b 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -248,6 +248,15 @@ config QCOM_LLCC_PERFMON interface. sysfs interface is used to configure and dump the LLCC performance events. +config QCOM_DIREWOLF_LLCC + tristate "Qualcomm Technologies, Inc. Direwolf LLCC driver" + depends on QCOM_LLCC + help + Say y or m here to enable the LLCC driver for Direwolf platform. + This provides data required to configure LLCC so that clients + can start using the LLCC slices. + If unsure, say n. + config QCOM_MDT_LOADER tristate select QCOM_SCM diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 23fff0f379e7..a9f32608c1fc 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_QCOM_YUPIK_LLCC) += llcc-yupik.o obj-$(CONFIG_QCOM_SM8150_LLCC) += llcc-sm8150.o obj-$(CONFIG_QCOM_SDMSHRIKE_LLCC) += llcc-sdmshrike.o obj-$(CONFIG_QCOM_SM6150_LLCC) += llcc-sm6150.o +obj-$(CONFIG_QCOM_DIREWOLF_LLCC) += llcc-direwolf.o obj-$(CONFIG_QCOM_MINIDUMP) += msm_minidump.o minidump_log.o obj-$(CONFIG_QCOM_MEM_OFFLINE) += mem-offline.o obj-$(CONFIG_QCOM_MEM_BUF) += mem-buf.o mem_buf_dma_buf.o diff --git a/drivers/soc/qcom/llcc-direwolf.c b/drivers/soc/qcom/llcc-direwolf.c new file mode 100644 index 000000000000..6de68fd7eeb0 --- /dev/null +++ b/drivers/soc/qcom/llcc-direwolf.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * + */ + +#include +#include +#include +#include +#include + +/* + * SCT entry contains of the following parameters + * uid: Unique id for the client's use case + * slice_id: llcc slice id for each client + * max_cap: The maximum capacity of the cache slice provided in KB + * priority: Priority of the client used to select victim line for replacement + * fixed_size: Determine of the slice has a fixed capacity + * bonus_ways: Bonus ways to be used by any slice, bonus way is used only if + * it't not a reserved way. + * res_ways: Reserved ways for the cache slice, the reserved ways cannot be used + * by any other client than the one its assigned to. + * cache_mode: Each slice operates as a cache, this controls the mode of the + * slice normal or TCM + * probe_target_ways: Determines what ways to probe for access hit. When + * configured to 1 only bonus and reserved ways are probed. + * when configured to 0 all ways in llcc are probed. + * dis_cap_alloc: Disable capacity based allocation for a client + * write_scid_en: Bit enables write cache support for a given scid. + * retain_on_pc: If this bit is set and client has maitained active vote + * then the ways assigned to this client are not flushed on power + * collapse. + * activate_on_init: Activate the slice immidiately after the SCT is programmed + */ +#define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, wse, rp, a) \ + { \ + .usecase_id = uid, \ + .slice_id = sid, \ + .max_cap = mc, \ + .priority = p, \ + .fixed_size = fs, \ + .bonus_ways = bway, \ + .res_ways = rway, \ + .cache_mode = cmod, \ + .probe_target_ways = ptw, \ + .dis_cap_alloc = dca, \ + .write_scid_en = wse, \ + .retain_on_pc = rp, \ + .activate_on_init = a, \ + } + +static struct llcc_slice_config direwolf_data[] = { + SCT_ENTRY(LLCC_CPUSS, 1, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1), + SCT_ENTRY(LLCC_VIDSC0, 2, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0), + SCT_ENTRY(LLCC_CMPT, 10, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0), + SCT_ENTRY(LLCC_GPUHTW, 11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_GPU, 12, 4608, 1, 0, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0), + SCT_ENTRY(LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), + SCT_ENTRY(LLCC_DISP, 16, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_AUDHW, 22, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_DRE, 26, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_CVP, 28, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_WRTCH, 31, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), + SCT_ENTRY(LLCC_CVPFW, 17, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_CPUSS1, 3, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0), + SCT_ENTRY(LLCC_CMPT1, 14, 6144, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 0), + SCT_ENTRY(LLCC_CPUHWT, 5, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1), +}; + +static int direwolf_qcom_llcc_probe(struct platform_device *pdev) +{ + return qcom_llcc_probe(pdev, direwolf_data, + ARRAY_SIZE(direwolf_data)); +} + +static const struct of_device_id direwolf_qcom_llcc_of_match[] = { + { .compatible = "qcom,direwolf-llcc" }, + { }, +}; + +static struct platform_driver direwolf_qcom_llcc_driver = { + .driver = { + .name = "direwolf-llcc", + .of_match_table = direwolf_qcom_llcc_of_match, + }, + .probe = direwolf_qcom_llcc_probe, +}; +module_platform_driver(direwolf_qcom_llcc_driver); + +MODULE_DESCRIPTION("QCOM Direwolf LLCC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index df8d7e39d1d4..a65033f5a75c 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. * */ @@ -30,12 +30,14 @@ #define LLCC_NPU 23 #define LLCC_WLNHW 24 #define LLCC_PIMEM 25 +#define LLCC_DRE 26 #define LLCC_CVP 28 #define LLCC_MDMVPE 29 #define LLCC_APTCM 30 #define LLCC_WRTCH 31 #define LLCC_CVPFW 32 #define LLCC_CPUSS1 33 +#define LLCC_CMPT1 34 #define LLCC_CPUHWT 36 #define LLCC_MDMCLD2 37 From 888f7fc66d9e3112e9305d15a89e940f723b0ace Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:29:42 +0530 Subject: [PATCH 3/6] defconfig: Enable LLCC support on Direwolf target Enable QCOM_LLCC to allow clients to use the last level cache controller block. Change-Id: Ic63669cb395097198bfd6f2822955d5f3d521215 Signed-off-by: Shreyas K K --- arch/arm64/configs/vendor/direwolf_auto_GKI.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/direwolf_auto_GKI.config b/arch/arm64/configs/vendor/direwolf_auto_GKI.config index 3af1ffdeedef..73f062b7f965 100644 --- a/arch/arm64/configs/vendor/direwolf_auto_GKI.config +++ b/arch/arm64/configs/vendor/direwolf_auto_GKI.config @@ -36,3 +36,5 @@ CONFIG_QCOM_SOC_WATCHDOG=m CONFIG_POWER_RESET_MSM=m CONFIG_QCOM_MEMORY_DUMP_V2=m CONFIG_QCOM_SCM=m +CONFIG_QCOM_LLCC=m +CONFIG_QCOM_DIREWOLF_LLCC=m From 244996a62cd4fa275b9d6590c5f23969df0eebc2 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:34:40 +0530 Subject: [PATCH 4/6] drivers: qcom: socinfo: Add Direwolf SoC IDs Add Direwolf SoC IDs for SC, IVI, and ADAS platform. Change-Id: I6b8263921eca2781c5903c2316bb60bc0273c290 Signed-off-by: Shreyas K K --- drivers/soc/qcom/socinfo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index eae23b18f03d..8ac99580769d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -668,7 +668,10 @@ static const struct soc_id soc_id[] = { { 405, "SA8195P" }, { 415, "LAHAINA" }, { 439, "LAHAINAP" }, + { 449, "SC_DIREWOLF"}, { 456, "LAHAINA-ATP" }, + { 460, "SA_DIREWOLF_IVI"}, + { 461, "SA_DIREWOLF_ADAS"}, { 501, "SM8325" }, { 502, "SM8325P" }, { 450, "SHIMA" }, From cb77a262323460e6f4c23fb84676709787fe687a Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:36:51 +0530 Subject: [PATCH 5/6] defconfig: Enable Socinfo driver on Direwolf target Enable Socinfo driver support on Direwolf target. Change-Id: Ic148b9e7bdb25950ee9be26ceaae38d4a0261eb7 Signed-off-by: Shreyas K K --- arch/arm64/configs/vendor/direwolf_auto_GKI.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/direwolf_auto_GKI.config b/arch/arm64/configs/vendor/direwolf_auto_GKI.config index 73f062b7f965..5d76b4045495 100644 --- a/arch/arm64/configs/vendor/direwolf_auto_GKI.config +++ b/arch/arm64/configs/vendor/direwolf_auto_GKI.config @@ -38,3 +38,4 @@ CONFIG_QCOM_MEMORY_DUMP_V2=m CONFIG_QCOM_SCM=m CONFIG_QCOM_LLCC=m CONFIG_QCOM_DIREWOLF_LLCC=m +CONFIG_QCOM_SOCINFO=m From 63f476db34feef89f179fd4588676786ddb4a0ae Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 17 Mar 2021 14:09:00 +0530 Subject: [PATCH 6/6] defconfig: Enable LLCC PMU on Direwolf target Enable LLCC PMU for monitiring and measuring various LLCC events on Direwolf target. Change-Id: I8d9f8ad889140c2c21f8c63dc8774307ebbe2c88 Signed-off-by: Shreyas K K --- arch/arm64/configs/vendor/direwolf_auto_QGKI.config | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/direwolf_auto_QGKI.config b/arch/arm64/configs/vendor/direwolf_auto_QGKI.config index ac806cf94b05..902c59470884 100644 --- a/arch/arm64/configs/vendor/direwolf_auto_QGKI.config +++ b/arch/arm64/configs/vendor/direwolf_auto_QGKI.config @@ -16,3 +16,4 @@ CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_ARM_QCOM_DEVFREQ_QOSLAT=y CONFIG_QCOM_DEVFREQ_ICC=y +CONFIG_QCOM_LLCC_PMU=y