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Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next

Browse source 
- NXP i.MX7ULP SoC clock support
 - Support for i.MX8QXP SoC clocks
 - Support for NXP i.MX8MQ clock controllers

* clk-imx7ulp:
  clk: imx: add imx7ulp clk driver
  clk: imx: implement new clk_hw based APIs
  clk: imx: make mux parent strings const
  dt-bindings: clock: add imx7ulp clock binding doc
  clk: imx: add imx7ulp composite clk support
  clk: imx: add pfdv2 support
  clk: imx: add pllv4 support
  clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support
  clk: imx: add gatable clock divider support

* clk-imx6-fixes:
  clk: imx6q: handle ENET PLL bypass
  clk: imx6q: optionally get CCM inputs via standard clock handles
  clk: imx6q: reset exclusive gates on init

* clk-imx-fixes:
  clk: imx6q: add DCICx clocks gate
  clk: imx6sl: ensure MMDC CH0 handshake is bypassed
  clk: imx7d: remove UART1 clock setting

* clk-imx8qxp:
  clk: imx: add imx8qxp lpcg driver
  clk: imx: add lpcg clock support
  clk: imx: add imx8qxp clk driver
  clk: imx: add scu clock common part
  clk: imx: add configuration option for mmio clks
  dt-bindings: clock: add imx8qxp lpcg clock binding
  dt-bindings: clock: imx8qxp: add SCU clock IDs
  firmware: imx: add pm svc headfile
  dt-bindings: fsl: scu: update power domain binding
  firmware: imx: remove resource id enums
  dt-bindings: imx: add scu resource id headfile

* clk-imx8mq:
  clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant
  clk: imx: remove redundant initialization of ret to zero
  clk: imx: Add SCCG PLL type
  clk: imx: Add fractional PLL output clock
  clk: imx: Add clock driver for i.MX8MQ CCM
  clk: imx: Add imx composite clock
  dt-bindings: Add binding for i.MX8MQ CCM
This commit is contained in:
Stephen Boyd 2018-12-14 13:34:47 -08:00
commit 58c05c823b
41 changed files with 4996 additions and 609 deletions
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4
include/dt-bindings/clock/imx6qdl-clock.h
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@ -274,6 +274,8 @@
#define IMX6QDL_CLK_EPIT1 261
#define IMX6QDL_CLK_EPIT2 262
#define IMX6QDL_CLK_MMDC_P0_IPG 263
#define IMX6QDL_CLK_END 264
#define IMX6QDL_CLK_DCIC1 264
#define IMX6QDL_CLK_DCIC2 265
#define IMX6QDL_CLK_END 266
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

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include/dt-bindings/clock/imx7ulp-clock.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017~2018 NXP
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
#define __DT_BINDINGS_CLOCK_IMX7ULP_H
/* SCG1 */
#define IMX7ULP_CLK_DUMMY 0
#define IMX7ULP_CLK_ROSC 1
#define IMX7ULP_CLK_SOSC 2
#define IMX7ULP_CLK_FIRC 3
#define IMX7ULP_CLK_SPLL_PRE_SEL 4
#define IMX7ULP_CLK_SPLL_PRE_DIV 5
#define IMX7ULP_CLK_SPLL 6
#define IMX7ULP_CLK_SPLL_POST_DIV1 7
#define IMX7ULP_CLK_SPLL_POST_DIV2 8
#define IMX7ULP_CLK_SPLL_PFD0 9
#define IMX7ULP_CLK_SPLL_PFD1 10
#define IMX7ULP_CLK_SPLL_PFD2 11
#define IMX7ULP_CLK_SPLL_PFD3 12
#define IMX7ULP_CLK_SPLL_PFD_SEL 13
#define IMX7ULP_CLK_SPLL_SEL 14
#define IMX7ULP_CLK_APLL_PRE_SEL 15
#define IMX7ULP_CLK_APLL_PRE_DIV 16
#define IMX7ULP_CLK_APLL 17
#define IMX7ULP_CLK_APLL_POST_DIV1 18
#define IMX7ULP_CLK_APLL_POST_DIV2 19
#define IMX7ULP_CLK_APLL_PFD0 20
#define IMX7ULP_CLK_APLL_PFD1 21
#define IMX7ULP_CLK_APLL_PFD2 22
#define IMX7ULP_CLK_APLL_PFD3 23
#define IMX7ULP_CLK_APLL_PFD_SEL 24
#define IMX7ULP_CLK_APLL_SEL 25
#define IMX7ULP_CLK_UPLL 26
#define IMX7ULP_CLK_SYS_SEL 27
#define IMX7ULP_CLK_CORE_DIV 28
#define IMX7ULP_CLK_BUS_DIV 29
#define IMX7ULP_CLK_PLAT_DIV 30
#define IMX7ULP_CLK_DDR_SEL 31
#define IMX7ULP_CLK_DDR_DIV 32
#define IMX7ULP_CLK_NIC_SEL 33
#define IMX7ULP_CLK_NIC0_DIV 34
#define IMX7ULP_CLK_GPU_DIV 35
#define IMX7ULP_CLK_NIC1_DIV 36
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
#define IMX7ULP_CLK_MIPI_PLL 39
#define IMX7ULP_CLK_SIRC 40
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
#define IMX7ULP_CLK_FIRC_BUS_CLK 42
#define IMX7ULP_CLK_SPLL_BUS_CLK 43
#define IMX7ULP_CLK_SCG1_END 44
/* PCC2 */
#define IMX7ULP_CLK_DMA1 0
#define IMX7ULP_CLK_RGPIO2P1 1
#define IMX7ULP_CLK_FLEXBUS 2
#define IMX7ULP_CLK_SEMA42_1 3
#define IMX7ULP_CLK_DMA_MUX1 4
#define IMX7ULP_CLK_SNVS 5
#define IMX7ULP_CLK_CAAM 6
#define IMX7ULP_CLK_LPTPM4 7
#define IMX7ULP_CLK_LPTPM5 8
#define IMX7ULP_CLK_LPIT1 9
#define IMX7ULP_CLK_LPSPI2 10
#define IMX7ULP_CLK_LPSPI3 11
#define IMX7ULP_CLK_LPI2C4 12
#define IMX7ULP_CLK_LPI2C5 13
#define IMX7ULP_CLK_LPUART4 14
#define IMX7ULP_CLK_LPUART5 15
#define IMX7ULP_CLK_FLEXIO1 16
#define IMX7ULP_CLK_USB0 17
#define IMX7ULP_CLK_USB1 18
#define IMX7ULP_CLK_USB_PHY 19
#define IMX7ULP_CLK_USB_PL301 20
#define IMX7ULP_CLK_USDHC0 21
#define IMX7ULP_CLK_USDHC1 22
#define IMX7ULP_CLK_WDG1 23
#define IMX7ULP_CLK_WDG2 24
#define IMX7ULP_CLK_PCC2_END 25
/* PCC3 */
#define IMX7ULP_CLK_LPTPM6 0
#define IMX7ULP_CLK_LPTPM7 1
#define IMX7ULP_CLK_LPI2C6 2
#define IMX7ULP_CLK_LPI2C7 3
#define IMX7ULP_CLK_LPUART6 4
#define IMX7ULP_CLK_LPUART7 5
#define IMX7ULP_CLK_VIU 6
#define IMX7ULP_CLK_DSI 7
#define IMX7ULP_CLK_LCDIF 8
#define IMX7ULP_CLK_MMDC 9
#define IMX7ULP_CLK_PCTLC 10
#define IMX7ULP_CLK_PCTLD 11
#define IMX7ULP_CLK_PCTLE 12
#define IMX7ULP_CLK_PCTLF 13
#define IMX7ULP_CLK_GPU3D 14
#define IMX7ULP_CLK_GPU2D 15
#define IMX7ULP_CLK_PCC3_END 16
#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */

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include/dt-bindings/clock/imx8mq-clock.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
#define __DT_BINDINGS_CLOCK_IMX8MQ_H
#define IMX8MQ_CLK_DUMMY 0
#define IMX8MQ_CLK_32K 1
#define IMX8MQ_CLK_25M 2
#define IMX8MQ_CLK_27M 3
#define IMX8MQ_CLK_EXT1 4
#define IMX8MQ_CLK_EXT2 5
#define IMX8MQ_CLK_EXT3 6
#define IMX8MQ_CLK_EXT4 7
/* ANAMIX PLL clocks */
/* FRAC PLLs */
/* ARM PLL */
#define IMX8MQ_ARM_PLL_REF_SEL 8
#define IMX8MQ_ARM_PLL_REF_DIV 9
#define IMX8MQ_ARM_PLL 10
#define IMX8MQ_ARM_PLL_BYPASS 11
#define IMX8MQ_ARM_PLL_OUT 12
/* GPU PLL */
#define IMX8MQ_GPU_PLL_REF_SEL 13
#define IMX8MQ_GPU_PLL_REF_DIV 14
#define IMX8MQ_GPU_PLL 15
#define IMX8MQ_GPU_PLL_BYPASS 16
#define IMX8MQ_GPU_PLL_OUT 17
/* VPU PLL */
#define IMX8MQ_VPU_PLL_REF_SEL 18
#define IMX8MQ_VPU_PLL_REF_DIV 19
#define IMX8MQ_VPU_PLL 20
#define IMX8MQ_VPU_PLL_BYPASS 21
#define IMX8MQ_VPU_PLL_OUT 22
/* AUDIO PLL1 */
#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
#define IMX8MQ_AUDIO_PLL1 25
#define IMX8MQ_AUDIO_PLL1_BYPASS 26
#define IMX8MQ_AUDIO_PLL1_OUT 27
/* AUDIO PLL2 */
#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
#define IMX8MQ_AUDIO_PLL2 30
#define IMX8MQ_AUDIO_PLL2_BYPASS 31
#define IMX8MQ_AUDIO_PLL2_OUT 32
/* VIDEO PLL1 */
#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
#define IMX8MQ_VIDEO_PLL1 35
#define IMX8MQ_VIDEO_PLL1_BYPASS 36
#define IMX8MQ_VIDEO_PLL1_OUT 37
/* SYS1 PLL */
#define IMX8MQ_SYS1_PLL1_REF_SEL 38
#define IMX8MQ_SYS1_PLL1_REF_DIV 39
#define IMX8MQ_SYS1_PLL1 40
#define IMX8MQ_SYS1_PLL1_OUT 41
#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
#define IMX8MQ_SYS1_PLL2 43
#define IMX8MQ_SYS1_PLL2_DIV 44
#define IMX8MQ_SYS1_PLL2_OUT 45
/* SYS2 PLL */
#define IMX8MQ_SYS2_PLL1_REF_SEL 46
#define IMX8MQ_SYS2_PLL1_REF_DIV 47
#define IMX8MQ_SYS2_PLL1 48
#define IMX8MQ_SYS2_PLL1_OUT 49
#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
#define IMX8MQ_SYS2_PLL2 51
#define IMX8MQ_SYS2_PLL2_DIV 52
#define IMX8MQ_SYS2_PLL2_OUT 53
/* SYS3 PLL */
#define IMX8MQ_SYS3_PLL1_REF_SEL 54
#define IMX8MQ_SYS3_PLL1_REF_DIV 55
#define IMX8MQ_SYS3_PLL1 56
#define IMX8MQ_SYS3_PLL1_OUT 57
#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
#define IMX8MQ_SYS3_PLL2 59
#define IMX8MQ_SYS3_PLL2_DIV 60
#define IMX8MQ_SYS3_PLL2_OUT 61
/* DRAM PLL */
#define IMX8MQ_DRAM_PLL1_REF_SEL 62
#define IMX8MQ_DRAM_PLL1_REF_DIV 63
#define IMX8MQ_DRAM_PLL1 64
#define IMX8MQ_DRAM_PLL1_OUT 65
#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
#define IMX8MQ_DRAM_PLL2 67
#define IMX8MQ_DRAM_PLL2_DIV 68
#define IMX8MQ_DRAM_PLL2_OUT 69
/* SYS PLL DIV */
#define IMX8MQ_SYS1_PLL_40M 70
#define IMX8MQ_SYS1_PLL_80M 71
#define IMX8MQ_SYS1_PLL_100M 72
#define IMX8MQ_SYS1_PLL_133M 73
#define IMX8MQ_SYS1_PLL_160M 74
#define IMX8MQ_SYS1_PLL_200M 75
#define IMX8MQ_SYS1_PLL_266M 76
#define IMX8MQ_SYS1_PLL_400M 77
#define IMX8MQ_SYS1_PLL_800M 78
#define IMX8MQ_SYS2_PLL_50M 79
#define IMX8MQ_SYS2_PLL_100M 80
#define IMX8MQ_SYS2_PLL_125M 81
#define IMX8MQ_SYS2_PLL_166M 82
#define IMX8MQ_SYS2_PLL_200M 83
#define IMX8MQ_SYS2_PLL_250M 84
#define IMX8MQ_SYS2_PLL_333M 85
#define IMX8MQ_SYS2_PLL_500M 86
#define IMX8MQ_SYS2_PLL_1000M 87
/* CCM ROOT clocks */
/* A53 */
#define IMX8MQ_CLK_A53_SRC 88
#define IMX8MQ_CLK_A53_CG 89
#define IMX8MQ_CLK_A53_DIV 90
/* M4 */
#define IMX8MQ_CLK_M4_SRC 91
#define IMX8MQ_CLK_M4_CG 92
#define IMX8MQ_CLK_M4_DIV 93
/* VPU */
#define IMX8MQ_CLK_VPU_SRC 94
#define IMX8MQ_CLK_VPU_CG 95
#define IMX8MQ_CLK_VPU_DIV 96
/* GPU CORE */
#define IMX8MQ_CLK_GPU_CORE_SRC 97
#define IMX8MQ_CLK_GPU_CORE_CG 98
#define IMX8MQ_CLK_GPU_CORE_DIV 99
/* GPU SHADER */
#define IMX8MQ_CLK_GPU_SHADER_SRC 100
#define IMX8MQ_CLK_GPU_SHADER_CG 101
#define IMX8MQ_CLK_GPU_SHADER_DIV 102
/* BUS TYPE */
/* MAIN AXI */
#define IMX8MQ_CLK_MAIN_AXI 103
/* ENET AXI */
#define IMX8MQ_CLK_ENET_AXI 104
/* NAND_USDHC_BUS */
#define IMX8MQ_CLK_NAND_USDHC_BUS 105
/* VPU BUS */
#define IMX8MQ_CLK_VPU_BUS 106
/* DISP_AXI */
#define IMX8MQ_CLK_DISP_AXI 107
/* DISP APB */
#define IMX8MQ_CLK_DISP_APB 108
/* DISP RTRM */
#define IMX8MQ_CLK_DISP_RTRM 109
/* USB_BUS */
#define IMX8MQ_CLK_USB_BUS 110
/* GPU_AXI */
#define IMX8MQ_CLK_GPU_AXI 111
/* GPU_AHB */
#define IMX8MQ_CLK_GPU_AHB 112
/* NOC */
#define IMX8MQ_CLK_NOC 113
/* NOC_APB */
#define IMX8MQ_CLK_NOC_APB 115
/* AHB */
#define IMX8MQ_CLK_AHB 116
/* AUDIO AHB */
#define IMX8MQ_CLK_AUDIO_AHB 117
/* DRAM_ALT */
#define IMX8MQ_CLK_DRAM_ALT 118
/* DRAM APB */
#define IMX8MQ_CLK_DRAM_APB 119
/* VPU_G1 */
#define IMX8MQ_CLK_VPU_G1 120
/* VPU_G2 */
#define IMX8MQ_CLK_VPU_G2 121
/* DISP_DTRC */
#define IMX8MQ_CLK_DISP_DTRC 122
/* DISP_DC8000 */
#define IMX8MQ_CLK_DISP_DC8000 123
/* PCIE_CTRL */
#define IMX8MQ_CLK_PCIE1_CTRL 124
/* PCIE_PHY */
#define IMX8MQ_CLK_PCIE1_PHY 125
/* PCIE_AUX */
#define IMX8MQ_CLK_PCIE1_AUX 126
/* DC_PIXEL */
#define IMX8MQ_CLK_DC_PIXEL 127
/* LCDIF_PIXEL */
#define IMX8MQ_CLK_LCDIF_PIXEL 128
/* SAI1~6 */
#define IMX8MQ_CLK_SAI1 129
#define IMX8MQ_CLK_SAI2 130
#define IMX8MQ_CLK_SAI3 131
#define IMX8MQ_CLK_SAI4 132
#define IMX8MQ_CLK_SAI5 133
#define IMX8MQ_CLK_SAI6 134
/* SPDIF1 */
#define IMX8MQ_CLK_SPDIF1 135
/* SPDIF2 */
#define IMX8MQ_CLK_SPDIF2 136
/* ENET_REF */
#define IMX8MQ_CLK_ENET_REF 137
/* ENET_TIMER */
#define IMX8MQ_CLK_ENET_TIMER 138
/* ENET_PHY */
#define IMX8MQ_CLK_ENET_PHY_REF 139
/* NAND */
#define IMX8MQ_CLK_NAND 140
/* QSPI */
#define IMX8MQ_CLK_QSPI 141
/* USDHC1 */
#define IMX8MQ_CLK_USDHC1 142
/* USDHC2 */
#define IMX8MQ_CLK_USDHC2 143
/* I2C1 */
#define IMX8MQ_CLK_I2C1 144
/* I2C2 */
#define IMX8MQ_CLK_I2C2 145
/* I2C3 */
#define IMX8MQ_CLK_I2C3 146
/* I2C4 */
#define IMX8MQ_CLK_I2C4 147
/* UART1 */
#define IMX8MQ_CLK_UART1 148
/* UART2 */
#define IMX8MQ_CLK_UART2 149
/* UART3 */
#define IMX8MQ_CLK_UART3 150
/* UART4 */
#define IMX8MQ_CLK_UART4 151
/* USB_CORE_REF */
#define IMX8MQ_CLK_USB_CORE_REF 152
/* USB_PHY_REF */
#define IMX8MQ_CLK_USB_PHY_REF 163
/* ECSPI1 */
#define IMX8MQ_CLK_ECSPI1 164
/* ECSPI2 */
#define IMX8MQ_CLK_ECSPI2 165
/* PWM1 */
#define IMX8MQ_CLK_PWM1 166
/* PWM2 */
#define IMX8MQ_CLK_PWM2 167
/* PWM3 */
#define IMX8MQ_CLK_PWM3 168
/* PWM4 */
#define IMX8MQ_CLK_PWM4 169
/* GPT1 */
#define IMX8MQ_CLK_GPT1 170
/* WDOG */
#define IMX8MQ_CLK_WDOG 171
/* WRCLK */
#define IMX8MQ_CLK_WRCLK 172
/* DSI_CORE */
#define IMX8MQ_CLK_DSI_CORE 173
/* DSI_PHY */
#define IMX8MQ_CLK_DSI_PHY_REF 174
/* DSI_DBI */
#define IMX8MQ_CLK_DSI_DBI 175
/*DSI_ESC */
#define IMX8MQ_CLK_DSI_ESC 176
/* CSI1_CORE */
#define IMX8MQ_CLK_CSI1_CORE 177
/* CSI1_PHY */
#define IMX8MQ_CLK_CSI1_PHY_REF 178
/* CSI_ESC */
#define IMX8MQ_CLK_CSI1_ESC 179
/* CSI2_CORE */
#define IMX8MQ_CLK_CSI2_CORE 170
/* CSI2_PHY */
#define IMX8MQ_CLK_CSI2_PHY_REF 181
/* CSI2_ESC */
#define IMX8MQ_CLK_CSI2_ESC 182
/* PCIE2_CTRL */
#define IMX8MQ_CLK_PCIE2_CTRL 183
/* PCIE2_PHY */
#define IMX8MQ_CLK_PCIE2_PHY 184
/* PCIE2_AUX */
#define IMX8MQ_CLK_PCIE2_AUX 185
/* ECSPI3 */
#define IMX8MQ_CLK_ECSPI3 186
/* CCGR clocks */
#define IMX8MQ_CLK_A53_ROOT 187
#define IMX8MQ_CLK_DRAM_ROOT 188
#define IMX8MQ_CLK_ECSPI1_ROOT 189
#define IMX8MQ_CLK_ECSPI2_ROOT 180
#define IMX8MQ_CLK_ECSPI3_ROOT 181
#define IMX8MQ_CLK_ENET1_ROOT 182
#define IMX8MQ_CLK_GPT1_ROOT 193
#define IMX8MQ_CLK_I2C1_ROOT 194
#define IMX8MQ_CLK_I2C2_ROOT 195
#define IMX8MQ_CLK_I2C3_ROOT 196
#define IMX8MQ_CLK_I2C4_ROOT 197
#define IMX8MQ_CLK_M4_ROOT 198
#define IMX8MQ_CLK_PCIE1_ROOT 199
#define IMX8MQ_CLK_PCIE2_ROOT 200
#define IMX8MQ_CLK_PWM1_ROOT 201
#define IMX8MQ_CLK_PWM2_ROOT 202
#define IMX8MQ_CLK_PWM3_ROOT 203
#define IMX8MQ_CLK_PWM4_ROOT 204
#define IMX8MQ_CLK_QSPI_ROOT 205
#define IMX8MQ_CLK_SAI1_ROOT 206
#define IMX8MQ_CLK_SAI2_ROOT 207
#define IMX8MQ_CLK_SAI3_ROOT 208
#define IMX8MQ_CLK_SAI4_ROOT 209
#define IMX8MQ_CLK_SAI5_ROOT 210
#define IMX8MQ_CLK_SAI6_ROOT 212
#define IMX8MQ_CLK_UART1_ROOT 213
#define IMX8MQ_CLK_UART2_ROOT 214
#define IMX8MQ_CLK_UART3_ROOT 215
#define IMX8MQ_CLK_UART4_ROOT 216
#define IMX8MQ_CLK_USB1_CTRL_ROOT 217
#define IMX8MQ_CLK_USB2_CTRL_ROOT 218
#define IMX8MQ_CLK_USB1_PHY_ROOT 219
#define IMX8MQ_CLK_USB2_PHY_ROOT 220
#define IMX8MQ_CLK_USDHC1_ROOT 221
#define IMX8MQ_CLK_USDHC2_ROOT 222
#define IMX8MQ_CLK_WDOG1_ROOT 223
#define IMX8MQ_CLK_WDOG2_ROOT 224
#define IMX8MQ_CLK_WDOG3_ROOT 225
#define IMX8MQ_CLK_GPU_ROOT 226
#define IMX8MQ_CLK_HEVC_ROOT 227
#define IMX8MQ_CLK_AVC_ROOT 228
#define IMX8MQ_CLK_VP9_ROOT 229
#define IMX8MQ_CLK_HEVC_INTER_ROOT 230
#define IMX8MQ_CLK_DISP_ROOT 231
#define IMX8MQ_CLK_HDMI_ROOT 232
#define IMX8MQ_CLK_HDMI_PHY_ROOT 233
#define IMX8MQ_CLK_VPU_DEC_ROOT 234
#define IMX8MQ_CLK_CSI1_ROOT 235
#define IMX8MQ_CLK_CSI2_ROOT 236
#define IMX8MQ_CLK_RAWNAND_ROOT 237
#define IMX8MQ_CLK_SDMA1_ROOT 238
#define IMX8MQ_CLK_SDMA2_ROOT 239
#define IMX8MQ_CLK_VPU_G1_ROOT 240
#define IMX8MQ_CLK_VPU_G2_ROOT 241
/* SCCG PLL GATE */
#define IMX8MQ_SYS1_PLL_OUT 232
#define IMX8MQ_SYS2_PLL_OUT 243
#define IMX8MQ_SYS3_PLL_OUT 244
#define IMX8MQ_DRAM_PLL_OUT 245
#define IMX8MQ_GPT_3M_CLK 246
#define IMX8MQ_CLK_IPG_ROOT 247
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248
#define IMX8MQ_CLK_SAI1_IPG 249
#define IMX8MQ_CLK_SAI2_IPG 250
#define IMX8MQ_CLK_SAI3_IPG 251
#define IMX8MQ_CLK_SAI4_IPG 252
#define IMX8MQ_CLK_SAI5_IPG 253
#define IMX8MQ_CLK_SAI6_IPG 254
/* DSI AHB/IPG clocks */
/* rxesc clock */
#define IMX8MQ_CLK_DSI_AHB 255
/* txesc clock */
#define IMX8MQ_CLK_DSI_IPG_DIV 256
#define IMX8MQ_CLK_TMU_ROOT 265
/* Display root clocks */
#define IMX8MQ_CLK_DISP_AXI_ROOT 266
#define IMX8MQ_CLK_DISP_APB_ROOT 267
#define IMX8MQ_CLK_DISP_RTRM_ROOT 268
#define IMX8MQ_CLK_OCOTP_ROOT 269
#define IMX8MQ_CLK_DRAM_ALT_ROOT 270
#define IMX8MQ_CLK_DRAM_CORE 271
#define IMX8MQ_CLK_MU_ROOT 272
#define IMX8MQ_VIDEO2_PLL_OUT 273
#define IMX8MQ_CLK_CLKO2 274
#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275
#define IMX8MQ_CLK_END 276
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
#define __DT_BINDINGS_CLOCK_IMX8QXP_H
/* SCU Clocks */
#define IMX8QXP_CLK_DUMMY 0
/* CPU */
#define IMX8QXP_A35_CLK 1
/* LSIO SS */
#define IMX8QXP_LSIO_MEM_CLK 2
#define IMX8QXP_LSIO_BUS_CLK 3
#define IMX8QXP_LSIO_PWM0_CLK 10
#define IMX8QXP_LSIO_PWM1_CLK 11
#define IMX8QXP_LSIO_PWM2_CLK 12
#define IMX8QXP_LSIO_PWM3_CLK 13
#define IMX8QXP_LSIO_PWM4_CLK 14
#define IMX8QXP_LSIO_PWM5_CLK 15
#define IMX8QXP_LSIO_PWM6_CLK 16
#define IMX8QXP_LSIO_PWM7_CLK 17
#define IMX8QXP_LSIO_GPT0_CLK 18
#define IMX8QXP_LSIO_GPT1_CLK 19
#define IMX8QXP_LSIO_GPT2_CLK 20
#define IMX8QXP_LSIO_GPT3_CLK 21
#define IMX8QXP_LSIO_GPT4_CLK 22
#define IMX8QXP_LSIO_FSPI0_CLK 23
#define IMX8QXP_LSIO_FSPI1_CLK 24
/* Connectivity SS */
#define IMX8QXP_CONN_AXI_CLK_ROOT 30
#define IMX8QXP_CONN_AHB_CLK_ROOT 31
#define IMX8QXP_CONN_IPG_CLK_ROOT 32
#define IMX8QXP_CONN_SDHC0_CLK 40
#define IMX8QXP_CONN_SDHC1_CLK 41
#define IMX8QXP_CONN_SDHC2_CLK 42
#define IMX8QXP_CONN_ENET0_ROOT_CLK 43
#define IMX8QXP_CONN_ENET0_BYPASS_CLK 44
#define IMX8QXP_CONN_ENET0_RGMII_CLK 45
#define IMX8QXP_CONN_ENET1_ROOT_CLK 46
#define IMX8QXP_CONN_ENET1_BYPASS_CLK 47
#define IMX8QXP_CONN_ENET1_RGMII_CLK 48
#define IMX8QXP_CONN_GPMI_BCH_IO_CLK 49
#define IMX8QXP_CONN_GPMI_BCH_CLK 50
#define IMX8QXP_CONN_USB2_ACLK 51
#define IMX8QXP_CONN_USB2_BUS_CLK 52
#define IMX8QXP_CONN_USB2_LPM_CLK 53
/* HSIO SS */
#define IMX8QXP_HSIO_AXI_CLK 60
#define IMX8QXP_HSIO_PER_CLK 61
/* Display controller SS */
#define IMX8QXP_DC_AXI_EXT_CLK 70
#define IMX8QXP_DC_AXI_INT_CLK 71
#define IMX8QXP_DC_CFG_CLK 72
#define IMX8QXP_DC0_PLL0_CLK 80
#define IMX8QXP_DC0_PLL1_CLK 81
#define IMX8QXP_DC0_DISP0_CLK 82
#define IMX8QXP_DC0_DISP1_CLK 83
/* MIPI-LVDS SS */
#define IMX8QXP_MIPI_IPG_CLK 90
#define IMX8QXP_MIPI0_PIXEL_CLK 100
#define IMX8QXP_MIPI0_BYPASS_CLK 101
#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 102
#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 103
#define IMX8QXP_MIPI0_LVDS_PHY_CLK 104
#define IMX8QXP_MIPI0_I2C0_CLK 105
#define IMX8QXP_MIPI0_I2C1_CLK 106
#define IMX8QXP_MIPI0_PWM0_CLK 107
#define IMX8QXP_MIPI1_PIXEL_CLK 108
#define IMX8QXP_MIPI1_BYPASS_CLK 109
#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 110
#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 111
#define IMX8QXP_MIPI1_LVDS_PHY_CLK 112
#define IMX8QXP_MIPI1_I2C0_CLK 113
#define IMX8QXP_MIPI1_I2C1_CLK 114
#define IMX8QXP_MIPI1_PWM0_CLK 115
/* IMG SS */
#define IMX8QXP_IMG_AXI_CLK 120
#define IMX8QXP_IMG_IPG_CLK 121
#define IMX8QXP_IMG_PXL_CLK 122
/* MIPI-CSI SS */
#define IMX8QXP_CSI0_CORE_CLK 130
#define IMX8QXP_CSI0_ESC_CLK 131
#define IMX8QXP_CSI0_PWM0_CLK 132
#define IMX8QXP_CSI0_I2C0_CLK 133
/* PARALLER CSI SS */
#define IMX8QXP_PARALLEL_CSI_DPLL_CLK 140
#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 141
#define IMX8QXP_PARALLEL_CSI_MCLK_CLK 142
/* VPU SS */
#define IMX8QXP_VPU_ENC_CLK 150
#define IMX8QXP_VPU_DEC_CLK 151
/* GPU SS */
#define IMX8QXP_GPU0_CORE_CLK 160
#define IMX8QXP_GPU0_SHADER_CLK 161
/* ADMA SS */
#define IMX8QXP_ADMA_IPG_CLK_ROOT 165
#define IMX8QXP_ADMA_UART0_CLK 170
#define IMX8QXP_ADMA_UART1_CLK 171
#define IMX8QXP_ADMA_UART2_CLK 172
#define IMX8QXP_ADMA_UART3_CLK 173
#define IMX8QXP_ADMA_SPI0_CLK 174
#define IMX8QXP_ADMA_SPI1_CLK 175
#define IMX8QXP_ADMA_SPI2_CLK 176
#define IMX8QXP_ADMA_SPI3_CLK 177
#define IMX8QXP_ADMA_CAN0_CLK 178
#define IMX8QXP_ADMA_CAN1_CLK 179
#define IMX8QXP_ADMA_CAN2_CLK 180
#define IMX8QXP_ADMA_I2C0_CLK 181
#define IMX8QXP_ADMA_I2C1_CLK 182
#define IMX8QXP_ADMA_I2C2_CLK 183
#define IMX8QXP_ADMA_I2C3_CLK 184
#define IMX8QXP_ADMA_FTM0_CLK 185
#define IMX8QXP_ADMA_FTM1_CLK 186
#define IMX8QXP_ADMA_ADC0_CLK 187
#define IMX8QXP_ADMA_PWM_CLK 188
#define IMX8QXP_ADMA_LCD_CLK 189
#define IMX8QXP_SCU_CLK_END 190
/* LPCG clocks */
/* LSIO SS LPCG */
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_CLK 0
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_S_CLK 1
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_HF_CLK 2
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_CLK 5
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_S_CLK 6
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_HF_CLK 7
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_CLK 10
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_S_CLK 11
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_HF_CLK 12
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_CLK 15
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_S_CLK 16
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_HF_CLK 17
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_CLK 20
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_S_CLK 21
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_HF_CLK 22
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_CLK 25
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_S_CLK 26
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_HF_CLK 27
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_CLK 30
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_S_CLK 31
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_HF_CLK 32
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_CLK 35
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_S_CLK 36
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_HF_CLK 37
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_CLK 40
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_S_CLK 41
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_HF_CLK 42
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_CLK 45
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_S_CLK 46
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_HF_CLK 47
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_CLK 50
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_S_CLK 51
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_HF_CLK 52
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
#define IMX8QXP_LSIO_LPCG_GPT3_IPG_CLK 55
#define IMX8QXP_LSIO_LPCG_GPT3_IPG_S_CLK 56
#define IMX8QXP_LSIO_LPCG_GPT3_IPG_HF_CLK 57
#define IMX8QXP_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
#define IMX8QXP_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
#define IMX8QXP_LSIO_LPCG_GPT4_IPG_CLK 60
#define IMX8QXP_LSIO_LPCG_GPT4_IPG_S_CLK 61
#define IMX8QXP_LSIO_LPCG_GPT4_IPG_HF_CLK 62
#define IMX8QXP_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
#define IMX8QXP_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
#define IMX8QXP_LSIO_LPCG_FSPI0_HCLK 65
#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_CLK 66
#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_S_CLK 67
#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_SFCK 68
#define IMX8QXP_LSIO_LPCG_FSPI1_HCLK 69
#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_CLK 70
#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_S_CLK 71
#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_SFCK 72
#define IMX8QXP_LSIO_LPCG_CLK_END 73
/* Connectivity SS LPCG */
#define IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK 0
#define IMX8QXP_CONN_LPCG_SDHC0_PER_CLK 1
#define IMX8QXP_CONN_LPCG_SDHC0_HCLK 2
#define IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK 3
#define IMX8QXP_CONN_LPCG_SDHC1_PER_CLK 4
#define IMX8QXP_CONN_LPCG_SDHC1_HCLK 5
#define IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK 6
#define IMX8QXP_CONN_LPCG_SDHC2_PER_CLK 7
#define IMX8QXP_CONN_LPCG_SDHC2_HCLK 8
#define IMX8QXP_CONN_LPCG_GPMI_APB_CLK 9
#define IMX8QXP_CONN_LPCG_GPMI_BCH_APB_CLK 10
#define IMX8QXP_CONN_LPCG_GPMI_BCH_IO_CLK 11
#define IMX8QXP_CONN_LPCG_GPMI_BCH_CLK 12
#define IMX8QXP_CONN_LPCG_APBHDMA_CLK 13
#define IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK 14
#define IMX8QXP_CONN_LPCG_ENET0_TX_CLK 15
#define IMX8QXP_CONN_LPCG_ENET0_AHB_CLK 16
#define IMX8QXP_CONN_LPCG_ENET0_IPG_S_CLK 17
#define IMX8QXP_CONN_LPCG_ENET0_IPG_CLK 18
#define IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK 19
#define IMX8QXP_CONN_LPCG_ENET1_TX_CLK 20
#define IMX8QXP_CONN_LPCG_ENET1_AHB_CLK 21
#define IMX8QXP_CONN_LPCG_ENET1_IPG_S_CLK 22
#define IMX8QXP_CONN_LPCG_ENET1_IPG_CLK 23
#define IMX8QXP_CONN_LPCG_CLK_END 24
/* ADMA SS LPCG */
#define IMX8QXP_ADMA_LPCG_UART0_IPG_CLK 0
#define IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK 1
#define IMX8QXP_ADMA_LPCG_UART1_IPG_CLK 2
#define IMX8QXP_ADMA_LPCG_UART1_BAUD_CLK 3
#define IMX8QXP_ADMA_LPCG_UART2_IPG_CLK 4
#define IMX8QXP_ADMA_LPCG_UART2_BAUD_CLK 5
#define IMX8QXP_ADMA_LPCG_UART3_IPG_CLK 6
#define IMX8QXP_ADMA_LPCG_UART3_BAUD_CLK 7
#define IMX8QXP_ADMA_LPCG_SPI0_IPG_CLK 8
#define IMX8QXP_ADMA_LPCG_SPI1_IPG_CLK 9
#define IMX8QXP_ADMA_LPCG_SPI2_IPG_CLK 10
#define IMX8QXP_ADMA_LPCG_SPI3_IPG_CLK 11
#define IMX8QXP_ADMA_LPCG_SPI0_CLK 12
#define IMX8QXP_ADMA_LPCG_SPI1_CLK 13
#define IMX8QXP_ADMA_LPCG_SPI2_CLK 14
#define IMX8QXP_ADMA_LPCG_SPI3_CLK 15
#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CLK 16
#define IMX8QXP_ADMA_LPCG_CAN0_IPG_PE_CLK 17
#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CLK 19
#define IMX8QXP_ADMA_LPCG_CAN1_IPG_PE_CLK 20
#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CLK 22
#define IMX8QXP_ADMA_LPCG_CAN2_IPG_PE_CLK 23
#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
#define IMX8QXP_ADMA_LPCG_I2C0_CLK 25
#define IMX8QXP_ADMA_LPCG_I2C1_CLK 26
#define IMX8QXP_ADMA_LPCG_I2C2_CLK 27
#define IMX8QXP_ADMA_LPCG_I2C3_CLK 28
#define IMX8QXP_ADMA_LPCG_I2C0_IPG_CLK 29
#define IMX8QXP_ADMA_LPCG_I2C1_IPG_CLK 30
#define IMX8QXP_ADMA_LPCG_I2C2_IPG_CLK 31
#define IMX8QXP_ADMA_LPCG_I2C3_IPG_CLK 32
#define IMX8QXP_ADMA_LPCG_FTM0_CLK 33
#define IMX8QXP_ADMA_LPCG_FTM1_CLK 34
#define IMX8QXP_ADMA_LPCG_FTM0_IPG_CLK 35
#define IMX8QXP_ADMA_LPCG_FTM1_IPG_CLK 36
#define IMX8QXP_ADMA_LPCG_PWM_HI_CLK 37
#define IMX8QXP_ADMA_LPCG_PWM_IPG_CLK 38
#define IMX8QXP_ADMA_LPCG_LCD_PIX_CLK 39
#define IMX8QXP_ADMA_LPCG_LCD_APB_CLK 40
#define IMX8QXP_ADMA_LPCG_CLK_END 41
#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */

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include/dt-bindings/firmware/imx/rsrc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP
*/
#ifndef __DT_BINDINGS_RSCRC_IMX_H
#define __DT_BINDINGS_RSCRC_IMX_H
/*
* These defines are used to indicate a resource. Resources include peripherals
* and bus masters (but not memory regions). Note items from list should
* never be changed or removed (only added to at the end of the list).
*/
#define IMX_SC_R_A53 0
#define IMX_SC_R_A53_0 1
#define IMX_SC_R_A53_1 2
#define IMX_SC_R_A53_2 3
#define IMX_SC_R_A53_3 4
#define IMX_SC_R_A72 5
#define IMX_SC_R_A72_0 6
#define IMX_SC_R_A72_1 7
#define IMX_SC_R_A72_2 8
#define IMX_SC_R_A72_3 9
#define IMX_SC_R_CCI 10
#define IMX_SC_R_DB 11
#define IMX_SC_R_DRC_0 12
#define IMX_SC_R_DRC_1 13
#define IMX_SC_R_GIC_SMMU 14
#define IMX_SC_R_IRQSTR_M4_0 15
#define IMX_SC_R_IRQSTR_M4_1 16
#define IMX_SC_R_SMMU 17
#define IMX_SC_R_GIC 18
#define IMX_SC_R_DC_0_BLIT0 19
#define IMX_SC_R_DC_0_BLIT1 20
#define IMX_SC_R_DC_0_BLIT2 21
#define IMX_SC_R_DC_0_BLIT_OUT 22
#define IMX_SC_R_DC_0_CAPTURE0 23
#define IMX_SC_R_DC_0_CAPTURE1 24
#define IMX_SC_R_DC_0_WARP 25
#define IMX_SC_R_DC_0_INTEGRAL0 26
#define IMX_SC_R_DC_0_INTEGRAL1 27
#define IMX_SC_R_DC_0_VIDEO0 28
#define IMX_SC_R_DC_0_VIDEO1 29
#define IMX_SC_R_DC_0_FRAC0 30
#define IMX_SC_R_DC_0_FRAC1 31
#define IMX_SC_R_DC_0 32
#define IMX_SC_R_GPU_2_PID0 33
#define IMX_SC_R_DC_0_PLL_0 34
#define IMX_SC_R_DC_0_PLL_1 35
#define IMX_SC_R_DC_1_BLIT0 36
#define IMX_SC_R_DC_1_BLIT1 37
#define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39
#define IMX_SC_R_DC_1_CAPTURE0 40
#define IMX_SC_R_DC_1_CAPTURE1 41
#define IMX_SC_R_DC_1_WARP 42
#define IMX_SC_R_DC_1_INTEGRAL0 43
#define IMX_SC_R_DC_1_INTEGRAL1 44
#define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47
#define IMX_SC_R_DC_1_FRAC1 48
#define IMX_SC_R_DC_1 49
#define IMX_SC_R_GPU_3_PID0 50
#define IMX_SC_R_DC_1_PLL_0 51
#define IMX_SC_R_DC_1_PLL_1 52
#define IMX_SC_R_SPI_0 53
#define IMX_SC_R_SPI_1 54
#define IMX_SC_R_SPI_2 55
#define IMX_SC_R_SPI_3 56
#define IMX_SC_R_UART_0 57
#define IMX_SC_R_UART_1 58
#define IMX_SC_R_UART_2 59
#define IMX_SC_R_UART_3 60
#define IMX_SC_R_UART_4 61
#define IMX_SC_R_EMVSIM_0 62
#define IMX_SC_R_EMVSIM_1 63
#define IMX_SC_R_DMA_0_CH0 64
#define IMX_SC_R_DMA_0_CH1 65
#define IMX_SC_R_DMA_0_CH2 66
#define IMX_SC_R_DMA_0_CH3 67
#define IMX_SC_R_DMA_0_CH4 68
#define IMX_SC_R_DMA_0_CH5 69
#define IMX_SC_R_DMA_0_CH6 70
#define IMX_SC_R_DMA_0_CH7 71
#define IMX_SC_R_DMA_0_CH8 72
#define IMX_SC_R_DMA_0_CH9 73
#define IMX_SC_R_DMA_0_CH10 74
#define IMX_SC_R_DMA_0_CH11 75
#define IMX_SC_R_DMA_0_CH12 76
#define IMX_SC_R_DMA_0_CH13 77
#define IMX_SC_R_DMA_0_CH14 78
#define IMX_SC_R_DMA_0_CH15 79
#define IMX_SC_R_DMA_0_CH16 80
#define IMX_SC_R_DMA_0_CH17 81
#define IMX_SC_R_DMA_0_CH18 82
#define IMX_SC_R_DMA_0_CH19 83
#define IMX_SC_R_DMA_0_CH20 84
#define IMX_SC_R_DMA_0_CH21 85
#define IMX_SC_R_DMA_0_CH22 86
#define IMX_SC_R_DMA_0_CH23 87
#define IMX_SC_R_DMA_0_CH24 88
#define IMX_SC_R_DMA_0_CH25 89
#define IMX_SC_R_DMA_0_CH26 90
#define IMX_SC_R_DMA_0_CH27 91
#define IMX_SC_R_DMA_0_CH28 92
#define IMX_SC_R_DMA_0_CH29 93
#define IMX_SC_R_DMA_0_CH30 94
#define IMX_SC_R_DMA_0_CH31 95
#define IMX_SC_R_I2C_0 96
#define IMX_SC_R_I2C_1 97
#define IMX_SC_R_I2C_2 98
#define IMX_SC_R_I2C_3 99
#define IMX_SC_R_I2C_4 100
#define IMX_SC_R_ADC_0 101
#define IMX_SC_R_ADC_1 102
#define IMX_SC_R_FTM_0 103
#define IMX_SC_R_FTM_1 104
#define IMX_SC_R_CAN_0 105
#define IMX_SC_R_CAN_1 106
#define IMX_SC_R_CAN_2 107
#define IMX_SC_R_DMA_1_CH0 108
#define IMX_SC_R_DMA_1_CH1 109
#define IMX_SC_R_DMA_1_CH2 110
#define IMX_SC_R_DMA_1_CH3 111
#define IMX_SC_R_DMA_1_CH4 112
#define IMX_SC_R_DMA_1_CH5 113
#define IMX_SC_R_DMA_1_CH6 114
#define IMX_SC_R_DMA_1_CH7 115
#define IMX_SC_R_DMA_1_CH8 116
#define IMX_SC_R_DMA_1_CH9 117
#define IMX_SC_R_DMA_1_CH10 118
#define IMX_SC_R_DMA_1_CH11 119
#define IMX_SC_R_DMA_1_CH12 120
#define IMX_SC_R_DMA_1_CH13 121
#define IMX_SC_R_DMA_1_CH14 122
#define IMX_SC_R_DMA_1_CH15 123
#define IMX_SC_R_DMA_1_CH16 124
#define IMX_SC_R_DMA_1_CH17 125
#define IMX_SC_R_DMA_1_CH18 126
#define IMX_SC_R_DMA_1_CH19 127
#define IMX_SC_R_DMA_1_CH20 128
#define IMX_SC_R_DMA_1_CH21 129
#define IMX_SC_R_DMA_1_CH22 130
#define IMX_SC_R_DMA_1_CH23 131
#define IMX_SC_R_DMA_1_CH24 132
#define IMX_SC_R_DMA_1_CH25 133
#define IMX_SC_R_DMA_1_CH26 134
#define IMX_SC_R_DMA_1_CH27 135
#define IMX_SC_R_DMA_1_CH28 136
#define IMX_SC_R_DMA_1_CH29 137
#define IMX_SC_R_DMA_1_CH30 138
#define IMX_SC_R_DMA_1_CH31 139
#define IMX_SC_R_UNUSED1 140
#define IMX_SC_R_UNUSED2 141
#define IMX_SC_R_UNUSED3 142
#define IMX_SC_R_UNUSED4 143
#define IMX_SC_R_GPU_0_PID0 144
#define IMX_SC_R_GPU_0_PID1 145
#define IMX_SC_R_GPU_0_PID2 146
#define IMX_SC_R_GPU_0_PID3 147
#define IMX_SC_R_GPU_1_PID0 148
#define IMX_SC_R_GPU_1_PID1 149
#define IMX_SC_R_GPU_1_PID2 150
#define IMX_SC_R_GPU_1_PID3 151
#define IMX_SC_R_PCIE_A 152
#define IMX_SC_R_SERDES_0 153
#define IMX_SC_R_MATCH_0 154
#define IMX_SC_R_MATCH_1 155
#define IMX_SC_R_MATCH_2 156
#define IMX_SC_R_MATCH_3 157
#define IMX_SC_R_MATCH_4 158
#define IMX_SC_R_MATCH_5 159
#define IMX_SC_R_MATCH_6 160
#define IMX_SC_R_MATCH_7 161
#define IMX_SC_R_MATCH_8 162
#define IMX_SC_R_MATCH_9 163
#define IMX_SC_R_MATCH_10 164
#define IMX_SC_R_MATCH_11 165
#define IMX_SC_R_MATCH_12 166
#define IMX_SC_R_MATCH_13 167
#define IMX_SC_R_MATCH_14 168
#define IMX_SC_R_PCIE_B 169
#define IMX_SC_R_SATA_0 170
#define IMX_SC_R_SERDES_1 171
#define IMX_SC_R_HSIO_GPIO 172
#define IMX_SC_R_MATCH_15 173
#define IMX_SC_R_MATCH_16 174
#define IMX_SC_R_MATCH_17 175
#define IMX_SC_R_MATCH_18 176
#define IMX_SC_R_MATCH_19 177
#define IMX_SC_R_MATCH_20 178
#define IMX_SC_R_MATCH_21 179
#define IMX_SC_R_MATCH_22 180
#define IMX_SC_R_MATCH_23 181
#define IMX_SC_R_MATCH_24 182
#define IMX_SC_R_MATCH_25 183
#define IMX_SC_R_MATCH_26 184
#define IMX_SC_R_MATCH_27 185
#define IMX_SC_R_MATCH_28 186
#define IMX_SC_R_LCD_0 187
#define IMX_SC_R_LCD_0_PWM_0 188
#define IMX_SC_R_LCD_0_I2C_0 189
#define IMX_SC_R_LCD_0_I2C_1 190
#define IMX_SC_R_PWM_0 191
#define IMX_SC_R_PWM_1 192
#define IMX_SC_R_PWM_2 193
#define IMX_SC_R_PWM_3 194
#define IMX_SC_R_PWM_4 195
#define IMX_SC_R_PWM_5 196
#define IMX_SC_R_PWM_6 197
#define IMX_SC_R_PWM_7 198
#define IMX_SC_R_GPIO_0 199
#define IMX_SC_R_GPIO_1 200
#define IMX_SC_R_GPIO_2 201
#define IMX_SC_R_GPIO_3 202
#define IMX_SC_R_GPIO_4 203
#define IMX_SC_R_GPIO_5 204
#define IMX_SC_R_GPIO_6 205
#define IMX_SC_R_GPIO_7 206
#define IMX_SC_R_GPT_0 207
#define IMX_SC_R_GPT_1 208
#define IMX_SC_R_GPT_2 209
#define IMX_SC_R_GPT_3 210
#define IMX_SC_R_GPT_4 211
#define IMX_SC_R_KPP 212
#define IMX_SC_R_MU_0A 213
#define IMX_SC_R_MU_1A 214
#define IMX_SC_R_MU_2A 215
#define IMX_SC_R_MU_3A 216
#define IMX_SC_R_MU_4A 217
#define IMX_SC_R_MU_5A 218
#define IMX_SC_R_MU_6A 219
#define IMX_SC_R_MU_7A 220
#define IMX_SC_R_MU_8A 221
#define IMX_SC_R_MU_9A 222
#define IMX_SC_R_MU_10A 223
#define IMX_SC_R_MU_11A 224
#define IMX_SC_R_MU_12A 225
#define IMX_SC_R_MU_13A 226
#define IMX_SC_R_MU_5B 227
#define IMX_SC_R_MU_6B 228
#define IMX_SC_R_MU_7B 229
#define IMX_SC_R_MU_8B 230
#define IMX_SC_R_MU_9B 231
#define IMX_SC_R_MU_10B 232
#define IMX_SC_R_MU_11B 233
#define IMX_SC_R_MU_12B 234
#define IMX_SC_R_MU_13B 235
#define IMX_SC_R_ROM_0 236
#define IMX_SC_R_FSPI_0 237
#define IMX_SC_R_FSPI_1 238
#define IMX_SC_R_IEE 239
#define IMX_SC_R_IEE_R0 240
#define IMX_SC_R_IEE_R1 241
#define IMX_SC_R_IEE_R2 242
#define IMX_SC_R_IEE_R3 243
#define IMX_SC_R_IEE_R4 244
#define IMX_SC_R_IEE_R5 245
#define IMX_SC_R_IEE_R6 246
#define IMX_SC_R_IEE_R7 247
#define IMX_SC_R_SDHC_0 248
#define IMX_SC_R_SDHC_1 249
#define IMX_SC_R_SDHC_2 250
#define IMX_SC_R_ENET_0 251
#define IMX_SC_R_ENET_1 252
#define IMX_SC_R_MLB_0 253
#define IMX_SC_R_DMA_2_CH0 254
#define IMX_SC_R_DMA_2_CH1 255
#define IMX_SC_R_DMA_2_CH2 256
#define IMX_SC_R_DMA_2_CH3 257
#define IMX_SC_R_DMA_2_CH4 258
#define IMX_SC_R_USB_0 259
#define IMX_SC_R_USB_1 260
#define IMX_SC_R_USB_0_PHY 261
#define IMX_SC_R_USB_2 262
#define IMX_SC_R_USB_2_PHY 263
#define IMX_SC_R_DTCP 264
#define IMX_SC_R_NAND 265
#define IMX_SC_R_LVDS_0 266
#define IMX_SC_R_LVDS_0_PWM_0 267
#define IMX_SC_R_LVDS_0_I2C_0 268
#define IMX_SC_R_LVDS_0_I2C_1 269
#define IMX_SC_R_LVDS_1 270
#define IMX_SC_R_LVDS_1_PWM_0 271
#define IMX_SC_R_LVDS_1_I2C_0 272
#define IMX_SC_R_LVDS_1_I2C_1 273
#define IMX_SC_R_LVDS_2 274
#define IMX_SC_R_LVDS_2_PWM_0 275
#define IMX_SC_R_LVDS_2_I2C_0 276
#define IMX_SC_R_LVDS_2_I2C_1 277
#define IMX_SC_R_M4_0_PID0 278
#define IMX_SC_R_M4_0_PID1 279
#define IMX_SC_R_M4_0_PID2 280
#define IMX_SC_R_M4_0_PID3 281
#define IMX_SC_R_M4_0_PID4 282
#define IMX_SC_R_M4_0_RGPIO 283
#define IMX_SC_R_M4_0_SEMA42 284
#define IMX_SC_R_M4_0_TPM 285
#define IMX_SC_R_M4_0_PIT 286
#define IMX_SC_R_M4_0_UART 287
#define IMX_SC_R_M4_0_I2C 288
#define IMX_SC_R_M4_0_INTMUX 289
#define IMX_SC_R_M4_0_SIM 290
#define IMX_SC_R_M4_0_WDOG 291
#define IMX_SC_R_M4_0_MU_0B 292
#define IMX_SC_R_M4_0_MU_0A0 293
#define IMX_SC_R_M4_0_MU_0A1 294
#define IMX_SC_R_M4_0_MU_0A2 295
#define IMX_SC_R_M4_0_MU_0A3 296
#define IMX_SC_R_M4_0_MU_1A 297
#define IMX_SC_R_M4_1_PID0 298
#define IMX_SC_R_M4_1_PID1 299
#define IMX_SC_R_M4_1_PID2 300
#define IMX_SC_R_M4_1_PID3 301
#define IMX_SC_R_M4_1_PID4 302
#define IMX_SC_R_M4_1_RGPIO 303
#define IMX_SC_R_M4_1_SEMA42 304
#define IMX_SC_R_M4_1_TPM 305
#define IMX_SC_R_M4_1_PIT 306
#define IMX_SC_R_M4_1_UART 307
#define IMX_SC_R_M4_1_I2C 308
#define IMX_SC_R_M4_1_INTMUX 309
#define IMX_SC_R_M4_1_SIM 310
#define IMX_SC_R_M4_1_WDOG 311
#define IMX_SC_R_M4_1_MU_0B 312
#define IMX_SC_R_M4_1_MU_0A0 313
#define IMX_SC_R_M4_1_MU_0A1 314
#define IMX_SC_R_M4_1_MU_0A2 315
#define IMX_SC_R_M4_1_MU_0A3 316
#define IMX_SC_R_M4_1_MU_1A 317
#define IMX_SC_R_SAI_0 318
#define IMX_SC_R_SAI_1 319
#define IMX_SC_R_SAI_2 320
#define IMX_SC_R_IRQSTR_SCU2 321
#define IMX_SC_R_IRQSTR_DSP 322
#define IMX_SC_R_ELCDIF_PLL 323
#define IMX_SC_R_UNUSED6 324
#define IMX_SC_R_AUDIO_PLL_0 325
#define IMX_SC_R_PI_0 326
#define IMX_SC_R_PI_0_PWM_0 327
#define IMX_SC_R_PI_0_PWM_1 328
#define IMX_SC_R_PI_0_I2C_0 329
#define IMX_SC_R_PI_0_PLL 330
#define IMX_SC_R_PI_1 331
#define IMX_SC_R_PI_1_PWM_0 332
#define IMX_SC_R_PI_1_PWM_1 333
#define IMX_SC_R_PI_1_I2C_0 334
#define IMX_SC_R_PI_1_PLL 335
#define IMX_SC_R_SC_PID0 336
#define IMX_SC_R_SC_PID1 337
#define IMX_SC_R_SC_PID2 338
#define IMX_SC_R_SC_PID3 339
#define IMX_SC_R_SC_PID4 340
#define IMX_SC_R_SC_SEMA42 341
#define IMX_SC_R_SC_TPM 342
#define IMX_SC_R_SC_PIT 343
#define IMX_SC_R_SC_UART 344
#define IMX_SC_R_SC_I2C 345
#define IMX_SC_R_SC_MU_0B 346
#define IMX_SC_R_SC_MU_0A0 347
#define IMX_SC_R_SC_MU_0A1 348
#define IMX_SC_R_SC_MU_0A2 349
#define IMX_SC_R_SC_MU_0A3 350
#define IMX_SC_R_SC_MU_1A 351
#define IMX_SC_R_SYSCNT_RD 352
#define IMX_SC_R_SYSCNT_CMP 353
#define IMX_SC_R_DEBUG 354
#define IMX_SC_R_SYSTEM 355
#define IMX_SC_R_SNVS 356
#define IMX_SC_R_OTP 357
#define IMX_SC_R_VPU_PID0 358
#define IMX_SC_R_VPU_PID1 359
#define IMX_SC_R_VPU_PID2 360
#define IMX_SC_R_VPU_PID3 361
#define IMX_SC_R_VPU_PID4 362
#define IMX_SC_R_VPU_PID5 363
#define IMX_SC_R_VPU_PID6 364
#define IMX_SC_R_VPU_PID7 365
#define IMX_SC_R_VPU_UART 366
#define IMX_SC_R_VPUCORE 367
#define IMX_SC_R_VPUCORE_0 368
#define IMX_SC_R_VPUCORE_1 369
#define IMX_SC_R_VPUCORE_2 370
#define IMX_SC_R_VPUCORE_3 371
#define IMX_SC_R_DMA_4_CH0 372
#define IMX_SC_R_DMA_4_CH1 373
#define IMX_SC_R_DMA_4_CH2 374
#define IMX_SC_R_DMA_4_CH3 375
#define IMX_SC_R_DMA_4_CH4 376
#define IMX_SC_R_ISI_CH0 377
#define IMX_SC_R_ISI_CH1 378
#define IMX_SC_R_ISI_CH2 379
#define IMX_SC_R_ISI_CH3 380
#define IMX_SC_R_ISI_CH4 381
#define IMX_SC_R_ISI_CH5 382
#define IMX_SC_R_ISI_CH6 383
#define IMX_SC_R_ISI_CH7 384
#define IMX_SC_R_MJPEG_DEC_S0 385
#define IMX_SC_R_MJPEG_DEC_S1 386
#define IMX_SC_R_MJPEG_DEC_S2 387
#define IMX_SC_R_MJPEG_DEC_S3 388
#define IMX_SC_R_MJPEG_ENC_S0 389
#define IMX_SC_R_MJPEG_ENC_S1 390
#define IMX_SC_R_MJPEG_ENC_S2 391
#define IMX_SC_R_MJPEG_ENC_S3 392
#define IMX_SC_R_MIPI_0 393
#define IMX_SC_R_MIPI_0_PWM_0 394
#define IMX_SC_R_MIPI_0_I2C_0 395
#define IMX_SC_R_MIPI_0_I2C_1 396
#define IMX_SC_R_MIPI_1 397
#define IMX_SC_R_MIPI_1_PWM_0 398
#define IMX_SC_R_MIPI_1_I2C_0 399
#define IMX_SC_R_MIPI_1_I2C_1 400
#define IMX_SC_R_CSI_0 401
#define IMX_SC_R_CSI_0_PWM_0 402
#define IMX_SC_R_CSI_0_I2C_0 403
#define IMX_SC_R_CSI_1 404
#define IMX_SC_R_CSI_1_PWM_0 405
#define IMX_SC_R_CSI_1_I2C_0 406
#define IMX_SC_R_HDMI 407
#define IMX_SC_R_HDMI_I2S 408
#define IMX_SC_R_HDMI_I2C_0 409
#define IMX_SC_R_HDMI_PLL_0 410
#define IMX_SC_R_HDMI_RX 411
#define IMX_SC_R_HDMI_RX_BYPASS 412
#define IMX_SC_R_HDMI_RX_I2C_0 413
#define IMX_SC_R_ASRC_0 414
#define IMX_SC_R_ESAI_0 415
#define IMX_SC_R_SPDIF_0 416
#define IMX_SC_R_SPDIF_1 417
#define IMX_SC_R_SAI_3 418
#define IMX_SC_R_SAI_4 419
#define IMX_SC_R_SAI_5 420
#define IMX_SC_R_GPT_5 421
#define IMX_SC_R_GPT_6 422
#define IMX_SC_R_GPT_7 423
#define IMX_SC_R_GPT_8 424
#define IMX_SC_R_GPT_9 425
#define IMX_SC_R_GPT_10 426
#define IMX_SC_R_DMA_2_CH5 427
#define IMX_SC_R_DMA_2_CH6 428
#define IMX_SC_R_DMA_2_CH7 429
#define IMX_SC_R_DMA_2_CH8 430
#define IMX_SC_R_DMA_2_CH9 431
#define IMX_SC_R_DMA_2_CH10 432
#define IMX_SC_R_DMA_2_CH11 433
#define IMX_SC_R_DMA_2_CH12 434
#define IMX_SC_R_DMA_2_CH13 435
#define IMX_SC_R_DMA_2_CH14 436
#define IMX_SC_R_DMA_2_CH15 437
#define IMX_SC_R_DMA_2_CH16 438
#define IMX_SC_R_DMA_2_CH17 439
#define IMX_SC_R_DMA_2_CH18 440
#define IMX_SC_R_DMA_2_CH19 441
#define IMX_SC_R_DMA_2_CH20 442
#define IMX_SC_R_DMA_2_CH21 443
#define IMX_SC_R_DMA_2_CH22 444
#define IMX_SC_R_DMA_2_CH23 445
#define IMX_SC_R_DMA_2_CH24 446
#define IMX_SC_R_DMA_2_CH25 447
#define IMX_SC_R_DMA_2_CH26 448
#define IMX_SC_R_DMA_2_CH27 449
#define IMX_SC_R_DMA_2_CH28 450
#define IMX_SC_R_DMA_2_CH29 451
#define IMX_SC_R_DMA_2_CH30 452
#define IMX_SC_R_DMA_2_CH31 453
#define IMX_SC_R_ASRC_1 454
#define IMX_SC_R_ESAI_1 455
#define IMX_SC_R_SAI_6 456
#define IMX_SC_R_SAI_7 457
#define IMX_SC_R_AMIX 458
#define IMX_SC_R_MQS_0 459
#define IMX_SC_R_DMA_3_CH0 460
#define IMX_SC_R_DMA_3_CH1 461
#define IMX_SC_R_DMA_3_CH2 462
#define IMX_SC_R_DMA_3_CH3 463
#define IMX_SC_R_DMA_3_CH4 464
#define IMX_SC_R_DMA_3_CH5 465
#define IMX_SC_R_DMA_3_CH6 466
#define IMX_SC_R_DMA_3_CH7 467
#define IMX_SC_R_DMA_3_CH8 468
#define IMX_SC_R_DMA_3_CH9 469
#define IMX_SC_R_DMA_3_CH10 470
#define IMX_SC_R_DMA_3_CH11 471
#define IMX_SC_R_DMA_3_CH12 472
#define IMX_SC_R_DMA_3_CH13 473
#define IMX_SC_R_DMA_3_CH14 474
#define IMX_SC_R_DMA_3_CH15 475
#define IMX_SC_R_DMA_3_CH16 476
#define IMX_SC_R_DMA_3_CH17 477
#define IMX_SC_R_DMA_3_CH18 478
#define IMX_SC_R_DMA_3_CH19 479
#define IMX_SC_R_DMA_3_CH20 480
#define IMX_SC_R_DMA_3_CH21 481
#define IMX_SC_R_DMA_3_CH22 482
#define IMX_SC_R_DMA_3_CH23 483
#define IMX_SC_R_DMA_3_CH24 484
#define IMX_SC_R_DMA_3_CH25 485
#define IMX_SC_R_DMA_3_CH26 486
#define IMX_SC_R_DMA_3_CH27 487
#define IMX_SC_R_DMA_3_CH28 488
#define IMX_SC_R_DMA_3_CH29 489
#define IMX_SC_R_DMA_3_CH30 490
#define IMX_SC_R_DMA_3_CH31 491
#define IMX_SC_R_AUDIO_PLL_1 492
#define IMX_SC_R_AUDIO_CLK_0 493
#define IMX_SC_R_AUDIO_CLK_1 494
#define IMX_SC_R_MCLK_OUT_0 495
#define IMX_SC_R_MCLK_OUT_1 496
#define IMX_SC_R_PMIC_0 497
#define IMX_SC_R_PMIC_1 498
#define IMX_SC_R_SECO 499
#define IMX_SC_R_CAAM_JR1 500
#define IMX_SC_R_CAAM_JR2 501
#define IMX_SC_R_CAAM_JR3 502
#define IMX_SC_R_SECO_MU_2 503
#define IMX_SC_R_SECO_MU_3 504
#define IMX_SC_R_SECO_MU_4 505
#define IMX_SC_R_HDMI_RX_PWM_0 506
#define IMX_SC_R_A35 507
#define IMX_SC_R_A35_0 508
#define IMX_SC_R_A35_1 509
#define IMX_SC_R_A35_2 510
#define IMX_SC_R_A35_3 511
#define IMX_SC_R_DSP 512
#define IMX_SC_R_DSP_RAM 513
#define IMX_SC_R_CAAM_JR1_OUT 514
#define IMX_SC_R_CAAM_JR2_OUT 515
#define IMX_SC_R_CAAM_JR3_OUT 516
#define IMX_SC_R_VPU_DEC_0 517
#define IMX_SC_R_VPU_ENC_0 518
#define IMX_SC_R_CAAM_JR0 519
#define IMX_SC_R_CAAM_JR0_OUT 520
#define IMX_SC_R_PMIC_2 521
#define IMX_SC_R_DBLOGIC 522
#define IMX_SC_R_HDMI_PLL_1 523
#define IMX_SC_R_BOARD_R0 524
#define IMX_SC_R_BOARD_R1 525
#define IMX_SC_R_BOARD_R2 526
#define IMX_SC_R_BOARD_R3 527
#define IMX_SC_R_BOARD_R4 528
#define IMX_SC_R_BOARD_R5 529
#define IMX_SC_R_BOARD_R6 530
#define IMX_SC_R_BOARD_R7 531
#define IMX_SC_R_MJPEG_DEC_MP 532
#define IMX_SC_R_MJPEG_ENC_MP 533
#define IMX_SC_R_VPU_TS_0 534
#define IMX_SC_R_VPU_MU_0 535
#define IMX_SC_R_VPU_MU_1 536
#define IMX_SC_R_VPU_MU_2 537
#define IMX_SC_R_VPU_MU_3 538
#define IMX_SC_R_VPU_ENC_1 539
#define IMX_SC_R_VPU 540
#define IMX_SC_R_LAST 541
#endif /* __DT_BINDINGS_RSCRC_IMX_H */