From 58dc0605603efc1d80c6444808ca2ce93f6fcd4f Mon Sep 17 00:00:00 2001
From: Hemant Kumar <hemantk@quicinc.com>
Date: Thu, 16 Jul 2020 14:53:35 -0700
Subject: [PATCH] ARM: dts: msm: Enable L1SS sleep for Lahaina-v2.1

PCIe0 phy on v2.1 manages the phy PLL properly hence
remove the software workaround to keep the phy PLL
always on.

Change-Id: Ia32cebb53b6873b2c9f3b07299eb3208c5b5a77c
---
 qcom/lahaina-v2.1.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/qcom/lahaina-v2.1.dtsi b/qcom/lahaina-v2.1.dtsi
index a2153356e6ef..f3752b851370 100644
--- a/qcom/lahaina-v2.1.dtsi
+++ b/qcom/lahaina-v2.1.dtsi
@@ -7,6 +7,7 @@
 };
 
 &pcie0 {
+	qcom,l1ss-sleep-disable = <0x0>;
 	qcom,pcie-phy-ver = <21100>;
 	qcom,phy-sequence = <0x0240 0x03 0x0
 			0x0094 0x08 0x0