mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-07 04:12:04 -04:00
Merge tag 'LA.UM.9.14.r1-23100-LAHAINA.QSSI14.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api into android13-5.4-lahaina
"LA.UM.9.14.r1-23100-LAHAINA.QSSI14.0" * tag 'LA.UM.9.14.r1-23100-LAHAINA.QSSI14.0' of https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/fw-api: fw-api: CL 24698636 - update fw common interface files fw-api: CL 24632751 - update fw common interface files fw-api: CL 24632749 - update fw common interface files fw-api: CL 24610273 - update fw common interface files fw-api: CL 24620909 - update fw common interface files fw-api: CL 24602439 - update fw common interface files fw-api: Fix E3.0: E3R44: WCSS_VERSION 2544 fw-api: peach: E3.0: E3R44: WCSS_VERSION 2544 Add peach hw header files fw-api: CL 24551836 - update fw common interface files fw-api: CL 24528979 - update fw common interface files fw-api: CL 24448911 - update fw common interface files fw-api: CL 24431840 - update fw common interface files fw-api: CL 24431228 - update fw common interface files fw-api: CL 24417305 - update fw common interface files fw-api: CL 24374793 - update fw common interface files fw-api: CL 24331558 - update fw common interface files fw-api: CL 24317964 - update fw common interface files fw-api: CL 24309540 - update fw common interface files fw-api: CL 24285962 - update fw common interface files fw-api: CL 24269688 - update fw common interface files fw-api: CL 24263101 - update fw common interface files fw-api: CL 24263097 - update fw common interface files fw-api: CL 24258897 - update fw common interface files fw-api: CL 24245865 - update fw common interface files fw-api: CL 24229660 - update fw common interface files fw-api: CL 24140579 - update fw common interface files fw-api: CL 24056101 - update fw common interface files fw-api: CL 24006951 - update fw common interface files fw-api: CL 23998194 - update fw common interface files fw-api: CL 23995783 - update fw common interface files Change-Id: If415303aea607742517e252534a912670f476c84
This commit is contained in:
Michael Bestas
commit
5994fbf3ae
211 changed files with 50622 additions and 43 deletions
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@ -252,9 +252,12 @@
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* 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def.
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* 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2.
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* 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def.
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* 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs.
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* 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND
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* msg defs
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*/
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#define HTT_CURRENT_VERSION_MAJOR 3
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#define HTT_CURRENT_VERSION_MINOR 126
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#define HTT_CURRENT_VERSION_MINOR 128
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#define HTT_NUM_TX_FRAG_DESC 1024
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@ -808,6 +811,8 @@ typedef enum {
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HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */
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HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */
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HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */
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HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */
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HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */
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HTT_STATS_MAX_TAG,
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@ -880,6 +885,7 @@ enum htt_h2t_msg_type {
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HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22,
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HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23,
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HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24,
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HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25,
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/* keep this last */
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HTT_H2T_NUM_MSGS
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@ -2877,7 +2883,8 @@ PREPACK struct htt_tx_wbm_completion_v2 {
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tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
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reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
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exception_frame: 1,
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rsvd0: 12, /* For future use */
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transmit_count: 7, /* Refer to struct wbm_release_ring */
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rsvd0: 5, /* For future use */
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used_by_hw4: 1, /* wbm_internal_error bit being used by HW */
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rsvd1: 1; /* For future use */
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A_UINT32
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@ -2903,6 +2910,8 @@ PREPACK struct htt_tx_wbm_completion_v2 {
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#define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13
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#define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000
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#define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18
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/* DWORD 3 */
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#define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \
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@ -2935,6 +2944,16 @@ PREPACK struct htt_tx_wbm_completion_v2 {
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \
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} while (0)
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \
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(((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \
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HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \
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} while (0)
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/**
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* @brief HTT TX WBM Completion from firmware to host (V3)
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* @details
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@ -2960,7 +2979,8 @@ PREPACK struct htt_tx_wbm_completion_v3 {
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A_UINT32
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reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
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exception_frame: 1,
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rsvd0: 27; /* For future use */
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transmit_count: 7, /* Refer to struct wbm_release_ring */
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rsvd0: 20; /* For future use */
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A_UINT32
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data0: 32; /* data0,1 and 2 changes based on tx_status type
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* if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
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@ -2977,13 +2997,17 @@ PREPACK struct htt_tx_wbm_completion_v3 {
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used_by_hw4: 12; /* Refer to struct wbm_release_ring */
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} POSTPACK;
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/* DWORD 3 */
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#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000
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#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13
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/* DWORD 4 */
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#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F
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#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0
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#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010
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#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4
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#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0
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#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5
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#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \
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@ -3016,6 +3040,16 @@ PREPACK struct htt_tx_wbm_completion_v3 {
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \
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} while (0)
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#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \
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(((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \
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HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)
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#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \
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} while (0)
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typedef enum {
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TX_FRAME_TYPE_UNDEFINED = 0,
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@ -3056,7 +3090,11 @@ PREPACK struct htt_tx_wbm_transmit_status {
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* contains valid data.
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*/
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frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */
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reserved: 4;
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transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the
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* transmit_count field in struct
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* htt_tx_wbm_completion_vx has valid data.
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*/
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reserved: 3;
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A_UINT32
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ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast
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* packets in the wbm completion path
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@ -3080,6 +3118,10 @@ PREPACK struct htt_tx_wbm_transmit_status {
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#define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22
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#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000
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#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23
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#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000
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#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28
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/* DWORD 4 */
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#define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \
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@ -3153,6 +3195,26 @@ PREPACK struct htt_tx_wbm_transmit_status {
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \
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} while (0)
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#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \
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(((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \
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HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)
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#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \
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(((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \
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HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)
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#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \
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((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \
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} while (0)
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/**
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* @brief HTT TX WBM reinject status from firmware to host
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* @details
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@ -10715,6 +10777,88 @@ typedef struct {
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} while (0)
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/**
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* @brief host -> tgt msg to configure params for PPDU tx latency stats report
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*
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* MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG
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*
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* @details
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* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to
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* configure the parameters needed for FW to report PPDU tx latency stats
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* for latency prediction in user space.
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*
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* The message would appear as follows:
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* |31 28|27 12|11|10 8|7 0|
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* |-----------+-------------------+--+-------+--------------|
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* |granularity| periodic interval | E|vdev ID| msg type |
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* |-----------+-------------------+--+-------+--------------|
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* Where: E = enable
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*
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* The message is interpreted as follows:
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* dword0 - b'0:7 - msg_type: This will be set to 0x25
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* (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG)
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* b'8:10 - vdev_id: Indicate which vdev is configuration is for
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* b'11 - enable: Indicate this message is to enable/disable
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* PPDU latency report from FW
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* b'12:27 - periodic_interval: Indicate the report interval in MS
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* b'28:31 - granularity: Indicate the granularity of the latency
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* stats report, in ms
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*/
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/* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */
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PREPACK struct htt_h2t_tx_latency_stats_cfg {
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A_UINT32 msg_type :8,
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vdev_id :3,
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enable :1,
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periodic_interval :16,
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granularity :4;
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} POSTPACK;
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#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700
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#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8
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#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \
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(((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \
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HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \
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((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \
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} while (0)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800
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#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11
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#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \
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(((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \
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HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \
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((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \
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} while (0)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000
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#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12
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#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \
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(((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \
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HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \
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((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \
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} while (0)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000
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#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28
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#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \
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(((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \
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HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)
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#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \
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do { \
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HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \
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((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \
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} while (0)
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/*=== target -> host messages ===============================================*/
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@ -10785,6 +10929,7 @@ enum htt_t2h_msg_type {
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HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37,
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HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38,
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HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39,
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HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a,
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HTT_T2H_MSG_TYPE_TEST,
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@ -21932,5 +22077,141 @@ typedef struct {
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#define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16
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/**
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* @brief target -> periodic report of tx latency to host
|
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*
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* MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND
|
||||
*
|
||||
* @details
|
||||
* The message starts with a message header followed by one or more
|
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* htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev.
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* After each upload, these tx latency stats will be reset.
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*
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* |31 24|23 16|15 14|13 10|9 8|7 0|
|
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* +-------------------------+-----+-----+---+----------|
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||||
* hdr | |pyld elem sz| | GR | P | msg type |
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||||
*- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
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* pyld | peer ID |
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||||
* |----------------------------------------------------|
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||||
* | peer_tx_latency[0] |
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||||
* |----------------------------------------------------|
|
||||
* 1st | peer_tx_latency[1] |
|
||||
* peer |----------------------------------------------------|
|
||||
* | peer_tx_latency[2] |
|
||||
* |----------------------------------------------------|
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||||
* | peer_tx_latency[3] |
|
||||
* |----------------------------------------------------|
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* | avg latency |
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* |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
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* | peer ID |
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||||
* |----------------------------------------------------|
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||||
* | peer_tx_latency[0] |
|
||||
* |----------------------------------------------------|
|
||||
* 2nd | peer_tx_latency[1] |
|
||||
* peer |----------------------------------------------------|
|
||||
* | peer_tx_latency[2] |
|
||||
* |----------------------------------------------------|
|
||||
* | peer_tx_latency[3] |
|
||||
* |----------------------------------------------------|
|
||||
* | avg latency |
|
||||
* |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
|
||||
* Where:
|
||||
* P = pdev ID
|
||||
* GR = granularity
|
||||
*
|
||||
* @details
|
||||
* htt_t2h_tx_latency_stats_periodic_hdr_t:
|
||||
* - msg_type
|
||||
* Bits 7:0
|
||||
* Purpose: identifies this as a tx latency report message
|
||||
* Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND)
|
||||
* - pdev_id
|
||||
* Bits 9:8
|
||||
* Purpose: Indicates which pdev this message is associated with.
|
||||
* - granularity
|
||||
* Bits 13:10
|
||||
* Purpose: specifies the granulairty of each tx latency bucket in MS.
|
||||
* There are 4 buckets in total. E.g. if granularity is set to 5 ms,
|
||||
* then the ranges for the 4 latency histogram buckets will be
|
||||
* 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively.
|
||||
* - payload_elem_size
|
||||
* Bits 23:16
|
||||
* Purpose: specifies the size of each element within the msg's payload
|
||||
* In other words, this field specified the value of
|
||||
* sizeof(htt_t2h_peer_tx_latency_stats) based on the target's
|
||||
* revision of the htt_t2h_peer_tx_latency_stats definition.
|
||||
* If the payload_elem_size reported in the message exceeds the
|
||||
* sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
|
||||
* revision of the htt_t2h_peer_tx_latency_stats definition,
|
||||
* the host shall ignore the excess data.
|
||||
* Conversely, if the payload_elem_size reported in the message is
|
||||
* less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
|
||||
* revision of the htt_t2h_peer_tx_latency_stats definition,
|
||||
* the host shall use 0x0 values for the portion of the data not
|
||||
* provided by the target.
|
||||
* The host can compare the payload_elem_size to the total size of
|
||||
* the message minus the size of the message header to determine
|
||||
* how many peer payload elements are present in the message.
|
||||
* - sw_peer_id
|
||||
* Purpose: The peer to which the following stats belong
|
||||
* - peer_tx_latency
|
||||
* Purpose: tx latency histogram for this peer, with 4 buckets whose
|
||||
* size (in milliseconds) is specified by the granularity field
|
||||
* - avg_latency
|
||||
* Purpose: average tx latency (in ms) for this peer in this report interval
|
||||
*/
|
||||
typedef struct {
|
||||
A_UINT32 msg_type: 8,
|
||||
pdev_id: 2,
|
||||
granularity: 4,
|
||||
reserved1: 2,
|
||||
payload_elem_size: 8,
|
||||
reserved2: 8;
|
||||
} htt_t2h_tx_latency_stats_periodic_hdr_t;
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \
|
||||
(sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t))
|
||||
#define HTT_PEER_TX_LATENCY_REPORT_BINS 4
|
||||
|
||||
typedef struct _htt_tx_latency_stats {
|
||||
A_UINT32 peer_id;
|
||||
A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS];
|
||||
A_UINT32 avg_latency;
|
||||
} htt_t2h_peer_tx_latency_stats;
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \
|
||||
(((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \
|
||||
((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \
|
||||
(((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \
|
||||
((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16
|
||||
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \
|
||||
(((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)
|
||||
#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \
|
||||
((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \
|
||||
} while (0)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -583,6 +583,22 @@ enum htt_dbg_ext_stats_type {
|
|||
*/
|
||||
HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62,
|
||||
|
||||
/** HTT_DBG_MLO_SCHED_STATS
|
||||
* PARAMS:
|
||||
* - No Params
|
||||
* RESP MSG:
|
||||
* - htt_pdev_mlo_sched_stats_tlv
|
||||
*/
|
||||
HTT_DBG_MLO_SCHED_STATS = 63,
|
||||
|
||||
/** HTT_DBG_PDEV_MLO_IPC_STATS
|
||||
* PARAMS:
|
||||
* - No Params
|
||||
* RESP MSG:
|
||||
* - htt_pdev_mlo_ipc_stats_tlv
|
||||
*/
|
||||
HTT_DBG_PDEV_MLO_IPC_STATS = 64,
|
||||
|
||||
|
||||
/* keep this last */
|
||||
HTT_DBG_NUM_EXT_STATS = 256,
|
||||
|
|
@ -2622,6 +2638,14 @@ typedef struct {
|
|||
A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */
|
||||
A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE UL OFDMA Basic Trigger frames per AC */
|
||||
A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */
|
||||
A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU-BAR Trigger frames per AC */
|
||||
A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM];
|
||||
/** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */
|
||||
A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM];
|
||||
} htt_tx_selfgen_ax_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -2677,6 +2701,14 @@ typedef struct {
|
|||
A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */
|
||||
A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT UL OFDMA Basic Trigger frames per AC */
|
||||
A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */
|
||||
A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT MU-BAR Trigger frames per AC */
|
||||
A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM];
|
||||
/** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */
|
||||
A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM];
|
||||
} htt_tx_selfgen_be_stats_tlv;
|
||||
|
||||
typedef struct { /* DEPRECATED */
|
||||
|
|
@ -5675,6 +5707,12 @@ typedef struct {
|
|||
* response to basic trigger. Typically a data response is expected.
|
||||
*/
|
||||
A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only;
|
||||
|
||||
/* UL MLO Queue Depth Sharing Stats */
|
||||
A_UINT32 ul_mlo_send_qdepth_params_count;
|
||||
A_UINT32 ul_mlo_proc_qdepth_params_count;
|
||||
A_UINT32 ul_mlo_proc_accepted_qdepth_params_count;
|
||||
A_UINT32 ul_mlo_proc_discarded_qdepth_params_count;
|
||||
} htt_rx_pdev_be_ul_trigger_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
|
||||
|
|
@ -6275,6 +6313,7 @@ typedef struct {
|
|||
A_UINT32 med_rx_idle_usec;
|
||||
A_UINT32 med_tx_idle_global_usec;
|
||||
A_UINT32 cca_obss_usec;
|
||||
A_UINT32 pre_rx_frame_usec;
|
||||
} htt_pdev_stats_cca_counters_tlv;
|
||||
|
||||
/* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED,
|
||||
|
|
@ -7930,6 +7969,58 @@ typedef struct {
|
|||
/* Considering 320 MHz maximum 16 power levels */
|
||||
#define HTT_MAX_CH_PWR_INFO_SIZE 16
|
||||
|
||||
#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M 0x000000ff
|
||||
#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S 0
|
||||
|
||||
#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \
|
||||
(((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \
|
||||
HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)
|
||||
#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \
|
||||
((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \
|
||||
((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M 0x0000ff00
|
||||
#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S 8
|
||||
|
||||
#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \
|
||||
(((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \
|
||||
HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)
|
||||
#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \
|
||||
((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \
|
||||
((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M 0x00ff0000
|
||||
#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S 16
|
||||
|
||||
#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \
|
||||
(((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \
|
||||
HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)
|
||||
#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \
|
||||
((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \
|
||||
((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \
|
||||
} while (0)
|
||||
|
||||
#define HTT_PHY_TPC_STATS_CTL_FLAG_M 0xff000000
|
||||
#define HTT_PHY_TPC_STATS_CTL_FLAG_S 24
|
||||
|
||||
#define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \
|
||||
(((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \
|
||||
HTT_PHY_TPC_STATS_CTL_FLAG_S)
|
||||
#define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \
|
||||
do { \
|
||||
HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \
|
||||
((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \
|
||||
((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \
|
||||
} while (0)
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
|
||||
|
|
@ -7968,6 +8059,33 @@ typedef struct {
|
|||
/** sub-band channels and corresponding Tx-power */
|
||||
A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE];
|
||||
A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE];
|
||||
|
||||
/** array_gain_cap:
|
||||
* CTL Array Gain cap, units are dB
|
||||
* The lower-triangular portion of this square matrix is stored, i.e.
|
||||
* array element 0 stores matrix element (0,0)
|
||||
* array element 1 stores matrix element (1,0)
|
||||
* array element 2 stores matrix element (1,1)
|
||||
* array element 3 stores matrix element (2,0)
|
||||
* ...
|
||||
* array element 35 stores matrix element (7,7)
|
||||
*/
|
||||
A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)];
|
||||
union {
|
||||
struct {
|
||||
A_UINT32
|
||||
ctl_region_grp:8, /** Group to which the ctl region belongs */
|
||||
sub_band_index:8, /** Frequency subband index */
|
||||
/** Array Gain Cap Ext2 feature enablement status */
|
||||
array_gain_cap_ext2_enabled:8,
|
||||
/** ctl_flag:
|
||||
* 1st bit ULOFDMA supported
|
||||
* 2nd bit DLOFDMA shared Exception supported
|
||||
*/
|
||||
ctl_flag:8;
|
||||
};
|
||||
A_UINT32 ctl_args;
|
||||
};
|
||||
} htt_phy_tpc_stats_tlv;
|
||||
|
||||
/* NOTE:
|
||||
|
|
@ -8830,6 +8948,18 @@ typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv {
|
|||
((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \
|
||||
} while (0)
|
||||
|
||||
typedef enum {
|
||||
HTT_STATS_SCHED_OFDMA_TXBF = 0, /* 0 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED, /* 1 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED, /* 2 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT, /* 3 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT, /* 4 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT, /* 6 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID, /* 7 */
|
||||
HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX,
|
||||
} htt_stats_sched_ofdma_txbf_ineligibility_t;
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
/**
|
||||
|
|
@ -8872,6 +9002,7 @@ typedef struct {
|
|||
A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM];
|
||||
/** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */
|
||||
A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM];
|
||||
A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX];
|
||||
} htt_pdev_sched_algo_ofdma_stats_tlv;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -9763,4 +9894,129 @@ typedef struct {
|
|||
};
|
||||
} htt_codel_msduq_stats_tlv;
|
||||
|
||||
/*===================== start MLO stats ====================*/
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 pref_link_num_sec_link_sched;
|
||||
A_UINT32 pref_link_num_pref_link_timeout;
|
||||
A_UINT32 pref_link_num_pref_link_sch_delay_ipc;
|
||||
A_UINT32 pref_link_num_pref_link_timeout_ipc;
|
||||
} htt_mlo_sched_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS
|
||||
* TLV_TAGS:
|
||||
* - HTT_STATS_MLO_SCHED_STATS_TAG
|
||||
*/
|
||||
/* NOTE:
|
||||
* This structure is for documentation, and cannot be safely used directly.
|
||||
* Instead, use the constituent TLV structures to fill/parse.
|
||||
*/
|
||||
typedef struct _htt_mlo_sched_stats {
|
||||
htt_mlo_sched_stats_tlv preferred_link_stats;
|
||||
} htt_mlo_sched_stats_t;
|
||||
|
||||
#define HTT_STATS_HWMLO_MAX_LINKS 6
|
||||
#define HTT_STATS_MLO_MAX_IPC_RINGS 7
|
||||
|
||||
typedef struct {
|
||||
htt_tlv_hdr_t tlv_hdr;
|
||||
A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS];
|
||||
} htt_pdev_mlo_ipc_stats_tlv;
|
||||
|
||||
/* STATS_TYPE : HTT_DBG_MLO_IPC_STATS
|
||||
* TLV_TAGS:
|
||||
* - HTT_STATS_PDEV_MLO_IPC_STATS_TAG
|
||||
*/
|
||||
/* NOTE:
|
||||
* This structure is for documentation, and cannot be safely used directly.
|
||||
* Instead, use the constituent TLV structures to fill/parse.
|
||||
*/
|
||||
typedef struct _htt_mlo_ipc_stats {
|
||||
htt_pdev_mlo_ipc_stats_tlv mlo_ipc_stats;
|
||||
} htt_pdev_mlo_ipc_stats_t;
|
||||
|
||||
/*===================== end MLO stats ======================*/
|
||||
|
||||
typedef enum {
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_ADC = 0x0,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_DAC = 0x1,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS = 0x2,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR = 0x3,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO = 0x4,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ = 0x5,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO = 0x6,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ = 0x7,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ = 0x8,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_IM2 = 0x9,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_LNA = 0xa,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO = 0xb,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ = 0xc,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS = 0xd,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY = 0xe,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_IBF = 0xf,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL = 0x10,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ = 0x11,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM = 0x12,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL = 0x13,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ = 0x14,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER = 0x15,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17,
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18,
|
||||
|
||||
/* add new cal types above this line */
|
||||
HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF
|
||||
} htt_ctrl_path_stats_cal_type_ids;
|
||||
|
||||
#define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str);
|
||||
|
||||
#define HTT_GET_BITS(_val, _index, _num_bits) \
|
||||
(((_val) >> (_index)) & ((1 << (_num_bits)) - 1))
|
||||
|
||||
#define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \
|
||||
HTT_GET_BITS(cal_info, 0, 8)
|
||||
|
||||
/*
|
||||
* Used by some hosts to print names of cal type, based on
|
||||
* htt_ctrl_path_cal_type_ids values specified in
|
||||
* htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg.
|
||||
*/
|
||||
#ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS
|
||||
static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id)
|
||||
{
|
||||
switch (cal_type_id)
|
||||
{
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP);
|
||||
HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC);
|
||||
}
|
||||
|
||||
return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN";
|
||||
}
|
||||
#endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */
|
||||
|
||||
|
||||
#endif /* __HTT_STATS_H__ */
|
||||
|
|
|
|||
|
|
@ -639,6 +639,9 @@ typedef enum {
|
|||
WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
|
||||
WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
|
||||
WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
|
||||
WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */
|
||||
WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */
|
||||
WMI_SERVICE_XPAN_SUPPORT = 391, /* Indicate FW support XPAN configuration */
|
||||
|
||||
WMI_MAX_EXT2_SERVICE
|
||||
|
||||
|
|
|
|||
|
|
@ -1396,6 +1396,13 @@ typedef enum {
|
|||
WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr,
|
||||
WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct,
|
||||
WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param,
|
||||
WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param,
|
||||
WMITLV_TAG_STRUC_WMI_RADAR_FLAGS,
|
||||
WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data,
|
||||
WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param,
|
||||
WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param,
|
||||
} WMITLV_TAG_ID;
|
||||
/*
|
||||
* IMPORTANT: Please add _ALL_ WMI Commands Here.
|
||||
|
|
@ -1931,6 +1938,7 @@ typedef enum {
|
|||
OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \
|
||||
OP(WMI_NAN_OEM_DATA_CMDID) \
|
||||
OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \
|
||||
OP(WMI_CSA_EVENT_STATUS_INDICATION_CMDID) \
|
||||
/* add new CMD_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -2247,6 +2255,7 @@ typedef enum {
|
|||
OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \
|
||||
OP(WMI_NAN_OEM_DATA_EVENTID) \
|
||||
OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \
|
||||
OP(WMI_MLO_LINK_STATE_SWITCH_EVENTID) \
|
||||
/* add new EVT_LIST elements above this line */
|
||||
|
||||
|
||||
|
|
@ -5455,7 +5464,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID);
|
|||
|
||||
/* MLO link switch confirmation command to inform FW about host side status and reason code */
|
||||
#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_CONF_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_set_active_cmd_fixed_param, set_link_params, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID);
|
||||
|
||||
/* WMI CMD used to send WSI stats info. */
|
||||
|
|
@ -5463,6 +5476,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID);
|
||||
|
||||
/* CSA status indication command to inform FW about host accepting or rejecting csa event*/
|
||||
#define WMITLV_TABLE_WMI_CSA_EVENT_STATUS_INDICATION_CMDID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param , wmi_csa_event_status_ind_fixed_param,fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_CSA_EVENT_STATUS_INDICATION_CMDID);
|
||||
|
||||
|
||||
|
||||
/************************** TLV definitions of WMI events *******************************/
|
||||
|
|
@ -5519,7 +5537,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \
|
||||
WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
|
||||
|
|
@ -6251,7 +6271,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_OPER_MODE_CHANGE_EVENTID);
|
|||
WMITLV_CREATE_PARAM_STRUC(WMI_DFS_RADAR_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_PDEV_DFS_RADAR_DETECTION_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RADAR_FLAGS, radar_flags, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID);
|
||||
|
||||
#define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID(id,op,buf,len) \
|
||||
|
|
@ -7005,7 +7026,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR)
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cqi_upload_meta_data, cqi_meta_data, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID);
|
||||
|
||||
/* ctl failsafe check event */
|
||||
|
|
@ -7456,6 +7478,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID);
|
|||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID);
|
||||
|
||||
/* MLO Link State Switch Event */
|
||||
#define WMITLV_TABLE_WMI_MLO_LINK_STATE_SWITCH_EVENTID(id,op,buf,len) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, wmi_mlo_link_state_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
|
||||
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_state_switch_trigger_reason, switch_trigger_reason, WMITLV_SIZE_VAR)
|
||||
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_STATE_SWITCH_EVENTID);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -98,6 +98,8 @@ extern "C" {
|
|||
|
||||
#define WMI_MAX_PN_LEN 8
|
||||
|
||||
#define MAX_NUM_CQI_USERS_IN_STANDALONE_SND 3
|
||||
|
||||
/*
|
||||
* These don't necessarily belong here; but as the MS/SM macros require
|
||||
* ar6000_internal.h to be included, it may not be defined as yet.
|
||||
|
|
@ -625,6 +627,10 @@ typedef enum {
|
|||
/** pause vdev's Tx, Rx, or both for a specific duration */
|
||||
WMI_VDEV_PAUSE_CMDID,
|
||||
|
||||
/** WMI Command to set status of CSA event from HOST */
|
||||
WMI_CSA_EVENT_STATUS_INDICATION_CMDID,
|
||||
|
||||
|
||||
/* peer specific commands */
|
||||
|
||||
/** create a peer */
|
||||
|
|
@ -2412,6 +2418,8 @@ typedef enum {
|
|||
WMI_MLO_LINK_SWITCH_REQUEST_EVENTID,
|
||||
/** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */
|
||||
WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID,
|
||||
/** WMI Event to spcify reason for link state switch */
|
||||
WMI_MLO_LINK_STATE_SWITCH_EVENTID,
|
||||
|
||||
/* WMI event specific to Quiet handling */
|
||||
WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL),
|
||||
|
|
@ -4591,7 +4599,15 @@ typedef struct {
|
|||
* Refer to the below definitions of the
|
||||
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_GET
|
||||
* and _SET macros.
|
||||
* Bits 31:14 - Reserved
|
||||
* Bit 14
|
||||
* This bit will be set when host wants to enable/disable
|
||||
* full BW NOL feature.
|
||||
* When set to 1: Enable full BW NOL feature.
|
||||
* When set to 0: Disable the full BW NOL feature.
|
||||
* Refer to the below definitions of the
|
||||
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET
|
||||
* and _SET macros.
|
||||
* Bits 31:15 - Reserved
|
||||
*/
|
||||
A_UINT32 host_service_flags;
|
||||
|
||||
|
|
@ -5034,6 +5050,11 @@ typedef struct {
|
|||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_SET(host_service_flags, val) \
|
||||
WMI_SET_BITS(host_service_flags, 13, 1, val)
|
||||
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET(host_service_flags) \
|
||||
WMI_GET_BITS(host_service_flags, 14, 1)
|
||||
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_SET(host_service_flags, val) \
|
||||
WMI_SET_BITS(host_service_flags, 14, 1, val)
|
||||
|
||||
|
||||
#define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
|
||||
WMI_GET_BITS(carrier_config, 0, 1)
|
||||
|
|
@ -5594,6 +5615,9 @@ typedef struct {
|
|||
/* NOTE: This constant cannot be changed without breaking WMI compatibility */
|
||||
#define WMI_IE_BITMAP_SIZE 8
|
||||
|
||||
#define WMI_SCAN_MLD_PARAM_MLD_ID_GET(mld_param) WMI_GET_BITS(mld_param, 0, 8)
|
||||
#define WMI_SCAN_MLD_PARAM_MLD_ID_SET(mld_param, val) WMI_SET_BITS(mld_param, 0, 8, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */
|
||||
/** Scan ID (lower 16 bits) MSB 4 bits is used to identify scan client based on enum WMI_SCAN_CLIENT_ID */
|
||||
|
|
@ -5685,6 +5709,11 @@ typedef struct {
|
|||
* dwell time in msec for 6 GHz channel of spectral scan channel list
|
||||
*/
|
||||
A_UINT32 dwell_time_spectral_ch;
|
||||
/**
|
||||
* B0-B7: mld id to be inserted in ML probe request
|
||||
* B8-B31: reserved
|
||||
*/
|
||||
A_UINT32 mld_parameter;
|
||||
|
||||
/**
|
||||
* TLV (tag length value) parameters follow the scan_cmd
|
||||
|
|
@ -9280,6 +9309,9 @@ typedef enum {
|
|||
* 3. Units are in milli-seconds
|
||||
*/
|
||||
WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME,
|
||||
|
||||
/** Parameter used for enabling/disabling RFA toggle for SAP mode */
|
||||
WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE,
|
||||
} WMI_PDEV_PARAM;
|
||||
|
||||
#define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
|
||||
|
|
@ -20534,6 +20566,9 @@ typedef struct {
|
|||
A_UINT32 max_num_simultaneous_links;
|
||||
/** NSTR indication bitmap received in assoc req */
|
||||
A_UINT32 nstr_indication_bitmap;
|
||||
|
||||
/** max num of active links recommended by AP or applications */
|
||||
A_UINT32 recommended_max_num_simultaneous_links;
|
||||
} wmi_peer_assoc_mlo_params;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -25547,6 +25582,30 @@ typedef struct {
|
|||
A_INT32 sidx; /* segment index (where was the radar within the channel) */
|
||||
} wmi_pdev_dfs_radar_detection_event_fixed_param;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_RADAR_FLAGS */
|
||||
/*
|
||||
* Bit 0:
|
||||
* 0 - need check sub channel marking
|
||||
* 1 - full bandwidth need put to NOL
|
||||
* Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros
|
||||
* [1:31] reserved
|
||||
*/
|
||||
A_UINT32 flags;
|
||||
} WMI_RADAR_FLAGS;
|
||||
|
||||
#define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS 0
|
||||
#define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS 1
|
||||
|
||||
#define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \
|
||||
WMI_GET_BITS(flag, \
|
||||
WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
|
||||
WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS)
|
||||
#define WMI_RADAR_FLAGS_FULL_BW_NOL_SET(flag, val) \
|
||||
WMI_GET_BITS(flag, \
|
||||
WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
|
||||
WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val)
|
||||
|
||||
typedef enum {
|
||||
OCAC_COMPLETE = 0,
|
||||
OCAC_ABORT,
|
||||
|
|
@ -34484,6 +34543,22 @@ typedef enum wmi_coex_config_type {
|
|||
* config BT RX PER threshold
|
||||
*/
|
||||
WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD = 49,
|
||||
/* WMI_COEX_SET_TRAFFIC_SHAPING_MODE
|
||||
* arg1: 0 (WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED)
|
||||
* Disable coex policies and set fixed arbitration config.
|
||||
* 1 (WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED)
|
||||
* Enable all coex policies.
|
||||
*/
|
||||
WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50,
|
||||
/* WMI_COEX_CONFIG_ENABLE_CONT_INFO
|
||||
* enable contention info log
|
||||
* arg1:
|
||||
* 0: disable both cont/sched log
|
||||
* 1: enable cont log
|
||||
* 2: enable sched log
|
||||
* 3: enable both cont and sched log
|
||||
*/
|
||||
WMI_COEX_CONFIG_ENABLE_CONT_INFO = 51,
|
||||
} WMI_COEX_CONFIG_TYPE;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -34504,6 +34579,11 @@ typedef enum wmi_coex_dbam_mode_type {
|
|||
WMI_COEX_DBAM_FORCED = 2,
|
||||
} WMI_COEX_DBAM_MODE_TYPE;
|
||||
|
||||
typedef enum {
|
||||
WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED = 0,
|
||||
WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED = 1,
|
||||
} WMI_COEX_TRAFFIC_SHAPING_MODE;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header;
|
||||
A_UINT32 vdev_id;
|
||||
|
|
@ -35795,10 +35875,22 @@ typedef struct {
|
|||
**************************************************************************/
|
||||
} WMI_OEM_DMA_RING_CAPABILITIES;
|
||||
|
||||
typedef enum {
|
||||
WMI_SAR_VERSION_0_ORIGINAL = 0x00,
|
||||
WMI_SAR_VERSION_1_FULL_TABLE = 0x01,
|
||||
WMI_SAR_VERSION_2_DBS_SAR = 0x02,
|
||||
WMI_SAR_VERSION_3_SBS_SAR = 0x03,
|
||||
|
||||
WMI_SAR_VERSION_SMART_TX = 0x04,
|
||||
WMI_SAR_VERSION_TAS = 0x05,
|
||||
|
||||
WMI_SAR_VERSION_INVALID = 0x80
|
||||
} wmi_sar_version_t;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SAR_CAPABILITIES*/
|
||||
/* sar version in bdf */
|
||||
A_UINT32 active_version;
|
||||
A_UINT32 active_version; /* contains a wmi_sar_version_t value */
|
||||
|
||||
/**************************************************************************
|
||||
* DON'T ADD ANY FURTHER FIELDS HERE -
|
||||
|
|
@ -36825,6 +36917,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
|
|||
WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID);
|
||||
WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID);
|
||||
WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID);
|
||||
WMI_RETURN_STRING(WMI_CSA_EVENT_STATUS_INDICATION_CMDID);
|
||||
}
|
||||
|
||||
return (A_UINT8 *) "Invalid WMI cmd";
|
||||
|
|
@ -38852,6 +38945,8 @@ typedef struct {
|
|||
* wmi_dma_buf_release_entry entries[num_buf_release_entry];
|
||||
* wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry];
|
||||
* wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry]
|
||||
* wmi_dma_buf_release_cqi_upload_meta_data
|
||||
* cqi_meta_data[num_meta_data_entry]
|
||||
*/
|
||||
} wmi_dma_buf_release_fixed_param;
|
||||
|
||||
|
|
@ -39480,6 +39575,16 @@ typedef struct {
|
|||
#define WMI_GET_BTCONNECT_STATUS(flags) WMI_GET_BITS(flags, 0, 1)
|
||||
#define WMI_SET_BTCONNECT_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val)
|
||||
|
||||
#define WMI_GET_MLO_BAND(flags) WMI_GET_BITS(flags, 1, 3)
|
||||
#define WMI_SET_MLO_BAND(flags, val) WMI_SET_BITS(flags, 1, 3, val)
|
||||
|
||||
typedef enum wmi_mlo_band_info {
|
||||
WMI_MLO_BAND_NO_MLO = 0,
|
||||
WMI_MLO_BAND_2GHZ_MLO,
|
||||
WMI_MLO_BAND_5GHZ_MLO,
|
||||
WMI_MLO_BAND_6GHZ_MLO,
|
||||
} wmi_mlo_band_info_t;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param */
|
||||
/* roam_scan_type:
|
||||
|
|
@ -39503,7 +39608,10 @@ typedef struct {
|
|||
/*
|
||||
* Flags capturing factors involved during roam scan:
|
||||
* Bit 0 : Bluetooth connect status, 0(not connected) or 1(connected).
|
||||
* Bit 1-31 : reserved for future use.
|
||||
* Bit 1-3 : Indicates which link triggered roaming in MLD cases.
|
||||
* The value is one of the wmi_mlo_band_info_t enum constants.
|
||||
* Refer to WMI_[GET,SET]_MLO_BAND macros.
|
||||
* Bit 4-31 : reserved for future use.
|
||||
*/
|
||||
A_UINT32 flags;
|
||||
} wmi_roam_scan_info;
|
||||
|
|
@ -39518,6 +39626,9 @@ typedef struct {
|
|||
*/
|
||||
} wmi_roam_scan_channel_info;
|
||||
|
||||
#define WMI_GET_AP_INFO_MLO_STATUS(flags) WMI_GET_BITS(flags, 0, 1)
|
||||
#define WMI_SET_AP_INFO_MLO_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param */
|
||||
/*
|
||||
|
|
@ -39553,6 +39664,12 @@ typedef struct {
|
|||
A_UINT32 bl_timestamp;
|
||||
/* Original timeout value in milli seconds when AP added to BL */
|
||||
A_UINT32 bl_original_timeout;
|
||||
/* flags:
|
||||
* bit 0: MLD AP FLAG -> 1: MLD AP, 0: non-MLD AP
|
||||
* Refer to WMI_[GET,SET]_AP_INFO_MLO_STATUS macros.
|
||||
* bit 1-31: reserved.
|
||||
*/
|
||||
A_UINT32 flags;
|
||||
} wmi_roam_ap_info;
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -39630,6 +39747,8 @@ typedef struct {
|
|||
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_RESPONSE_TOKEN_SET(detail,val) WMI_SET_BITS(detail, 8, 8, val)
|
||||
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_GET(detail) WMI_GET_BITS(detail, 16, 8)
|
||||
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_SET(detail,val) WMI_SET_BITS(detail, 16, 8, val)
|
||||
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 24, 3)
|
||||
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 24, 3, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param */
|
||||
|
|
@ -39660,13 +39779,20 @@ typedef struct {
|
|||
* [7:0] : neighbor report request token
|
||||
* [15:8] : neighbor report response token
|
||||
* [23:16] : the number of neighbor report elements in response frame
|
||||
* [31:24] : reserved
|
||||
* [26:24] : band on which frame is sent; the value will be one of the
|
||||
* wmi_mlo_band_info enum constants
|
||||
* Refer to WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET,SET
|
||||
* macros.
|
||||
* [31:27] : reserved
|
||||
* Refer to the above WMI_ROAM_NEIGHBOR_REPORT_INFO_*_GET,_SET macros for
|
||||
* reading and writing these bitfields.
|
||||
*/
|
||||
A_UINT32 neighbor_report_detail;
|
||||
} wmi_roam_neighbor_report_info;
|
||||
|
||||
#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 0, 3)
|
||||
#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 0, 3, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_btm_response_info_tlv_param */
|
||||
|
||||
|
|
@ -39700,6 +39826,13 @@ typedef struct {
|
|||
* that the responding STA requests the BSS to delay termination.
|
||||
*/
|
||||
A_UINT32 btm_resp_bss_termination_delay;
|
||||
/* info:
|
||||
* Bit[0:2] - band on which frame is sent, band value will be one of the
|
||||
* wmi_mlo_band_info_t enum constants
|
||||
* Refer to WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET,SET macros.
|
||||
* Bit[3:31] - reserved.
|
||||
*/
|
||||
A_UINT32 info;
|
||||
} wmi_roam_btm_response_info;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -39716,6 +39849,15 @@ typedef struct {
|
|||
#define WMI_GET_ASSOC_ID(frame_info_ext) WMI_GET_BITS(frame_info_ext, 0, 16)
|
||||
#define WMI_SET_ASSOC_ID(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 0, 16, val)
|
||||
|
||||
#define WMI_GET_MLO_BITMAP_BAND_INFO(frame_info_ext) WMI_GET_BITS(frame_info_ext, 16, 5)
|
||||
#define WMI_SET_MLO_BITMAP_BAND_INFO(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 16, 5, val)
|
||||
|
||||
#define WMI_GET_RX_INDICATE(frame_info_ext) WMI_GET_BITS(frame_info_ext, 21, 1)
|
||||
#define WMI_SET_RX_INDICATE(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 21, 1, val)
|
||||
|
||||
#define WMI_GET_TX_FAILED_REASON(frame_info_ext) WMI_GET_BITS(frame_info_ext, 22, 4)
|
||||
#define WMI_SET_TX_FAILED_REASON(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 22, 4, val)
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param */
|
||||
/* timestamp is the absolute time w.r.t host timer which is synchronized between the host and target */
|
||||
|
|
@ -39763,7 +39905,14 @@ typedef struct {
|
|||
* frame_info_ext captures below fields:
|
||||
* Bit 0-15 : (re)assoc id of (re)association response frame,
|
||||
* section 9.4.1.8 AID field.
|
||||
* Bit 16~31 : reserved for future use.
|
||||
* Bit 16-20 : MLO bitmap band info,
|
||||
* bit0: 2GHz, bit1: 5GHz, bit2: 6GHz, bits 3-4: reserved
|
||||
* Refer to WMI_[GET,SET]_MLO_BITMAP_BAND_INFO macros.
|
||||
* Bit 21 : indicate whether this frame is rx :0-not rx; 1-rx
|
||||
* Refer to WMI_[GET,SET]_RX_INDICATE macros.
|
||||
* Bit 22-25 : opaque tx failure reason
|
||||
* Refer to WMI_[GET,SET]_TX_FAILED_REASON macros.
|
||||
* Bit 26-31 : reserved for future use.
|
||||
*/
|
||||
A_UINT32 frame_info_ext;
|
||||
} wmi_roam_frame_info;
|
||||
|
|
@ -40211,6 +40360,22 @@ typedef enum {
|
|||
*/
|
||||
WMI_ROAM_PARAM_ROAM_RSSI_BOOST_FOR_6GHZ_CAND_AP = 8,
|
||||
|
||||
/*
|
||||
* Roam param to indicate unsupported Power Type for 6 GHz Candidate AP
|
||||
* found during Roam Scan. If AP operates on the power type disabled by
|
||||
* the host, then that candidate should not be selected.
|
||||
* This unsupported Power Type will be configured based
|
||||
* on disabled 6GHz Power Types in Regdomain
|
||||
*
|
||||
* If below bits in the obtianed Bitmap is set then any AP
|
||||
* broadcasting these Power Types should not be selected
|
||||
* BIT 0 - Indoor Access Point
|
||||
* BIT 1 - Standard Power (SP) Access Point
|
||||
* BIT 2 - Very Low Power (VLP) Access Point
|
||||
* BIT 3-7 - Reserved
|
||||
*/
|
||||
WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE = 9,
|
||||
|
||||
/*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/
|
||||
} WMI_ROAM_PARAM;
|
||||
|
||||
|
|
@ -40589,6 +40754,104 @@ typedef struct {
|
|||
};
|
||||
} wmi_enhanced_aoa_gain_phase_data_hdr;
|
||||
|
||||
typedef enum _WMI_AGC_GAIN_TABLE_IDX {
|
||||
WMI_AGC_DG_TABLE_IDX = 0,
|
||||
WMI_AGC_LG_TABLE_IDX,
|
||||
WMI_AGC_VLG_TABLE_IDX,
|
||||
WMI_AGC_MAX_GAIN_TABLE_IDX = 8,
|
||||
} WMI_AGC_GAIN_TABLE_IDX;
|
||||
|
||||
#define WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD 4
|
||||
#define WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD 2
|
||||
#define WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM 1
|
||||
#define WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM 2
|
||||
|
||||
/* Number of words required to store max number of gain table elements = ((max number of gain table elements)/(number of gain table elements per word)) */
|
||||
/* 2 bytes (at most)used to store each gain table elements */
|
||||
#define WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD)
|
||||
|
||||
/* 1 byte (at most) used to store each gain table elements obtained from BDF */
|
||||
#define WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD)
|
||||
|
||||
typedef enum {
|
||||
WMI_AOA_2G = 0,
|
||||
WMI_AOA_5G,
|
||||
WMI_AOA_6G,
|
||||
WMI_AOA_MAX_BAND,
|
||||
} WMI_AOA_SUPPORTED_BANDS;
|
||||
|
||||
#define WMI_AOA_MAX_AGC_GAIN_GET(pcap_var, tbl_idx, output) \
|
||||
do { \
|
||||
A_UINT8 word_idx = 0; \
|
||||
A_UINT8 bit_index = 0; \
|
||||
A_UINT8 nth_byte = 0; \
|
||||
word_idx = tbl_idx >> 1; \
|
||||
nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \
|
||||
bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \
|
||||
output = WMI_GET_BITS(*(pcap_var + word_idx), bit_index, 16); \
|
||||
} while (0)
|
||||
|
||||
#define WMI_AOA_MAX_AGC_GAIN_SET(pcap_var, tbl_idx, value) \
|
||||
do { \
|
||||
A_UINT8 word_idx = 0; \
|
||||
A_UINT8 bit_index = 0; \
|
||||
A_UINT8 nth_byte = 0; \
|
||||
word_idx = tbl_idx >> 1; \
|
||||
nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \
|
||||
bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \
|
||||
WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 16, value); \
|
||||
} while (0)
|
||||
|
||||
#define WMI_AOA_MAX_BDF_ENTRIES_GET(pcap_var, tbl_idx, output) \
|
||||
do { \
|
||||
A_UINT8 word_idx = 0; \
|
||||
A_UINT8 bit_index = 0; \
|
||||
A_UINT8 nth_byte = 0; \
|
||||
word_idx = tbl_idx >> 2; \
|
||||
nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \
|
||||
bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \
|
||||
output = WMI_GET_BITS(*(pcap_var+word_idx), bit_index, 8); \
|
||||
} while (0)
|
||||
|
||||
#define WMI_AOA_MAX_BDF_ENTRIES_SET(pcap_var, tbl_idx, value) \
|
||||
do { \
|
||||
A_UINT8 word_idx = 0; \
|
||||
A_UINT8 nth_byte = 0; \
|
||||
A_UINT8 bit_index = 0; \
|
||||
word_idx = tbl_idx >> 2; \
|
||||
nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \
|
||||
bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \
|
||||
WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 8, value); \
|
||||
} while (0)
|
||||
|
||||
typedef struct {
|
||||
/** TLV tag and len; tag equals
|
||||
* WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param */
|
||||
A_UINT32 tlv_header;
|
||||
|
||||
/* Maximum number of Rx AGC gain tables supported */
|
||||
A_UINT32 max_agc_gain_tbls;
|
||||
|
||||
/* 1 byte is used to store bdf max number of elements in each gain tables */
|
||||
A_UINT32 max_bdf_gain_entries[WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS];
|
||||
|
||||
/** This TLV is followed by TLV array - wmi_enhanced_aoa_per_band_caps_param
|
||||
* containing band specifc agc gain table information.
|
||||
*/
|
||||
} wmi_enhanced_aoa_caps_param;
|
||||
|
||||
typedef struct {
|
||||
/** TLV tag and len; tag equals
|
||||
* WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param */
|
||||
A_UINT32 tlv_header;
|
||||
|
||||
/* Band information - WMI_AOA_SUPPORTED_BANDS */
|
||||
A_UINT32 band_info;
|
||||
|
||||
/* 2 bytes are used to store agc max number of elements in each gain tables */
|
||||
A_UINT32 max_agc_gain[WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS];
|
||||
} wmi_enhanced_aoa_per_band_caps_param;
|
||||
|
||||
/* WMI_HALPHY_CAL_LIST:
|
||||
*
|
||||
* Below is the list of HALPHY online CAL currently enabled in
|
||||
|
|
@ -44210,6 +44473,7 @@ typedef enum {
|
|||
WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, /* Set force specific links because of new dis-connection */
|
||||
WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, /* Set force specific links because of AP-side link removal */
|
||||
WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */
|
||||
WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, /* Set force specific links for revert previous failed due to host reject */
|
||||
} WMI_MLO_LINK_FORCE_REASON;
|
||||
|
||||
#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \
|
||||
|
|
@ -44316,6 +44580,11 @@ typedef struct wmi_mlo_set_active_link_number_param
|
|||
|
||||
} wmi_mlo_set_active_link_number_param;
|
||||
|
||||
typedef enum {
|
||||
WMI_MLO_LINK_SET_ACTIVE_STATUS_SUCCESS = 0,
|
||||
WMI_MLO_LINK_SET_ACTIVE_STATUS_HOST_REJECT = 1,
|
||||
} WMI_MLO_LINK_SET_ACTIVE_STATUS;
|
||||
|
||||
typedef struct wmi_mlo_link_set_active_resp_event
|
||||
{
|
||||
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param; */
|
||||
|
|
@ -44382,8 +44651,14 @@ typedef struct {
|
|||
} wmi_mlo_ready_cmd_fixed_param;
|
||||
|
||||
typedef enum wmi_mlo_tear_down_reason_code_type {
|
||||
WMI_MLO_TEARDOWN_SSR_REASON,
|
||||
WMI_MLO_TEARDOWN_HOST_INITIATED_REASON,
|
||||
WMI_MLO_TEARDOWN_REASON_SSR,
|
||||
/* keep old name as alias for new name */
|
||||
WMI_MLO_TEARDOWN_SSR_REASON = WMI_MLO_TEARDOWN_REASON_SSR,
|
||||
WMI_MLO_TEARDOWN_REASON_HOST_INITIATED,
|
||||
/* keep old name as alias for new name */
|
||||
WMI_MLO_TEARDOWN_HOST_INITIATED_REASON =
|
||||
WMI_MLO_TEARDOWN_REASON_HOST_INITIATED,
|
||||
WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN,
|
||||
} WMI_MLO_TEARDOWN_REASON_TYPE;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -44395,6 +44670,8 @@ typedef struct {
|
|||
A_UINT32 reason_code;
|
||||
/* trigger_umac_reset : of type A_BOOL to indicate the umac reset for the partner chip. */
|
||||
A_UINT32 trigger_umac_reset;
|
||||
/* erp_standby_mode : of type A_BOOL to indicate the chip is going to be active in ERP */
|
||||
A_UINT32 erp_standby_mode;
|
||||
} wmi_mlo_teardown_fixed_param;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -45897,6 +46174,9 @@ typedef struct {
|
|||
} wmi_vdev_set_manual_su_trig_cmd_fixed_param;
|
||||
|
||||
|
||||
#define CQI_UPLOAD_META_DATA_NC_IDX(idx) \
|
||||
(MAX_NUM_CQI_USERS_IN_STANDALONE_SND + (idx * 2))
|
||||
|
||||
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \
|
||||
WMI_SET_BITS(asnr_params, 0, 16, value)
|
||||
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \
|
||||
|
|
@ -45927,26 +46207,46 @@ typedef struct {
|
|||
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \
|
||||
WMI_GET_BITS(fb_params, 2, 2)
|
||||
|
||||
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DDR_BUF_IDX(ddr_buffer_idx, value) \
|
||||
WMI_SET_BITS(ddr_buffer_idx, 4, 2, value)
|
||||
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DDR_BUF_IDX(ddr_buffer_idx) \
|
||||
WMI_GET_BITS(ddr_buffer_idx, 4, 2)
|
||||
|
||||
|
||||
#define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \
|
||||
WMI_SET_BITS(snd_params, 0, 1, value)
|
||||
WMI_SET_BITS(snd_params, 0, 2, value)
|
||||
#define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \
|
||||
WMI_GET_BITS(snd_params, 0, 1)
|
||||
WMI_GET_BITS(snd_params, 0, 2)
|
||||
|
||||
#define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \
|
||||
WMI_SET_BITS(snd_params, 1, 2, value)
|
||||
WMI_SET_BITS(snd_params, 2, 2, value)
|
||||
#define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \
|
||||
WMI_GET_BITS(snd_params, 1, 2)
|
||||
WMI_GET_BITS(snd_params, 2, 2)
|
||||
|
||||
#define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \
|
||||
WMI_SET_BITS(snd_params, 3, 1, value)
|
||||
WMI_SET_BITS(snd_params, 4, 1, value)
|
||||
#define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \
|
||||
WMI_GET_BITS(snd_params, 3, 1)
|
||||
WMI_GET_BITS(snd_params, 4, 1)
|
||||
|
||||
#define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \
|
||||
WMI_SET_BITS(snd_params, 4, 3, value)
|
||||
WMI_SET_BITS(snd_params, 5, 3, value)
|
||||
#define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \
|
||||
WMI_GET_BITS(snd_params, 4, 3)
|
||||
WMI_GET_BITS(snd_params, 5, 3)
|
||||
|
||||
#define WMI_SET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params, value) \
|
||||
WMI_SET_BITS(snd_params, 8, 1, value)
|
||||
#define WMI_GET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params) \
|
||||
WMI_GET_BITS(snd_params, 8, 1)
|
||||
|
||||
#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_IS_VALID(fb_params_cqi, value, idx) \
|
||||
WMI_SET_BITS(fb_params_cqi, idx, 1, value)
|
||||
#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_IS_VALID(fb_params_cqi, idx) \
|
||||
WMI_GET_BITS(fb_params_cqi, idx, 1)
|
||||
|
||||
#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_NC(fb_params_cqi, value, idx) \
|
||||
WMI_SET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2, value)
|
||||
#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_NC(fb_params_cqi, idx) \
|
||||
WMI_GET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2)
|
||||
|
||||
|
||||
typedef enum _WMI_STANDALONE_SOUND_STATUS_T {
|
||||
|
|
@ -45980,37 +46280,67 @@ typedef struct {
|
|||
A_UINT32 dsnr_params;
|
||||
/** Peer mac address */
|
||||
wmi_mac_addr peer_mac_address;
|
||||
/**
|
||||
/** fb_params:
|
||||
* [1:0] Nc
|
||||
* Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NC
|
||||
* [3:2] nss_num
|
||||
* Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NSS_NUM
|
||||
* [5:4] ddr_buffer_idx
|
||||
* Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_DDR_BUF_IDX
|
||||
*/
|
||||
A_UINT32 fb_params;
|
||||
} wmi_dma_buf_release_cv_upload_meta_data;
|
||||
|
||||
typedef struct {
|
||||
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data */
|
||||
A_UINT32 tlv_header;
|
||||
|
||||
/**
|
||||
* [15:0] ASNR length
|
||||
* [31:16] ASNR offset
|
||||
*/
|
||||
A_UINT32 asnr_params;
|
||||
|
||||
/** Peer mac address */
|
||||
wmi_mac_addr peer_mac_address[MAX_NUM_CQI_USERS_IN_STANDALONE_SND];
|
||||
|
||||
/**
|
||||
* [0] is_user0_valid
|
||||
* [1] is_user1_valid
|
||||
* [2] is_user2_valid
|
||||
* [4:3] User0_Nc
|
||||
* [6:5] User1_Nc
|
||||
* [8:7] User2_Nc
|
||||
*/
|
||||
A_UINT32 fb_params_cqi : 9,
|
||||
reserved : 23;
|
||||
} wmi_dma_buf_release_cqi_upload_meta_data;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */
|
||||
/** vdev identifier */
|
||||
A_UINT32 vdev_id;
|
||||
/** sounding_params:
|
||||
* [0] Feedback type
|
||||
* [2:1] Ng
|
||||
* [3] Codebook
|
||||
* [6:4] BW
|
||||
* 0 = 20 MHz
|
||||
* 1 = 40 MHz
|
||||
* 2 = 80 MHz
|
||||
* 3 = 160 MHz
|
||||
* 4 = 320 MHz
|
||||
* [31:7] Reserved
|
||||
*/
|
||||
* [1:0] Feedback type
|
||||
* [3:2] Ng
|
||||
* [4] Codebook
|
||||
* [7:5] BW
|
||||
* 0 = 20 MHz
|
||||
* 1 = 40 MHz
|
||||
* 2 = 80 MHz
|
||||
* 3 = 160 MHz
|
||||
* 4 = 320 MHz
|
||||
* [8] Triggered/Non-Triggered CQI
|
||||
* [31:9] Reserved
|
||||
*/
|
||||
A_UINT32 sounding_params;
|
||||
/** The number of sounding repeats */
|
||||
A_UINT32 num_sounding_repeats;
|
||||
/**
|
||||
* TLV (tag length value) parameters follow the
|
||||
* structure. The TLV's are:
|
||||
* wmi_mac_addr peer_list[num_peers];
|
||||
*/
|
||||
* TLV (tag length value) parameters follow the
|
||||
* structure. The TLV's are:
|
||||
* wmi_mac_addr peer_list[num_peers];
|
||||
*/
|
||||
} wmi_standalone_sounding_cmd_fixed_param;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -46186,6 +46516,9 @@ typedef struct {
|
|||
A_UINT32 tlv_header;
|
||||
wmi_mac_addr ap_mld_macaddr;
|
||||
|
||||
/* max num of active links recommended by AP or applications */
|
||||
A_UINT32 recommended_max_num_simultaneous_links;
|
||||
|
||||
/*
|
||||
* The TLVs listed below follow this fixed_param TLV:
|
||||
* wmi_mlo_link_bss_param link_bss_params[]:
|
||||
|
|
@ -46217,6 +46550,7 @@ typedef enum _WMI_LINK_SWITCH_CNF_REASON{
|
|||
WMI_MLO_LINK_SWITCH_CNF_REASON_BSS_PARAMS_CHANGED = 1,
|
||||
WMI_MLO_LINK_SWITCH_CNF_REASON_CONCURRECNY_CONFLICT = 2,
|
||||
WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_INTERNAL_ERROR = 3,
|
||||
WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE = 4,
|
||||
WMI_MLO_LINK_SWITCH_CNF_REASON_MAX,
|
||||
} WMI_LINK_SWITCH_CNF_REASON;
|
||||
|
||||
|
|
@ -46229,10 +46563,71 @@ typedef struct {
|
|||
A_UINT32 tlv_header;
|
||||
|
||||
A_UINT32 vdev_id;
|
||||
A_UINT32 status; /*see definition of WMI_LINK_SWITCH_CNF_STATUS*/
|
||||
A_UINT32 reason; /*see definition of WMI_LINK_SWITCH_CNF_REASON*/
|
||||
A_UINT32 status; /* see definition of WMI_LINK_SWITCH_CNF_STATUS */
|
||||
A_UINT32 reason; /* see definition of WMI_LINK_SWITCH_CNF_REASON */
|
||||
|
||||
/*
|
||||
* The following optional TLVs may follow this fixed_praam TLV,
|
||||
* depending on the value of the reason field.
|
||||
*
|
||||
* wmi_mlo_link_set_active_cmd_fixed_param set_link_params[];
|
||||
* The set_link_params array has one element when reason is
|
||||
* WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE and
|
||||
* use_ieee_link_id_bitmap should always be filled with 1.
|
||||
* In other cases the length of the set_link_params array shall be 0.
|
||||
*
|
||||
* wmi_mlo_set_active_link_number_param link_number_param[];
|
||||
* Link number parameters, optional TLV.
|
||||
* Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or
|
||||
* WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM.
|
||||
* In other cases the length of array shall be 0.
|
||||
*
|
||||
* A_UINT32 ieee_link_id_bitmap[];
|
||||
* present for WMI_MLO_LINK_FORCE_ACTIVE
|
||||
* or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE
|
||||
* or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or
|
||||
* WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM
|
||||
* In other cases the length of array shall be 0.
|
||||
*
|
||||
* A_UINT32 ieee_link_id_bitmap2[];
|
||||
* For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[]
|
||||
* carries the inactive linkid bitmap.
|
||||
* In other cases the length of the array shall be 0.
|
||||
*/
|
||||
} wmi_mlo_link_switch_cnf_fixed_param;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param */
|
||||
A_UINT32 link_state_switch_count; /* Number of link state switch event pending, MAX 5 iteration */
|
||||
} wmi_mlo_link_state_switch_req_evt_fixed_param;
|
||||
|
||||
typedef struct {
|
||||
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param */
|
||||
A_UINT32 cur_active_ieee_bitmap; /* current active ieee linkbitmap */
|
||||
A_UINT32 prev_active_ieee_bitmap; /* previous active iee linkbitmap */
|
||||
A_UINT32 host_ref_fw_timestamp_ms; /* fw time stamp on refrence of TIME_STAMP_SYNC_CMD */
|
||||
A_UINT32 reason_code; /* reason for link state switch trigger -
|
||||
* refer to WMI_LINK_STATE_SWITCH_REASON
|
||||
*/
|
||||
wmi_mac_addr ml_bssid; /* mac address of mld device */
|
||||
} wmi_mlo_link_state_switch_trigger_reason;
|
||||
|
||||
typedef enum _WMI_LINK_STATE_SWITCH_REASON {
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_VDEV_READY = 0,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_ULL_MODE = 1,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_ENABLED = 2,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_DISABLED = 3,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_ENABLED = 4,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_DISABLED = 5,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_QUALITY = 6,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_CAPACITY = 7,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_RSSI = 8,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BMISS = 9,
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BT_STATUS = 10,
|
||||
|
||||
WMI_MLO_PS_LINK_STATE_SWITCH_REASON_MAX,
|
||||
} WMI_LINK_STATE_SWITCH_REASON;
|
||||
|
||||
#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 0, 16)
|
||||
#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 0, 16, value)
|
||||
|
||||
|
|
@ -46414,6 +46809,15 @@ typedef struct {
|
|||
A_UINT32 wsi_egress_load_info;
|
||||
} wmi_pdev_wsi_stats_info_cmd_fixed_param;
|
||||
|
||||
typedef struct {
|
||||
/** TLV tag and len; tag equals
|
||||
* WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param
|
||||
*/
|
||||
A_UINT32 tlv_header;
|
||||
A_UINT32 vdev_id;
|
||||
A_UINT32 status; /* accept: 1 reject : 0 */
|
||||
} wmi_csa_event_status_ind_fixed_param;
|
||||
|
||||
|
||||
|
||||
/* ADD NEW DEFS HERE */
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
#define __WMI_VER_MINOR_ 0
|
||||
/** WMI revision number has to be incremented when there is a
|
||||
* change that may or may not break compatibility. */
|
||||
#define __WMI_REVISION_ 1375
|
||||
#define __WMI_REVISION_ 1392
|
||||
|
||||
/** The Version Namespace should not be normally changed. Only
|
||||
* host and firmware of the same WMI namespace will work
|
||||
|
|
|
|||
49
drivers/staging/fw-api/hw/peach/v1/HALcomdef.h
Normal file
49
drivers/staging/fw-api/hw/peach/v1/HALcomdef.h
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#ifndef HAL_COMDEF_H
|
||||
#define HAL_COMDEF_H
|
||||
|
||||
#ifndef _ARM_ASM_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "com_dtypes.h"
|
||||
|
||||
#ifndef _BOOL32_DEFINED
|
||||
typedef unsigned long int bool32;
|
||||
#define _BOOL32_DEFINED
|
||||
#endif
|
||||
|
||||
#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
|
||||
|
||||
#define inp(port) (*((volatile byte *) (port)))
|
||||
#define inpw(port) (*((volatile word *) (port)))
|
||||
#define inpdw(port) (*((volatile dword *)(port)))
|
||||
|
||||
#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
|
||||
#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
|
||||
#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
301
drivers/staging/fw-api/hw/peach/v1/HALhwio.h
Normal file
301
drivers/staging/fw-api/hw/peach/v1/HALhwio.h
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#ifndef HAL_HWIO_H
|
||||
#define HAL_HWIO_H
|
||||
|
||||
#include "HALcomdef.h"
|
||||
|
||||
#define HWIO_BASE_PTR(base) base##_BASE_PTR
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
|
||||
#else
|
||||
#define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
|
||||
#endif
|
||||
|
||||
#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
|
||||
#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
|
||||
#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
|
||||
#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
|
||||
#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
|
||||
#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
|
||||
#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
|
||||
#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
|
||||
#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
|
||||
#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
|
||||
#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
|
||||
#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
|
||||
#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
|
||||
#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
|
||||
#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
|
||||
#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
|
||||
#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
|
||||
#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
|
||||
#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
|
||||
#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
|
||||
#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
|
||||
#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
|
||||
|
||||
#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
|
||||
#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
|
||||
#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
|
||||
#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
|
||||
|
||||
#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
|
||||
#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
|
||||
#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
|
||||
#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
|
||||
|
||||
#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
|
||||
#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
|
||||
#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
|
||||
#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
|
||||
|
||||
#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
|
||||
#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
|
||||
#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
|
||||
#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
|
||||
|
||||
#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
|
||||
#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
|
||||
#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
|
||||
#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
|
||||
|
||||
#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
|
||||
#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
|
||||
#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
|
||||
#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
|
||||
#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
|
||||
#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
|
||||
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
|
||||
|
||||
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
|
||||
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
|
||||
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
|
||||
|
||||
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
|
||||
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
|
||||
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
|
||||
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
|
||||
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
|
||||
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
|
||||
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
|
||||
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
|
||||
|
||||
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
|
||||
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
|
||||
|
||||
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
|
||||
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
|
||||
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
|
||||
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
|
||||
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
|
||||
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
|
||||
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
|
||||
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
|
||||
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
|
||||
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
|
||||
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
|
||||
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
|
||||
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
|
||||
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
|
||||
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
|
||||
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
|
||||
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
|
||||
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
|
||||
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
|
||||
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
|
||||
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
|
||||
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
|
||||
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
|
||||
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
|
||||
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
|
||||
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
|
||||
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
|
||||
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
|
||||
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
|
||||
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
|
||||
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
|
||||
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
|
||||
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
|
||||
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
|
||||
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
|
||||
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
|
||||
|
||||
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
|
||||
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
|
||||
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
|
||||
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
|
||||
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
|
||||
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
|
||||
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
|
||||
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
|
||||
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
|
||||
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
|
||||
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
|
||||
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
|
||||
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
|
||||
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
|
||||
static unsigned int Readdata, Val_temp, Val;\
|
||||
Readdata = HWIO_INX(base, hwiosym); \
|
||||
Val_temp = Readdata & ~mask1 & ~mask2; \
|
||||
Val = Val_temp | val1 | val2; \
|
||||
HWIO_##hwiosym##_OUT(base, Val); \
|
||||
}
|
||||
|
||||
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
|
||||
static unsigned int Readdata1, Val_temp1, Val1;\
|
||||
Readdata1 = HWIO_INX(base, hwiosym); \
|
||||
Val_temp1 = Readdata1 & ~mask1 & ~mask2 & ~mask3; \
|
||||
Val1 = Val_temp1 | val1 | val2 | val3; \
|
||||
HWIO_##hwiosym##_OUT(base, Val1); \
|
||||
}
|
||||
|
||||
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
|
||||
static unsigned int Readdata2, Val_temp2, Val2;\
|
||||
Readdata2 = HWIO_INX(base, hwiosym); \
|
||||
Val_temp2 = Readdata2 & ~mask1 & ~mask2 & ~mask3 & ~mask4; \
|
||||
Val2 = Val_temp2 | val1 | val2 | val3 | val4; \
|
||||
HWIO_##hwiosym##_OUT(base, Val2); \
|
||||
}
|
||||
|
||||
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
|
||||
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
|
||||
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
|
||||
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
|
||||
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
|
||||
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
|
||||
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
|
||||
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
|
||||
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
|
||||
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
|
||||
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
|
||||
|
||||
#define HWIO_INTLOCK()
|
||||
#define HWIO_INTFREE()
|
||||
|
||||
#define __inp(port) (*((volatile uint8 *) (port)))
|
||||
#define __inpw(port) (*((volatile uint16 *) (port)))
|
||||
#define __inpdw(port) (*((volatile uint32 *) (port)))
|
||||
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
|
||||
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
|
||||
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
|
||||
|
||||
#ifdef HAL_HWIO_EXTERNAL
|
||||
|
||||
#undef __inp
|
||||
#undef __inpw
|
||||
#undef __inpdw
|
||||
#undef __outp
|
||||
#undef __outpw
|
||||
#undef __outpdw
|
||||
|
||||
#define __inp(port) __inp_extern(port)
|
||||
#define __inpw(port) __inpw_extern(port)
|
||||
#define __inpdw(port) __inpdw_extern(port)
|
||||
#define __outp(port, val) __outp_extern(port, val)
|
||||
#define __outpw(port, val) __outpw_extern(port, val)
|
||||
#define __outpdw(port, val) __outpdw_extern(port, val)
|
||||
|
||||
extern uint8 __inp_extern ( uint32 nAddr );
|
||||
extern uint16 __inpw_extern ( uint32 nAddr );
|
||||
extern uint32 __inpdw_extern ( uint32 nAddr );
|
||||
extern void __outp_extern ( uint32 nAddr, uint8 nData );
|
||||
extern void __outpw_extern ( uint32 nAddr, uint16 nData );
|
||||
extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
|
||||
|
||||
#endif
|
||||
|
||||
#define in_byte(addr) (__inp(addr))
|
||||
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
|
||||
#define out_byte(addr, val) __outp(addr,val)
|
||||
#define out_byte_masked(io, mask, val, shadow) \
|
||||
HWIO_INTLOCK(); \
|
||||
out_byte( io, shadow); \
|
||||
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
|
||||
HWIO_INTFREE()
|
||||
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
|
||||
out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
|
||||
((uint16)((val) & (mask)))) )
|
||||
|
||||
#define in_word(addr) (__inpw(addr))
|
||||
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
|
||||
#define out_word(addr, val) __outpw(addr,val)
|
||||
#define out_word_masked(io, mask, val, shadow) \
|
||||
HWIO_INTLOCK( ); \
|
||||
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
|
||||
out_word( io, shadow); \
|
||||
HWIO_INTFREE( )
|
||||
#define out_word_masked_ns(io, mask, val, current_reg_content) \
|
||||
out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
|
||||
((uint16)((val) & (mask)))) )
|
||||
|
||||
#define in_dword(addr) (__inpdw(addr))
|
||||
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
|
||||
#define out_dword(addr, val) __outpdw(addr,val)
|
||||
#define out_dword_masked(io, mask, val, shadow) \
|
||||
HWIO_INTLOCK(); \
|
||||
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
|
||||
out_dword( io, shadow); \
|
||||
HWIO_INTFREE()
|
||||
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
|
||||
out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
|
||||
((uint32)((val) & (mask)))) )
|
||||
|
||||
#endif
|
||||
|
||||
64
drivers/staging/fw-api/hw/peach/v1/ack_report.h
Normal file
64
drivers/staging/fw-api/hw/peach/v1/ack_report.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ACK_REPORT_H_
|
||||
#define _ACK_REPORT_H_
|
||||
|
||||
#define NUM_OF_DWORDS_ACK_REPORT 1
|
||||
|
||||
struct ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t selfgen_response_reason : 4,
|
||||
ax_trigger_type : 4,
|
||||
sr_ppdu : 1,
|
||||
reserved : 7,
|
||||
frame_control : 16;
|
||||
#else
|
||||
uint32_t frame_control : 16,
|
||||
reserved : 7,
|
||||
sr_ppdu : 1,
|
||||
ax_trigger_type : 4,
|
||||
selfgen_response_reason : 4;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
|
||||
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0
|
||||
|
||||
#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
|
||||
#define ACK_REPORT_SR_PPDU_LSB 8
|
||||
#define ACK_REPORT_SR_PPDU_MSB 8
|
||||
#define ACK_REPORT_SR_PPDU_MASK 0x00000100
|
||||
|
||||
#define ACK_REPORT_RESERVED_OFFSET 0x00000000
|
||||
#define ACK_REPORT_RESERVED_LSB 9
|
||||
#define ACK_REPORT_RESERVED_MSB 15
|
||||
#define ACK_REPORT_RESERVED_MASK 0x0000fe00
|
||||
|
||||
#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
23
drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h
Normal file
23
drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef BERYLLIUM_TOP_REG_H
|
||||
#define BERYLLIUM_TOP_REG_H
|
||||
|
||||
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
|
||||
#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
|
||||
|
||||
#endif
|
||||
57
drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h
Normal file
57
drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BUFFER_ADDR_INFO_H_
|
||||
#define _BUFFER_ADDR_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
|
||||
|
||||
struct buffer_addr_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t buffer_addr_31_0 : 32;
|
||||
uint32_t buffer_addr_39_32 : 8,
|
||||
return_buffer_manager : 4,
|
||||
sw_buffer_cookie : 20;
|
||||
#else
|
||||
uint32_t buffer_addr_31_0 : 32;
|
||||
uint32_t sw_buffer_cookie : 20,
|
||||
return_buffer_manager : 4,
|
||||
buffer_addr_39_32 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
#endif
|
||||
134
drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h
Normal file
134
drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CE_SRC_DESC_H_
|
||||
#define _CE_SRC_DESC_H_
|
||||
|
||||
#define NUM_OF_DWORDS_CE_SRC_DESC 4
|
||||
|
||||
struct ce_src_desc {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t src_buffer_low : 32;
|
||||
uint32_t src_buffer_high : 8,
|
||||
toeplitz_en : 1,
|
||||
src_swap : 1,
|
||||
dest_swap : 1,
|
||||
gather : 1,
|
||||
ce_res_0 : 1,
|
||||
barrier_read : 1,
|
||||
ce_res_1 : 2,
|
||||
length : 16;
|
||||
uint32_t fw_metadata : 16,
|
||||
ce_res_2 : 16;
|
||||
uint32_t ce_res_3 : 20,
|
||||
ring_id : 8,
|
||||
looping_count : 4;
|
||||
#else
|
||||
uint32_t src_buffer_low : 32;
|
||||
uint32_t length : 16,
|
||||
ce_res_1 : 2,
|
||||
barrier_read : 1,
|
||||
ce_res_0 : 1,
|
||||
gather : 1,
|
||||
dest_swap : 1,
|
||||
src_swap : 1,
|
||||
toeplitz_en : 1,
|
||||
src_buffer_high : 8;
|
||||
uint32_t ce_res_2 : 16,
|
||||
fw_metadata : 16;
|
||||
uint32_t looping_count : 4,
|
||||
ring_id : 8,
|
||||
ce_res_3 : 20;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff
|
||||
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff
|
||||
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100
|
||||
|
||||
#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_SRC_SWAP_LSB 9
|
||||
#define CE_SRC_DESC_SRC_SWAP_MSB 9
|
||||
#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200
|
||||
|
||||
#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_DEST_SWAP_LSB 10
|
||||
#define CE_SRC_DESC_DEST_SWAP_MSB 10
|
||||
#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400
|
||||
|
||||
#define CE_SRC_DESC_GATHER_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_GATHER_LSB 11
|
||||
#define CE_SRC_DESC_GATHER_MSB 11
|
||||
#define CE_SRC_DESC_GATHER_MASK 0x00000800
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_CE_RES_0_LSB 12
|
||||
#define CE_SRC_DESC_CE_RES_0_MSB 12
|
||||
#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000
|
||||
|
||||
#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_BARRIER_READ_LSB 13
|
||||
#define CE_SRC_DESC_BARRIER_READ_MSB 13
|
||||
#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_CE_RES_1_LSB 14
|
||||
#define CE_SRC_DESC_CE_RES_1_MSB 15
|
||||
#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000
|
||||
|
||||
#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_LENGTH_LSB 16
|
||||
#define CE_SRC_DESC_LENGTH_MSB 31
|
||||
#define CE_SRC_DESC_LENGTH_MASK 0xffff0000
|
||||
|
||||
#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008
|
||||
#define CE_SRC_DESC_FW_METADATA_LSB 0
|
||||
#define CE_SRC_DESC_FW_METADATA_MSB 15
|
||||
#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008
|
||||
#define CE_SRC_DESC_CE_RES_2_LSB 16
|
||||
#define CE_SRC_DESC_CE_RES_2_MSB 31
|
||||
#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c
|
||||
#define CE_SRC_DESC_CE_RES_3_LSB 0
|
||||
#define CE_SRC_DESC_CE_RES_3_MSB 19
|
||||
#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff
|
||||
|
||||
#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c
|
||||
#define CE_SRC_DESC_RING_ID_LSB 20
|
||||
#define CE_SRC_DESC_RING_ID_MSB 27
|
||||
#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000
|
||||
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_LSB 28
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_MSB 31
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
#endif
|
||||
127
drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h
Normal file
127
drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CE_STAT_DESC_H_
|
||||
#define _CE_STAT_DESC_H_
|
||||
|
||||
#define NUM_OF_DWORDS_CE_STAT_DESC 4
|
||||
|
||||
struct ce_stat_desc {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ce_res_5 : 8,
|
||||
toeplitz_en : 1,
|
||||
src_swap : 1,
|
||||
dest_swap : 1,
|
||||
gather : 1,
|
||||
barrier_read : 1,
|
||||
ce_res_6 : 3,
|
||||
length : 16;
|
||||
uint32_t toeplitz_hash_0 : 32;
|
||||
uint32_t toeplitz_hash_1 : 32;
|
||||
uint32_t fw_metadata : 16,
|
||||
ce_res_7 : 4,
|
||||
ring_id : 8,
|
||||
looping_count : 4;
|
||||
#else
|
||||
uint32_t length : 16,
|
||||
ce_res_6 : 3,
|
||||
barrier_read : 1,
|
||||
gather : 1,
|
||||
dest_swap : 1,
|
||||
src_swap : 1,
|
||||
toeplitz_en : 1,
|
||||
ce_res_5 : 8;
|
||||
uint32_t toeplitz_hash_0 : 32;
|
||||
uint32_t toeplitz_hash_1 : 32;
|
||||
uint32_t looping_count : 4,
|
||||
ring_id : 8,
|
||||
ce_res_7 : 4,
|
||||
fw_metadata : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_CE_RES_5_LSB 0
|
||||
#define CE_STAT_DESC_CE_RES_5_MSB 7
|
||||
#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff
|
||||
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100
|
||||
|
||||
#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_SRC_SWAP_LSB 9
|
||||
#define CE_STAT_DESC_SRC_SWAP_MSB 9
|
||||
#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200
|
||||
|
||||
#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_DEST_SWAP_LSB 10
|
||||
#define CE_STAT_DESC_DEST_SWAP_MSB 10
|
||||
#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400
|
||||
|
||||
#define CE_STAT_DESC_GATHER_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_GATHER_LSB 11
|
||||
#define CE_STAT_DESC_GATHER_MSB 11
|
||||
#define CE_STAT_DESC_GATHER_MASK 0x00000800
|
||||
|
||||
#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_BARRIER_READ_LSB 12
|
||||
#define CE_STAT_DESC_BARRIER_READ_MSB 12
|
||||
#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000
|
||||
|
||||
#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_CE_RES_6_LSB 13
|
||||
#define CE_STAT_DESC_CE_RES_6_MSB 15
|
||||
#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000
|
||||
|
||||
#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_LENGTH_LSB 16
|
||||
#define CE_STAT_DESC_LENGTH_MSB 31
|
||||
#define CE_STAT_DESC_LENGTH_MASK 0xffff0000
|
||||
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff
|
||||
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff
|
||||
|
||||
#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_FW_METADATA_LSB 0
|
||||
#define CE_STAT_DESC_FW_METADATA_MSB 15
|
||||
#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff
|
||||
|
||||
#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_CE_RES_7_LSB 16
|
||||
#define CE_STAT_DESC_CE_RES_7_MSB 19
|
||||
#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000
|
||||
|
||||
#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_RING_ID_LSB 20
|
||||
#define CE_STAT_DESC_RING_ID_MSB 27
|
||||
#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000
|
||||
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_LSB 28
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_MSB 31
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
#endif
|
||||
141
drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h
Normal file
141
drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COEX_RX_STATUS_H_
|
||||
#define _COEX_RX_STATUS_H_
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_RX_STATUS 2
|
||||
|
||||
struct coex_rx_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rx_mac_frame_status : 2,
|
||||
rx_with_tx_response : 1,
|
||||
rx_rate : 5,
|
||||
rx_bw : 3,
|
||||
single_mpdu : 1,
|
||||
filter_status : 1,
|
||||
ampdu : 1,
|
||||
directed : 1,
|
||||
reserved_0 : 1,
|
||||
rx_nss : 3,
|
||||
rx_rssi : 8,
|
||||
rx_type : 3,
|
||||
retry_bit_setting : 1,
|
||||
more_data_bit_setting : 1;
|
||||
uint32_t remain_rx_packet_time : 16,
|
||||
rx_remaining_fes_time : 16;
|
||||
#else
|
||||
uint32_t more_data_bit_setting : 1,
|
||||
retry_bit_setting : 1,
|
||||
rx_type : 3,
|
||||
rx_rssi : 8,
|
||||
rx_nss : 3,
|
||||
reserved_0 : 1,
|
||||
directed : 1,
|
||||
ampdu : 1,
|
||||
filter_status : 1,
|
||||
single_mpdu : 1,
|
||||
rx_bw : 3,
|
||||
rx_rate : 5,
|
||||
rx_with_tx_response : 1,
|
||||
rx_mac_frame_status : 2;
|
||||
uint32_t rx_remaining_fes_time : 16,
|
||||
remain_rx_packet_time : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003
|
||||
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004
|
||||
|
||||
#define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_RATE_LSB 3
|
||||
#define COEX_RX_STATUS_RX_RATE_MSB 7
|
||||
#define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8
|
||||
|
||||
#define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_BW_LSB 8
|
||||
#define COEX_RX_STATUS_RX_BW_MSB 10
|
||||
#define COEX_RX_STATUS_RX_BW_MASK 0x00000700
|
||||
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800
|
||||
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000
|
||||
|
||||
#define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_AMPDU_LSB 13
|
||||
#define COEX_RX_STATUS_AMPDU_MSB 13
|
||||
#define COEX_RX_STATUS_AMPDU_MASK 0x00002000
|
||||
|
||||
#define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_DIRECTED_LSB 14
|
||||
#define COEX_RX_STATUS_DIRECTED_MSB 14
|
||||
#define COEX_RX_STATUS_DIRECTED_MASK 0x00004000
|
||||
|
||||
#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RESERVED_0_LSB 15
|
||||
#define COEX_RX_STATUS_RESERVED_0_MSB 15
|
||||
#define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000
|
||||
|
||||
#define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_NSS_LSB 16
|
||||
#define COEX_RX_STATUS_RX_NSS_MSB 18
|
||||
#define COEX_RX_STATUS_RX_NSS_MASK 0x00070000
|
||||
|
||||
#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_RSSI_LSB 19
|
||||
#define COEX_RX_STATUS_RX_RSSI_MSB 26
|
||||
#define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000
|
||||
|
||||
#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RX_TYPE_LSB 27
|
||||
#define COEX_RX_STATUS_RX_TYPE_MSB 29
|
||||
#define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000
|
||||
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000
|
||||
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000
|
||||
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff
|
||||
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
190
drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h
Normal file
190
drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COEX_TX_REQ_H_
|
||||
#define _COEX_TX_REQ_H_
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_TX_REQ 4
|
||||
|
||||
struct coex_tx_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_pwr : 8,
|
||||
min_tx_pwr : 8,
|
||||
nss : 3,
|
||||
tx_chain_mask : 8,
|
||||
bw : 3,
|
||||
reserved_0 : 2;
|
||||
uint32_t alt_tx_pwr : 8,
|
||||
alt_min_tx_pwr : 8,
|
||||
alt_nss : 3,
|
||||
alt_tx_chain_mask : 8,
|
||||
alt_bw : 3,
|
||||
reserved_1 : 2;
|
||||
uint32_t tx_pwr_1 : 8,
|
||||
alt_tx_pwr_1 : 8,
|
||||
wlan_request_duration : 16;
|
||||
uint32_t wlan_pkt_type : 4,
|
||||
coex_tx_reason : 2,
|
||||
response_frame_type : 5,
|
||||
wlan_low_priority_slicing_allowed : 1,
|
||||
wlan_high_priority_slicing_allowed : 1,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
coex_tx_priority : 4,
|
||||
reserved_3a : 14;
|
||||
#else
|
||||
uint32_t reserved_0 : 2,
|
||||
bw : 3,
|
||||
tx_chain_mask : 8,
|
||||
nss : 3,
|
||||
min_tx_pwr : 8,
|
||||
tx_pwr : 8;
|
||||
uint32_t reserved_1 : 2,
|
||||
alt_bw : 3,
|
||||
alt_tx_chain_mask : 8,
|
||||
alt_nss : 3,
|
||||
alt_min_tx_pwr : 8,
|
||||
alt_tx_pwr : 8;
|
||||
uint32_t wlan_request_duration : 16,
|
||||
alt_tx_pwr_1 : 8,
|
||||
tx_pwr_1 : 8;
|
||||
uint32_t reserved_3a : 14,
|
||||
coex_tx_priority : 4,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
wlan_high_priority_slicing_allowed : 1,
|
||||
wlan_low_priority_slicing_allowed : 1,
|
||||
response_frame_type : 5,
|
||||
coex_tx_reason : 2,
|
||||
wlan_pkt_type : 4;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define COEX_TX_REQ_TX_PWR_OFFSET 0x00000000
|
||||
#define COEX_TX_REQ_TX_PWR_LSB 0
|
||||
#define COEX_TX_REQ_TX_PWR_MSB 7
|
||||
#define COEX_TX_REQ_TX_PWR_MASK 0x000000ff
|
||||
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x00000000
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_LSB 8
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_MSB 15
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define COEX_TX_REQ_NSS_OFFSET 0x00000000
|
||||
#define COEX_TX_REQ_NSS_LSB 16
|
||||
#define COEX_TX_REQ_NSS_MSB 18
|
||||
#define COEX_TX_REQ_NSS_MASK 0x00070000
|
||||
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x00000000
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x07f80000
|
||||
|
||||
#define COEX_TX_REQ_BW_OFFSET 0x00000000
|
||||
#define COEX_TX_REQ_BW_LSB 27
|
||||
#define COEX_TX_REQ_BW_MSB 29
|
||||
#define COEX_TX_REQ_BW_MASK 0x38000000
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_0_OFFSET 0x00000000
|
||||
#define COEX_TX_REQ_RESERVED_0_LSB 30
|
||||
#define COEX_TX_REQ_RESERVED_0_MSB 31
|
||||
#define COEX_TX_REQ_RESERVED_0_MASK 0xc0000000
|
||||
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x00000004
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_LSB 0
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_MSB 7
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff
|
||||
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x00000004
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 8
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 15
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define COEX_TX_REQ_ALT_NSS_OFFSET 0x00000004
|
||||
#define COEX_TX_REQ_ALT_NSS_LSB 16
|
||||
#define COEX_TX_REQ_ALT_NSS_MSB 18
|
||||
#define COEX_TX_REQ_ALT_NSS_MASK 0x00070000
|
||||
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 19
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 26
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f80000
|
||||
|
||||
#define COEX_TX_REQ_ALT_BW_OFFSET 0x00000004
|
||||
#define COEX_TX_REQ_ALT_BW_LSB 27
|
||||
#define COEX_TX_REQ_ALT_BW_MSB 29
|
||||
#define COEX_TX_REQ_ALT_BW_MASK 0x38000000
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_1_OFFSET 0x00000004
|
||||
#define COEX_TX_REQ_RESERVED_1_LSB 30
|
||||
#define COEX_TX_REQ_RESERVED_1_MSB 31
|
||||
#define COEX_TX_REQ_RESERVED_1_MASK 0xc0000000
|
||||
|
||||
#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x00000008
|
||||
#define COEX_TX_REQ_TX_PWR_1_LSB 0
|
||||
#define COEX_TX_REQ_TX_PWR_1_MSB 7
|
||||
#define COEX_TX_REQ_TX_PWR_1_MASK 0x000000ff
|
||||
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x00000008
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x0000ff00
|
||||
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x00000008
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0xffff0000
|
||||
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 0
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 3
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f
|
||||
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_LSB 4
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_MSB 5
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x00000030
|
||||
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 6
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 10
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c0
|
||||
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 11
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 11
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x00000800
|
||||
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 12
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 12
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x00001000
|
||||
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 13
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 13
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x00002000
|
||||
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 14
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 17
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c000
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define COEX_TX_REQ_RESERVED_3A_LSB 18
|
||||
#define COEX_TX_REQ_RESERVED_3A_MSB 31
|
||||
#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc0000
|
||||
|
||||
#endif
|
||||
120
drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h
Normal file
120
drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COEX_TX_STATUS_H_
|
||||
#define _COEX_TX_STATUS_H_
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_TX_STATUS 3
|
||||
|
||||
struct coex_tx_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 7,
|
||||
tx_bw : 3,
|
||||
tx_status_reason : 3,
|
||||
tx_wait_ack : 1,
|
||||
fes_tx_is_gen_frame : 1,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
current_tx_duration : 16;
|
||||
uint32_t next_rx_active_time : 16,
|
||||
remaining_fes_time : 16;
|
||||
uint32_t tx_antenna_mask : 8,
|
||||
shared_ant_tx_pwr : 8,
|
||||
other_ant_tx_pwr : 8,
|
||||
reserved_2 : 8;
|
||||
#else
|
||||
uint32_t current_tx_duration : 16,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
fes_tx_is_gen_frame : 1,
|
||||
tx_wait_ack : 1,
|
||||
tx_status_reason : 3,
|
||||
tx_bw : 3,
|
||||
reserved_0a : 7;
|
||||
uint32_t remaining_fes_time : 16,
|
||||
next_rx_active_time : 16;
|
||||
uint32_t reserved_2 : 8,
|
||||
other_ant_tx_pwr : 8,
|
||||
shared_ant_tx_pwr : 8,
|
||||
tx_antenna_mask : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_RESERVED_0A_LSB 0
|
||||
#define COEX_TX_STATUS_RESERVED_0A_MSB 6
|
||||
#define COEX_TX_STATUS_RESERVED_0A_MASK 0x0000007f
|
||||
|
||||
#define COEX_TX_STATUS_TX_BW_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_TX_BW_LSB 7
|
||||
#define COEX_TX_STATUS_TX_BW_MSB 9
|
||||
#define COEX_TX_STATUS_TX_BW_MASK 0x00000380
|
||||
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x00001c00
|
||||
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x00002000
|
||||
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x00004000
|
||||
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x00008000
|
||||
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x00000000
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0xffff0000
|
||||
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x00000004
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 0
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 15
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff
|
||||
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x00000004
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 16
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 31
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff0000
|
||||
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x00000008
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x000000ff
|
||||
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x00000008
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x00000008
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x00ff0000
|
||||
|
||||
#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x00000008
|
||||
#define COEX_TX_STATUS_RESERVED_2_LSB 24
|
||||
#define COEX_TX_STATUS_RESERVED_2_MSB 31
|
||||
#define COEX_TX_STATUS_RESERVED_2_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
178
drivers/staging/fw-api/hw/peach/v1/com_dtypes.h
Normal file
178
drivers/staging/fw-api/hw/peach/v1/com_dtypes.h
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#ifndef COM_DTYPES_H
|
||||
#define COM_DTYPES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef T_WINNT
|
||||
#ifndef WIN32
|
||||
#define WIN32
|
||||
#endif
|
||||
#include <stdlib.h>
|
||||
#endif
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
#define ON 1
|
||||
#define OFF 0
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#ifndef _ARM_ASM_
|
||||
#ifndef _BOOLEAN_DEFINED
|
||||
|
||||
typedef unsigned char boolean;
|
||||
#define _BOOLEAN_DEFINED
|
||||
#endif
|
||||
|
||||
#if defined(DALSTDDEF_H)
|
||||
#define _BOOLEAN_DEFINED
|
||||
#define _UINT32_DEFINED
|
||||
#define _UINT16_DEFINED
|
||||
#define _UINT8_DEFINED
|
||||
#define _INT32_DEFINED
|
||||
#define _INT16_DEFINED
|
||||
#define _INT8_DEFINED
|
||||
#define _UINT64_DEFINED
|
||||
#define _INT64_DEFINED
|
||||
#define _BYTE_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT32_DEFINED
|
||||
|
||||
typedef unsigned int uint32;
|
||||
#define _UINT32_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT16_DEFINED
|
||||
|
||||
typedef unsigned short uint16;
|
||||
#define _UINT16_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT8_DEFINED
|
||||
|
||||
typedef unsigned char uint8;
|
||||
#define _UINT8_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _INT32_DEFINED
|
||||
|
||||
typedef signed int int32;
|
||||
#define _INT32_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _INT16_DEFINED
|
||||
|
||||
typedef signed short int16;
|
||||
#define _INT16_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _INT8_DEFINED
|
||||
|
||||
typedef signed char int8;
|
||||
#define _INT8_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _BYTE_DEFINED
|
||||
|
||||
typedef unsigned char byte;
|
||||
#define _BYTE_DEFINED
|
||||
#endif
|
||||
|
||||
typedef unsigned short word;
|
||||
|
||||
typedef unsigned long dword;
|
||||
|
||||
typedef unsigned char uint1;
|
||||
|
||||
typedef unsigned short uint2;
|
||||
|
||||
typedef unsigned long uint4;
|
||||
|
||||
typedef signed char int1;
|
||||
|
||||
typedef signed short int2;
|
||||
|
||||
typedef long int int4;
|
||||
|
||||
typedef signed long sint31;
|
||||
|
||||
typedef signed short sint15;
|
||||
|
||||
typedef signed char sint7;
|
||||
|
||||
typedef uint16 UWord16 ;
|
||||
typedef uint32 UWord32 ;
|
||||
typedef int32 Word32 ;
|
||||
typedef int16 Word16 ;
|
||||
typedef uint8 UWord8 ;
|
||||
typedef int8 Word8 ;
|
||||
typedef int32 Vect32 ;
|
||||
|
||||
#if (! defined T_WINNT) && (! defined __GNUC__)
|
||||
|
||||
#ifndef _INT64_DEFINED
|
||||
|
||||
typedef long long int64;
|
||||
#define _INT64_DEFINED
|
||||
#endif
|
||||
#ifndef _UINT64_DEFINED
|
||||
|
||||
typedef unsigned long long uint64;
|
||||
#define _UINT64_DEFINED
|
||||
#endif
|
||||
#else
|
||||
|
||||
#if (defined __GNUC__)
|
||||
#ifndef _INT64_DEFINED
|
||||
typedef long long int64;
|
||||
#define _INT64_DEFINED
|
||||
#endif
|
||||
#ifndef _UINT64_DEFINED
|
||||
typedef unsigned long long uint64;
|
||||
#define _UINT64_DEFINED
|
||||
#endif
|
||||
#else
|
||||
typedef __int64 int64;
|
||||
#ifndef _UINT64_DEFINED
|
||||
typedef unsigned __int64 uint64;
|
||||
#define _UINT64_DEFINED
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
106
drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h
Normal file
106
drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#define _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
|
||||
|
||||
struct eht_sig_usr_mu_mimo_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_mcs : 4,
|
||||
sta_coding : 1,
|
||||
sta_spatial_config : 6,
|
||||
reserved_0a : 1,
|
||||
rx_integrity_check_passed : 1,
|
||||
subband80_cc_mask : 8;
|
||||
uint32_t user_order_subband80_0 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_3 : 8;
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8,
|
||||
rx_integrity_check_passed : 1,
|
||||
reserved_0a : 1,
|
||||
sta_spatial_config : 6,
|
||||
sta_coding : 1,
|
||||
sta_mcs : 4,
|
||||
sta_id : 11;
|
||||
uint32_t user_order_subband80_3 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_0 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
120
drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h
Normal file
120
drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#define _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
|
||||
|
||||
struct eht_sig_usr_ofdma_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_mcs : 4,
|
||||
validate_0a : 1,
|
||||
nss : 4,
|
||||
txbf : 1,
|
||||
sta_coding : 1,
|
||||
reserved_0b : 1,
|
||||
rx_integrity_check_passed : 1,
|
||||
subband80_cc_mask : 8;
|
||||
uint32_t user_order_subband80_0 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_3 : 8;
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8,
|
||||
rx_integrity_check_passed : 1,
|
||||
reserved_0b : 1,
|
||||
sta_coding : 1,
|
||||
txbf : 1,
|
||||
nss : 4,
|
||||
validate_0a : 1,
|
||||
sta_mcs : 4,
|
||||
sta_id : 11;
|
||||
uint32_t user_order_subband80_3 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_0 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
85
drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h
Normal file
85
drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_SU_INFO_H_
|
||||
#define _EHT_SIG_USR_SU_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
|
||||
|
||||
struct eht_sig_usr_su_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_mcs : 4,
|
||||
validate_0a : 1,
|
||||
nss : 4,
|
||||
txbf : 1,
|
||||
sta_coding : 1,
|
||||
reserved_0b : 9,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_0b : 9,
|
||||
sta_coding : 1,
|
||||
txbf : 1,
|
||||
nss : 4,
|
||||
validate_0a : 1,
|
||||
sta_mcs : 4,
|
||||
sta_id : 11;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
204
drivers/staging/fw-api/hw/peach/v1/expected_response.h
Normal file
204
drivers/staging/fw-api/hw/peach/v1/expected_response.h
Normal file
|
|
@ -0,0 +1,204 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _EXPECTED_RESPONSE_H_
|
||||
#define _EXPECTED_RESPONSE_H_
|
||||
|
||||
#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5
|
||||
|
||||
struct expected_response {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_ad2_31_0 : 32;
|
||||
uint32_t tx_ad2_47_32 : 16,
|
||||
expected_response_type : 5,
|
||||
response_to_response : 3,
|
||||
su_ba_user_number : 1,
|
||||
response_info_part2_required : 1,
|
||||
transmitted_bssid_check_en : 1,
|
||||
reserved_1 : 5;
|
||||
uint32_t ndp_sta_partial_aid_2_8_0 : 11,
|
||||
reserved_2 : 10,
|
||||
ndp_sta_partial_aid1_8_0 : 11;
|
||||
uint32_t ast_index : 16,
|
||||
capture_ack_ba_sounding : 1,
|
||||
capture_sounding_1str_20mhz : 1,
|
||||
capture_sounding_1str_40mhz : 1,
|
||||
capture_sounding_1str_80mhz : 1,
|
||||
capture_sounding_1str_160mhz : 1,
|
||||
capture_sounding_1str_240mhz : 1,
|
||||
capture_sounding_1str_320mhz : 1,
|
||||
reserved_3a : 9;
|
||||
uint32_t fcs : 9,
|
||||
reserved_4a : 1,
|
||||
crc : 4,
|
||||
scrambler_seed : 7,
|
||||
reserved_4b : 11;
|
||||
#else
|
||||
uint32_t tx_ad2_31_0 : 32;
|
||||
uint32_t reserved_1 : 5,
|
||||
transmitted_bssid_check_en : 1,
|
||||
response_info_part2_required : 1,
|
||||
su_ba_user_number : 1,
|
||||
response_to_response : 3,
|
||||
expected_response_type : 5,
|
||||
tx_ad2_47_32 : 16;
|
||||
uint32_t ndp_sta_partial_aid1_8_0 : 11,
|
||||
reserved_2 : 10,
|
||||
ndp_sta_partial_aid_2_8_0 : 11;
|
||||
uint32_t reserved_3a : 9,
|
||||
capture_sounding_1str_320mhz : 1,
|
||||
capture_sounding_1str_240mhz : 1,
|
||||
capture_sounding_1str_160mhz : 1,
|
||||
capture_sounding_1str_80mhz : 1,
|
||||
capture_sounding_1str_40mhz : 1,
|
||||
capture_sounding_1str_20mhz : 1,
|
||||
capture_ack_ba_sounding : 1,
|
||||
ast_index : 16;
|
||||
uint32_t reserved_4b : 11,
|
||||
scrambler_seed : 7,
|
||||
crc : 4,
|
||||
reserved_4a : 1,
|
||||
fcs : 9;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff
|
||||
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff
|
||||
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000
|
||||
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000
|
||||
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_LSB 27
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_MSB 31
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000
|
||||
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_LSB 11
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_MSB 20
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800
|
||||
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000
|
||||
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_LSB 0
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_MSB 15
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_LSB 23
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_MSB 31
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000
|
||||
|
||||
#define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010
|
||||
#define EXPECTED_RESPONSE_FCS_LSB 0
|
||||
#define EXPECTED_RESPONSE_FCS_MSB 8
|
||||
#define EXPECTED_RESPONSE_FCS_MASK 0x000001ff
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200
|
||||
|
||||
#define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010
|
||||
#define EXPECTED_RESPONSE_CRC_LSB 10
|
||||
#define EXPECTED_RESPONSE_CRC_MSB 13
|
||||
#define EXPECTED_RESPONSE_CRC_MASK 0x00003c00
|
||||
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000
|
||||
|
||||
#endif
|
||||
183
drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h
Normal file
183
drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HE_SIG_A_MU_DL_INFO_H_
|
||||
#define _HE_SIG_A_MU_DL_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
|
||||
|
||||
struct he_sig_a_mu_dl_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t dl_ul_flag : 1,
|
||||
mcs_of_sig_b : 3,
|
||||
dcm_of_sig_b : 1,
|
||||
bss_color_id : 6,
|
||||
spatial_reuse : 4,
|
||||
transmit_bw : 3,
|
||||
num_sig_b_symbols : 4,
|
||||
comp_mode_sig_b : 1,
|
||||
cp_ltf_size : 2,
|
||||
doppler_indication : 1,
|
||||
reserved_0a : 6;
|
||||
uint32_t txop_duration : 7,
|
||||
reserved_1a : 1,
|
||||
num_ltf_symbols : 3,
|
||||
ldpc_extra_symbol : 1,
|
||||
stbc : 1,
|
||||
packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
crc : 4,
|
||||
tail : 6,
|
||||
reserved_1b : 5,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t reserved_0a : 6,
|
||||
doppler_indication : 1,
|
||||
cp_ltf_size : 2,
|
||||
comp_mode_sig_b : 1,
|
||||
num_sig_b_symbols : 4,
|
||||
transmit_bw : 3,
|
||||
spatial_reuse : 4,
|
||||
bss_color_id : 6,
|
||||
dcm_of_sig_b : 1,
|
||||
mcs_of_sig_b : 3,
|
||||
dl_ul_flag : 1;
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_1b : 5,
|
||||
tail : 6,
|
||||
crc : 4,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2,
|
||||
stbc : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
num_ltf_symbols : 3,
|
||||
reserved_1a : 1,
|
||||
txop_duration : 7;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
113
drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h
Normal file
113
drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HE_SIG_A_MU_UL_INFO_H_
|
||||
#define _HE_SIG_A_MU_UL_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
|
||||
|
||||
struct he_sig_a_mu_ul_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t format_indication : 1,
|
||||
bss_color_id : 6,
|
||||
spatial_reuse : 16,
|
||||
reserved_0a : 1,
|
||||
transmit_bw : 2,
|
||||
reserved_0b : 6;
|
||||
uint32_t txop_duration : 7,
|
||||
reserved_1a : 9,
|
||||
crc : 4,
|
||||
tail : 6,
|
||||
reserved_1b : 5,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t reserved_0b : 6,
|
||||
transmit_bw : 2,
|
||||
reserved_0a : 1,
|
||||
spatial_reuse : 16,
|
||||
bss_color_id : 6,
|
||||
format_indication : 1;
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_1b : 5,
|
||||
tail : 6,
|
||||
crc : 4,
|
||||
reserved_1a : 9,
|
||||
txop_duration : 7;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
218
drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h
Normal file
218
drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HE_SIG_A_SU_INFO_H_
|
||||
#define _HE_SIG_A_SU_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
|
||||
|
||||
struct he_sig_a_su_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t format_indication : 1,
|
||||
beam_change : 1,
|
||||
dl_ul_flag : 1,
|
||||
transmit_mcs : 4,
|
||||
dcm : 1,
|
||||
bss_color_id : 6,
|
||||
reserved_0a : 1,
|
||||
spatial_reuse : 4,
|
||||
transmit_bw : 2,
|
||||
cp_ltf_size : 2,
|
||||
nsts : 3,
|
||||
reserved_0b : 6;
|
||||
uint32_t txop_duration : 7,
|
||||
coding : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
stbc : 1,
|
||||
txbf : 1,
|
||||
packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
reserved_1a : 1,
|
||||
doppler_indication : 1,
|
||||
crc : 4,
|
||||
tail : 6,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_ext_ru_size : 3,
|
||||
rx_ndp : 1,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t reserved_0b : 6,
|
||||
nsts : 3,
|
||||
cp_ltf_size : 2,
|
||||
transmit_bw : 2,
|
||||
spatial_reuse : 4,
|
||||
reserved_0a : 1,
|
||||
bss_color_id : 6,
|
||||
dcm : 1,
|
||||
transmit_mcs : 4,
|
||||
dl_ul_flag : 1,
|
||||
beam_change : 1,
|
||||
format_indication : 1;
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
rx_ndp : 1,
|
||||
dot11ax_ext_ru_size : 3,
|
||||
dot11ax_su_extended : 1,
|
||||
tail : 6,
|
||||
crc : 4,
|
||||
doppler_indication : 1,
|
||||
reserved_1a : 1,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2,
|
||||
txbf : 1,
|
||||
stbc : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
coding : 1,
|
||||
txop_duration : 7;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_DCM_LSB 7
|
||||
#define HE_SIG_A_SU_INFO_DCM_MSB 7
|
||||
#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080
|
||||
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_NSTS_LSB 23
|
||||
#define HE_SIG_A_SU_INFO_NSTS_MSB 25
|
||||
#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_CODING_LSB 7
|
||||
#define HE_SIG_A_SU_INFO_CODING_MSB 7
|
||||
#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080
|
||||
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100
|
||||
|
||||
#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_STBC_LSB 9
|
||||
#define HE_SIG_A_SU_INFO_STBC_MSB 9
|
||||
#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_TXBF_LSB 10
|
||||
#define HE_SIG_A_SU_INFO_TXBF_MSB 10
|
||||
#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400
|
||||
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
|
||||
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_SU_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_SU_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
50
drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h
Normal file
50
drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HE_SIG_B1_MU_INFO_H_
|
||||
#define _HE_SIG_B1_MU_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
|
||||
|
||||
struct he_sig_b1_mu_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ru_allocation : 8,
|
||||
reserved_0 : 23,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_0 : 23,
|
||||
ru_allocation : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff
|
||||
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00
|
||||
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
106
drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h
Normal file
106
drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HE_SIG_B2_MU_INFO_H_
|
||||
#define _HE_SIG_B2_MU_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
|
||||
|
||||
struct he_sig_b2_mu_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_spatial_config : 4,
|
||||
sta_mcs : 4,
|
||||
reserved_set_to_1 : 1,
|
||||
sta_coding : 1,
|
||||
reserved_0a : 7,
|
||||
nsts : 3,
|
||||
rx_integrity_check_passed : 1;
|
||||
uint32_t user_order : 8,
|
||||
cc_mask : 8,
|
||||
reserved_1a : 16;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
nsts : 3,
|
||||
reserved_0a : 7,
|
||||
sta_coding : 1,
|
||||
reserved_set_to_1 : 1,
|
||||
sta_mcs : 4,
|
||||
sta_spatial_config : 4,
|
||||
sta_id : 11;
|
||||
uint32_t reserved_1a : 16,
|
||||
cc_mask : 8,
|
||||
user_order : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_LSB 28
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_MSB 30
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
106
drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h
Normal file
106
drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HE_SIG_B2_OFDMA_INFO_H_
|
||||
#define _HE_SIG_B2_OFDMA_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
|
||||
|
||||
struct he_sig_b2_ofdma_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
nsts : 3,
|
||||
txbf : 1,
|
||||
sta_mcs : 4,
|
||||
sta_dcm : 1,
|
||||
sta_coding : 1,
|
||||
reserved_0 : 10,
|
||||
rx_integrity_check_passed : 1;
|
||||
uint32_t user_order : 8,
|
||||
cc_mask : 8,
|
||||
reserved_1a : 16;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_0 : 10,
|
||||
sta_coding : 1,
|
||||
sta_dcm : 1,
|
||||
sta_mcs : 4,
|
||||
txbf : 1,
|
||||
nsts : 3,
|
||||
sta_id : 11;
|
||||
uint32_t reserved_1a : 16,
|
||||
cc_mask : 8,
|
||||
user_order : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
141
drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h
Normal file
141
drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _HT_SIG_INFO_H_
|
||||
#define _HT_SIG_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_HT_SIG_INFO 2
|
||||
|
||||
struct ht_sig_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mcs : 7,
|
||||
cbw : 1,
|
||||
length : 16,
|
||||
reserved_0 : 8;
|
||||
uint32_t smoothing : 1,
|
||||
not_sounding : 1,
|
||||
ht_reserved : 1,
|
||||
aggregation : 1,
|
||||
stbc : 2,
|
||||
fec_coding : 1,
|
||||
short_gi : 1,
|
||||
num_ext_sp_str : 2,
|
||||
crc : 8,
|
||||
signal_tail : 6,
|
||||
reserved_1 : 7,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t reserved_0 : 8,
|
||||
length : 16,
|
||||
cbw : 1,
|
||||
mcs : 7;
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_1 : 7,
|
||||
signal_tail : 6,
|
||||
crc : 8,
|
||||
num_ext_sp_str : 2,
|
||||
short_gi : 1,
|
||||
fec_coding : 1,
|
||||
stbc : 2,
|
||||
aggregation : 1,
|
||||
ht_reserved : 1,
|
||||
not_sounding : 1,
|
||||
smoothing : 1;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define HT_SIG_INFO_MCS_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_MCS_LSB 0
|
||||
#define HT_SIG_INFO_MCS_MSB 6
|
||||
#define HT_SIG_INFO_MCS_MASK 0x0000007f
|
||||
|
||||
#define HT_SIG_INFO_CBW_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_CBW_LSB 7
|
||||
#define HT_SIG_INFO_CBW_MSB 7
|
||||
#define HT_SIG_INFO_CBW_MASK 0x00000080
|
||||
|
||||
#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_LENGTH_LSB 8
|
||||
#define HT_SIG_INFO_LENGTH_MSB 23
|
||||
#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
|
||||
|
||||
#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_RESERVED_0_LSB 24
|
||||
#define HT_SIG_INFO_RESERVED_0_MSB 31
|
||||
#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
|
||||
|
||||
#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_SMOOTHING_LSB 0
|
||||
#define HT_SIG_INFO_SMOOTHING_MSB 0
|
||||
#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
|
||||
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
|
||||
|
||||
#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_HT_RESERVED_LSB 2
|
||||
#define HT_SIG_INFO_HT_RESERVED_MSB 2
|
||||
#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
|
||||
|
||||
#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_AGGREGATION_LSB 3
|
||||
#define HT_SIG_INFO_AGGREGATION_MSB 3
|
||||
#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
|
||||
|
||||
#define HT_SIG_INFO_STBC_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_STBC_LSB 4
|
||||
#define HT_SIG_INFO_STBC_MSB 5
|
||||
#define HT_SIG_INFO_STBC_MASK 0x00000030
|
||||
|
||||
#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_FEC_CODING_LSB 6
|
||||
#define HT_SIG_INFO_FEC_CODING_MSB 6
|
||||
#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
|
||||
|
||||
#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_SHORT_GI_LSB 7
|
||||
#define HT_SIG_INFO_SHORT_GI_MSB 7
|
||||
#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
|
||||
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
|
||||
|
||||
#define HT_SIG_INFO_CRC_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_CRC_LSB 10
|
||||
#define HT_SIG_INFO_CRC_MSB 17
|
||||
#define HT_SIG_INFO_CRC_MASK 0x0003fc00
|
||||
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_RESERVED_1_LSB 24
|
||||
#define HT_SIG_INFO_RESERVED_1_MSB 30
|
||||
#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
|
||||
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
92
drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h
Normal file
92
drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _L_SIG_A_INFO_H_
|
||||
#define _L_SIG_A_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_L_SIG_A_INFO 1
|
||||
|
||||
struct l_sig_a_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rate : 4,
|
||||
lsig_reserved : 1,
|
||||
length : 12,
|
||||
parity : 1,
|
||||
tail : 6,
|
||||
pkt_type : 4,
|
||||
captured_implicit_sounding : 1,
|
||||
reserved : 2,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved : 2,
|
||||
captured_implicit_sounding : 1,
|
||||
pkt_type : 4,
|
||||
tail : 6,
|
||||
parity : 1,
|
||||
length : 12,
|
||||
lsig_reserved : 1,
|
||||
rate : 4;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define L_SIG_A_INFO_RATE_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_RATE_LSB 0
|
||||
#define L_SIG_A_INFO_RATE_MSB 3
|
||||
#define L_SIG_A_INFO_RATE_MASK 0x0000000f
|
||||
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010
|
||||
|
||||
#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_LENGTH_LSB 5
|
||||
#define L_SIG_A_INFO_LENGTH_MSB 16
|
||||
#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0
|
||||
|
||||
#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_PARITY_LSB 17
|
||||
#define L_SIG_A_INFO_PARITY_MSB 17
|
||||
#define L_SIG_A_INFO_PARITY_MASK 0x00020000
|
||||
|
||||
#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_TAIL_LSB 18
|
||||
#define L_SIG_A_INFO_TAIL_MSB 23
|
||||
#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_PKT_TYPE_LSB 24
|
||||
#define L_SIG_A_INFO_PKT_TYPE_MSB 27
|
||||
#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
|
||||
|
||||
#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_RESERVED_LSB 29
|
||||
#define L_SIG_A_INFO_RESERVED_MSB 30
|
||||
#define L_SIG_A_INFO_RESERVED_MASK 0x60000000
|
||||
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
57
drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h
Normal file
57
drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _L_SIG_B_INFO_H_
|
||||
#define _L_SIG_B_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_L_SIG_B_INFO 1
|
||||
|
||||
struct l_sig_b_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rate : 4,
|
||||
length : 12,
|
||||
reserved : 15,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved : 15,
|
||||
length : 12,
|
||||
rate : 4;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define L_SIG_B_INFO_RATE_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_RATE_LSB 0
|
||||
#define L_SIG_B_INFO_RATE_MSB 3
|
||||
#define L_SIG_B_INFO_RATE_MASK 0x0000000f
|
||||
|
||||
#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_LENGTH_LSB 4
|
||||
#define L_SIG_B_INFO_LENGTH_MSB 15
|
||||
#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0
|
||||
|
||||
#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_RESERVED_LSB 16
|
||||
#define L_SIG_B_INFO_RESERVED_MSB 30
|
||||
#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000
|
||||
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACRX_ABORT_REQUEST_INFO_H_
|
||||
#define _MACRX_ABORT_REQUEST_INFO_H_
|
||||
|
||||
#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
|
||||
|
||||
struct macrx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t macrx_abort_reason : 8,
|
||||
reserved_0 : 8;
|
||||
#else
|
||||
uint16_t reserved_0 : 8,
|
||||
macrx_abort_reason : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
|
||||
#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
|
||||
|
||||
#include "eht_sig_usr_mu_mimo_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
|
||||
|
||||
struct mactx_eht_sig_usr_mu_mimo {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x00008000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x003f0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x00400000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
97
drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h
Normal file
97
drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
|
||||
#define _MACTX_EHT_SIG_USR_OFDMA_H_
|
||||
|
||||
#include "eht_sig_usr_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
|
||||
|
||||
struct mactx_eht_sig_usr_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x000f0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x00100000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00200000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x00400000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
72
drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h
Normal file
72
drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_SU_H_
|
||||
#define _MACTX_EHT_SIG_USR_SU_H_
|
||||
|
||||
#include "eht_sig_usr_su_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 1
|
||||
|
||||
struct mactx_eht_sig_usr_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x000f0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x00100000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x00200000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x7fc00000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
142
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h
Normal file
142
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_MU_DL_H_
|
||||
#define _MACTX_HE_SIG_A_MU_DL_H_
|
||||
|
||||
#include "he_sig_a_mu_dl_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
|
||||
|
||||
struct mactx_he_sig_a_mu_dl {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
92
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h
Normal file
92
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_MU_UL_H_
|
||||
#define _MACTX_HE_SIG_A_MU_UL_H_
|
||||
|
||||
#include "he_sig_a_mu_ul_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
|
||||
|
||||
struct mactx_he_sig_a_mu_ul {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
167
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h
Normal file
167
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_SU_H_
|
||||
#define _MACTX_HE_SIG_A_SU_H_
|
||||
|
||||
#include "he_sig_a_su_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
|
||||
|
||||
struct mactx_he_sig_a_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
|
||||
#else
|
||||
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
47
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h
Normal file
47
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B1_MU_H_
|
||||
#define _MACTX_HE_SIG_B1_MU_H_
|
||||
|
||||
#include "he_sig_b1_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 1
|
||||
|
||||
struct mactx_he_sig_b1_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
87
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h
Normal file
87
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B2_MU_H_
|
||||
#define _MACTX_HE_SIG_B2_MU_H_
|
||||
|
||||
#include "he_sig_b2_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
|
||||
|
||||
struct mactx_he_sig_b2_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
87
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h
Normal file
87
drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
|
||||
#define _MACTX_HE_SIG_B2_OFDMA_H_
|
||||
|
||||
#include "he_sig_b2_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
|
||||
|
||||
struct mactx_he_sig_b2_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
|
||||
#else
|
||||
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
112
drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h
Normal file
112
drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_HT_SIG_H_
|
||||
#define _MACTX_HT_SIG_H_
|
||||
|
||||
#include "ht_sig_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HT_SIG 2
|
||||
|
||||
struct mactx_ht_sig {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct ht_sig_info mactx_ht_sig_info_details;
|
||||
#else
|
||||
struct ht_sig_info mactx_ht_sig_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 4
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 5
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 10
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 17
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
77
drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h
Normal file
77
drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_L_SIG_A_H_
|
||||
#define _MACTX_L_SIG_A_H_
|
||||
|
||||
#include "l_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_L_SIG_A 1
|
||||
|
||||
struct mactx_l_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_a_info mactx_l_sig_a_info_details;
|
||||
#else
|
||||
struct l_sig_a_info mactx_l_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
52
drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h
Normal file
52
drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_L_SIG_B_H_
|
||||
#define _MACTX_L_SIG_B_H_
|
||||
|
||||
#include "l_sig_b_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_L_SIG_B 1
|
||||
|
||||
struct mactx_l_sig_b {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_b_info mactx_l_sig_b_info_details;
|
||||
#else
|
||||
struct l_sig_b_info mactx_l_sig_b_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
365
drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h
Normal file
365
drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h
Normal file
|
|
@ -0,0 +1,365 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_PHY_DESC_H_
|
||||
#define _MACTX_PHY_DESC_H_
|
||||
|
||||
#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
|
||||
|
||||
struct mactx_phy_desc {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 16,
|
||||
bf_type : 2,
|
||||
wait_sifs : 2,
|
||||
dot11b_preamble_type : 1,
|
||||
pkt_type : 4,
|
||||
su_or_mu : 2,
|
||||
mu_type : 1,
|
||||
bandwidth : 3,
|
||||
channel_capture : 1;
|
||||
uint32_t mcs : 4,
|
||||
global_ofdma_mimo_enable : 1,
|
||||
reserved_1a : 1,
|
||||
stbc : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_trigger_frame_embedded : 1,
|
||||
tx_pwr_shared : 8,
|
||||
tx_pwr_unshared : 8,
|
||||
measure_power : 1,
|
||||
tpc_glut_self_cal : 1,
|
||||
back_to_back_transmission_expected : 1,
|
||||
heavy_clip_nss : 3,
|
||||
txbf_per_packet_no_csd_no_walsh : 1;
|
||||
uint32_t ndp : 2,
|
||||
ul_flag : 1,
|
||||
triggered : 1,
|
||||
ap_pkt_bw : 3,
|
||||
ru_position_start : 8,
|
||||
pcu_ppdu_setup_start_reason : 3,
|
||||
tlv_source : 1,
|
||||
reserved_2a : 2,
|
||||
nss : 3,
|
||||
stream_offset : 3,
|
||||
reserved_2b : 2,
|
||||
clpc_enable : 1,
|
||||
mu_ndp : 1,
|
||||
response_expected : 1;
|
||||
uint32_t rx_chain_mask : 8,
|
||||
rx_chain_mask_valid : 1,
|
||||
ant_sel_valid : 1,
|
||||
ant_sel : 1,
|
||||
cp_setting : 2,
|
||||
he_ppdu_subtype : 2,
|
||||
active_channel : 3,
|
||||
generate_phyrx_tx_start_timing : 1,
|
||||
ltf_size : 2,
|
||||
ru_size_updated_v2 : 4,
|
||||
reserved_3c : 1,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
#else
|
||||
uint32_t channel_capture : 1,
|
||||
bandwidth : 3,
|
||||
mu_type : 1,
|
||||
su_or_mu : 2,
|
||||
pkt_type : 4,
|
||||
dot11b_preamble_type : 1,
|
||||
wait_sifs : 2,
|
||||
bf_type : 2,
|
||||
reserved_0a : 16;
|
||||
uint32_t txbf_per_packet_no_csd_no_walsh : 1,
|
||||
heavy_clip_nss : 3,
|
||||
back_to_back_transmission_expected : 1,
|
||||
tpc_glut_self_cal : 1,
|
||||
measure_power : 1,
|
||||
tx_pwr_unshared : 8,
|
||||
tx_pwr_shared : 8,
|
||||
dot11ax_trigger_frame_embedded : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
stbc : 1,
|
||||
reserved_1a : 1,
|
||||
global_ofdma_mimo_enable : 1,
|
||||
mcs : 4;
|
||||
uint32_t response_expected : 1,
|
||||
mu_ndp : 1,
|
||||
clpc_enable : 1,
|
||||
reserved_2b : 2,
|
||||
stream_offset : 3,
|
||||
nss : 3,
|
||||
reserved_2a : 2,
|
||||
tlv_source : 1,
|
||||
pcu_ppdu_setup_start_reason : 3,
|
||||
ru_position_start : 8,
|
||||
ap_pkt_bw : 3,
|
||||
triggered : 1,
|
||||
ul_flag : 1,
|
||||
ndp : 2;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_3c : 1,
|
||||
ru_size_updated_v2 : 4,
|
||||
ltf_size : 2,
|
||||
generate_phyrx_tx_start_timing : 1,
|
||||
active_channel : 3,
|
||||
he_ppdu_subtype : 2,
|
||||
cp_setting : 2,
|
||||
ant_sel : 1,
|
||||
ant_sel_valid : 1,
|
||||
rx_chain_mask_valid : 1,
|
||||
rx_chain_mask : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_LSB 0
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_MSB 15
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff
|
||||
|
||||
#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_BF_TYPE_LSB 16
|
||||
#define MACTX_PHY_DESC_BF_TYPE_MSB 17
|
||||
#define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000
|
||||
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000
|
||||
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000
|
||||
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_LSB 21
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_MSB 24
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000
|
||||
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_LSB 25
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_MSB 26
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000
|
||||
|
||||
#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_MU_TYPE_LSB 27
|
||||
#define MACTX_PHY_DESC_MU_TYPE_MSB 27
|
||||
#define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000
|
||||
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_LSB 28
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_MSB 30
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000
|
||||
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000
|
||||
|
||||
#define MACTX_PHY_DESC_MCS_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_MCS_LSB 0
|
||||
#define MACTX_PHY_DESC_MCS_MSB 3
|
||||
#define MACTX_PHY_DESC_MCS_MASK 0x0000000f
|
||||
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_LSB 5
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_MSB 5
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020
|
||||
|
||||
#define MACTX_PHY_DESC_STBC_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_STBC_LSB 6
|
||||
#define MACTX_PHY_DESC_STBC_MSB 6
|
||||
#define MACTX_PHY_DESC_STBC_MASK 0x00000040
|
||||
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080
|
||||
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100
|
||||
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00
|
||||
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000
|
||||
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_LSB 25
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_MSB 25
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000
|
||||
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000
|
||||
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000
|
||||
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000
|
||||
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000
|
||||
|
||||
#define MACTX_PHY_DESC_NDP_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_NDP_LSB 0
|
||||
#define MACTX_PHY_DESC_NDP_MSB 1
|
||||
#define MACTX_PHY_DESC_NDP_MASK 0x00000003
|
||||
|
||||
#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_UL_FLAG_LSB 2
|
||||
#define MACTX_PHY_DESC_UL_FLAG_MSB 2
|
||||
#define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004
|
||||
|
||||
#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_TRIGGERED_LSB 3
|
||||
#define MACTX_PHY_DESC_TRIGGERED_MSB 3
|
||||
#define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008
|
||||
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070
|
||||
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80
|
||||
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000
|
||||
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_LSB 19
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_MSB 20
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000
|
||||
|
||||
#define MACTX_PHY_DESC_NSS_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_NSS_LSB 21
|
||||
#define MACTX_PHY_DESC_NSS_MSB 23
|
||||
#define MACTX_PHY_DESC_NSS_MASK 0x00e00000
|
||||
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_LSB 27
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_MSB 28
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000
|
||||
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000
|
||||
|
||||
#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_MU_NDP_LSB 30
|
||||
#define MACTX_PHY_DESC_MU_NDP_MSB 30
|
||||
#define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000
|
||||
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000
|
||||
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff
|
||||
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100
|
||||
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200
|
||||
|
||||
#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_ANT_SEL_LSB 10
|
||||
#define MACTX_PHY_DESC_ANT_SEL_MSB 10
|
||||
#define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400
|
||||
|
||||
#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_CP_SETTING_LSB 11
|
||||
#define MACTX_PHY_DESC_CP_SETTING_MSB 12
|
||||
#define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800
|
||||
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000
|
||||
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000
|
||||
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000
|
||||
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_LSB 19
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_MSB 20
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000
|
||||
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_LSB 25
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_MSB 25
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000
|
||||
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
|
||||
|
||||
#endif
|
||||
132
drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h
Normal file
132
drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
|
||||
#define _MACTX_U_SIG_EHT_SU_MU_H_
|
||||
|
||||
#include "u_sig_eht_su_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
|
||||
|
||||
struct mactx_u_sig_eht_su_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
|
||||
#else
|
||||
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x00000007
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x01f00000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x02000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 2
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 2
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 3
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 7
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 8
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 8
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x00000100
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 9
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 10
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x00000600
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 11
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 15
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 16
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 19
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 27
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 29
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x38000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 30
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 30
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x40000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
107
drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h
Normal file
107
drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_U_SIG_EHT_TB_H_
|
||||
#define _MACTX_U_SIG_EHT_TB_H_
|
||||
|
||||
#include "u_sig_eht_tb_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
|
||||
|
||||
struct mactx_u_sig_eht_tb {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
|
||||
#else
|
||||
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x00000007
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x03f00000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 2
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 2
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 3
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 10
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f8
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 11
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 15
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f800
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 16
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 19
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 30
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
478
drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h
Normal file
478
drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h
Normal file
|
|
@ -0,0 +1,478 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_USER_DESC_COMMON_H_
|
||||
#define _MACTX_USER_DESC_COMMON_H_
|
||||
|
||||
#include "unallocated_ru_160_info.h"
|
||||
#include "ru_allocation_160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
|
||||
|
||||
struct mactx_user_desc_common {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t num_users : 6,
|
||||
reserved_0b : 5,
|
||||
ltf_size : 2,
|
||||
reserved_0c : 3,
|
||||
he_stf_long : 1,
|
||||
reserved_0d : 7,
|
||||
num_users_he_sigb_band0 : 8;
|
||||
uint32_t num_ltf_symbols : 3,
|
||||
reserved_1a : 5,
|
||||
num_users_he_sigb_band1 : 8,
|
||||
reserved_1b : 16;
|
||||
uint32_t packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension : 3,
|
||||
reserved : 2,
|
||||
he_sigb_dcm : 1,
|
||||
reserved_2b : 7,
|
||||
he_sigb_compression : 1,
|
||||
reserved_2c : 15;
|
||||
uint32_t he_sigb_0_mcs : 3,
|
||||
reserved_3a : 13,
|
||||
num_he_sigb_sym : 5,
|
||||
center_ru_0 : 1,
|
||||
center_ru_1 : 1,
|
||||
reserved_3b : 1,
|
||||
ftm_en : 1,
|
||||
pe_nss : 3,
|
||||
pe_ltf_size : 2,
|
||||
pe_content : 1,
|
||||
pe_chain_csd_en : 1;
|
||||
struct ru_allocation_160_info ru_allocation_0123_details;
|
||||
struct ru_allocation_160_info ru_allocation_4567_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_0_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_1_details;
|
||||
uint32_t num_data_symbols : 16,
|
||||
ndp_ru_tone_set_index : 7,
|
||||
ndp_feedback_status : 1,
|
||||
doppler_indication : 1,
|
||||
reserved_14a : 7;
|
||||
uint32_t spatial_reuse : 16,
|
||||
reserved_15a : 16;
|
||||
#else
|
||||
uint32_t num_users_he_sigb_band0 : 8,
|
||||
reserved_0d : 7,
|
||||
he_stf_long : 1,
|
||||
reserved_0c : 3,
|
||||
ltf_size : 2,
|
||||
reserved_0b : 5,
|
||||
num_users : 6;
|
||||
uint32_t reserved_1b : 16,
|
||||
num_users_he_sigb_band1 : 8,
|
||||
reserved_1a : 5,
|
||||
num_ltf_symbols : 3;
|
||||
uint32_t reserved_2c : 15,
|
||||
he_sigb_compression : 1,
|
||||
reserved_2b : 7,
|
||||
he_sigb_dcm : 1,
|
||||
reserved : 2,
|
||||
packet_extension : 3,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2;
|
||||
uint32_t pe_chain_csd_en : 1,
|
||||
pe_content : 1,
|
||||
pe_ltf_size : 2,
|
||||
pe_nss : 3,
|
||||
ftm_en : 1,
|
||||
reserved_3b : 1,
|
||||
center_ru_1 : 1,
|
||||
center_ru_0 : 1,
|
||||
num_he_sigb_sym : 5,
|
||||
reserved_3a : 13,
|
||||
he_sigb_0_mcs : 3;
|
||||
struct ru_allocation_160_info ru_allocation_0123_details;
|
||||
struct ru_allocation_160_info ru_allocation_4567_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_0_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_1_details;
|
||||
uint32_t reserved_14a : 7,
|
||||
doppler_indication : 1,
|
||||
ndp_feedback_status : 1,
|
||||
ndp_ru_tone_set_index : 7,
|
||||
num_data_symbols : 16;
|
||||
uint32_t reserved_15a : 16,
|
||||
spatial_reuse : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x0000003f
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x000007c0
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x00001800
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x0000e000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x00010000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x00fe0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0xff000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 2
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x00000007
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 3
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 7
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f8
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 8
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x00000038
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x000000c0
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x00000100
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x0000fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x00010000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0xfffe0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 2
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x00000007
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 3
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff8
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 20
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 21
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 21
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x00200000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 22
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 22
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x00400000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x00800000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 24
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x01000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 25
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 27
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 28
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 29
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x30000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 30
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 30
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x40000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 31
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x80000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x00000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x00fc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x00000014
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x00000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0xfffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000001c
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x00000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x00fc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x00000024
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x00000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0xfffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000002c
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000034
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 7
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000034
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000034
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000034
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x00000038
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x0000ffff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x00000038
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x007f0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x00000038
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x00800000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x00000038
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x01000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x00000038
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0xfe000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000003c
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000003c
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
190
drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h
Normal file
190
drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h
Normal file
|
|
@ -0,0 +1,190 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_USER_DESC_PER_USER_H_
|
||||
#define _MACTX_USER_DESC_PER_USER_H_
|
||||
|
||||
#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4
|
||||
|
||||
struct mactx_user_desc_per_user {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t psdu_length : 24,
|
||||
reserved_0a : 8;
|
||||
uint32_t ru_start_index : 8,
|
||||
ru_size : 4,
|
||||
reserved_1b : 4,
|
||||
ofdma_mu_mimo_enabled : 1,
|
||||
nss : 3,
|
||||
stream_offset : 3,
|
||||
reserved_1c : 1,
|
||||
mcs : 4,
|
||||
dcm : 1,
|
||||
reserved_1d : 3;
|
||||
uint32_t fec_type : 1,
|
||||
reserved_2a : 7,
|
||||
user_bf_type : 2,
|
||||
reserved_2b : 6,
|
||||
drop_user_cbf : 1,
|
||||
reserved_2c : 7,
|
||||
ldpc_extra_symbol : 1,
|
||||
force_extra_symbol : 1,
|
||||
reserved_2d : 6;
|
||||
uint32_t sw_peer_id : 16,
|
||||
per_user_subband_mask : 16;
|
||||
#else
|
||||
uint32_t reserved_0a : 8,
|
||||
psdu_length : 24;
|
||||
uint32_t reserved_1d : 3,
|
||||
dcm : 1,
|
||||
mcs : 4,
|
||||
reserved_1c : 1,
|
||||
stream_offset : 3,
|
||||
nss : 3,
|
||||
ofdma_mu_mimo_enabled : 1,
|
||||
reserved_1b : 4,
|
||||
ru_size : 4,
|
||||
ru_start_index : 8;
|
||||
uint32_t reserved_2d : 6,
|
||||
force_extra_symbol : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
reserved_2c : 7,
|
||||
drop_user_cbf : 1,
|
||||
reserved_2b : 6,
|
||||
user_bf_type : 2,
|
||||
reserved_2a : 7,
|
||||
fec_type : 1;
|
||||
uint32_t per_user_subband_mask : 16,
|
||||
sw_peer_id : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x00ffffff
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0xff000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 7
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 8
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 11
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f00
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 12
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 15
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x00010000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_LSB 17
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_MSB 19
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e0000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 20
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 22
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x00700000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x00800000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_MSB 27
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_LSB 28
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_MSB 28
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x10000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x00000004
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 29
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe0000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x00000001
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x000000fe
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x00000300
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000fc00
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x00010000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x00fe0000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x01000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x02000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x00000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0xfc000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 15
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000c
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
122
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h
Normal file
122
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_A_H_
|
||||
#define _MACTX_VHT_SIG_A_H_
|
||||
|
||||
#include "vht_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
|
||||
|
||||
struct mactx_vht_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_a_info mactx_vht_sig_a_info_details;
|
||||
#else
|
||||
struct vht_sig_a_info mactx_vht_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
192
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h
Normal file
192
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU160_H_
|
||||
#define _MACTX_VHT_SIG_B_MU160_H_
|
||||
|
||||
#include "vht_sig_b_mu160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
|
||||
|
||||
struct mactx_vht_sig_b_mu160 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe0000000
|
||||
|
||||
#endif
|
||||
57
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h
Normal file
57
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU20_H_
|
||||
#define _MACTX_VHT_SIG_B_MU20_H_
|
||||
|
||||
#include "vht_sig_b_mu20_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 1
|
||||
|
||||
struct mactx_vht_sig_b_mu20 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x0000ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x000f0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x1c000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0xe0000000
|
||||
|
||||
#endif
|
||||
77
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h
Normal file
77
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU40_H_
|
||||
#define _MACTX_VHT_SIG_B_MU40_H_
|
||||
|
||||
#include "vht_sig_b_mu40_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
|
||||
|
||||
struct mactx_vht_sig_b_mu40 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x0001ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x001e0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x07e00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x18000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 16
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 17
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 20
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 21
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 26
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 27
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf8000000
|
||||
|
||||
#endif
|
||||
112
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h
Normal file
112
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU80_H_
|
||||
#define _MACTX_VHT_SIG_B_MU80_H_
|
||||
|
||||
#include "vht_sig_b_mu80_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
|
||||
|
||||
struct mactx_vht_sig_b_mu80 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe0000000
|
||||
|
||||
#endif
|
||||
232
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h
Normal file
232
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h
Normal file
|
|
@ -0,0 +1,232 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU160_H_
|
||||
#define _MACTX_VHT_SIG_B_SU160_H_
|
||||
|
||||
#include "vht_sig_b_su160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
|
||||
|
||||
struct mactx_vht_sig_b_su160 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x00000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x00000014
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x00000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000001c
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
57
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h
Normal file
57
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU20_H_
|
||||
#define _MACTX_VHT_SIG_B_SU20_H_
|
||||
|
||||
#include "vht_sig_b_su20_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 1
|
||||
|
||||
struct mactx_vht_sig_b_su20 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x0001ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x000e0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x7c000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
82
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h
Normal file
82
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU40_H_
|
||||
#define _MACTX_VHT_SIG_B_SU40_H_
|
||||
|
||||
#include "vht_sig_b_su40_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
|
||||
|
||||
struct mactx_vht_sig_b_su40 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x00180000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x07e00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x78000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 18
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 19
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x00180000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 26
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 27
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x78000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
132
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h
Normal file
132
drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU80_H_
|
||||
#define _MACTX_VHT_SIG_B_SU80_H_
|
||||
|
||||
#include "vht_sig_b_su80_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
|
||||
|
||||
struct mactx_vht_sig_b_su80 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x60000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
64
drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h
Normal file
64
drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MLO_STA_ID_DETAILS_H_
|
||||
#define _MLO_STA_ID_DETAILS_H_
|
||||
|
||||
#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
|
||||
|
||||
struct mlo_sta_id_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t nstr_mlo_sta_id : 10,
|
||||
block_self_ml_sync : 1,
|
||||
block_partner_ml_sync : 1,
|
||||
nstr_mlo_sta_id_valid : 1,
|
||||
reserved_0a : 3;
|
||||
#else
|
||||
uint16_t reserved_0a : 3,
|
||||
nstr_mlo_sta_id_valid : 1,
|
||||
block_partner_ml_sync : 1,
|
||||
block_self_ml_sync : 1,
|
||||
nstr_mlo_sta_id : 10;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
#endif
|
||||
78
drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h
Normal file
78
drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MON_BUFFER_ADDR_H_
|
||||
#define _MON_BUFFER_ADDR_H_
|
||||
|
||||
#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3
|
||||
|
||||
struct mon_buffer_addr {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
uint32_t dma_length : 12,
|
||||
reserved_2a : 4,
|
||||
msdu_continuation : 1,
|
||||
truncated : 1,
|
||||
reserved_2b : 14;
|
||||
#else
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
uint32_t reserved_2b : 14,
|
||||
truncated : 1,
|
||||
msdu_continuation : 1,
|
||||
reserved_2a : 4,
|
||||
dma_length : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff
|
||||
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000
|
||||
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000
|
||||
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000
|
||||
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000
|
||||
|
||||
#endif
|
||||
106
drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h
Normal file
106
drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MON_DESTINATION_RING_H_
|
||||
#define _MON_DESTINATION_RING_H_
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
|
||||
|
||||
struct mon_destination_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t stat_buf_virt_addr_31_0 : 32;
|
||||
uint32_t stat_buf_virt_addr_63_32 : 32;
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t end_offset : 12,
|
||||
reserved_3a : 2,
|
||||
link_info : 2,
|
||||
end_reason : 2,
|
||||
initiator : 1,
|
||||
empty_descriptor : 1,
|
||||
ring_id : 8,
|
||||
looping_count : 4;
|
||||
#else
|
||||
uint32_t stat_buf_virt_addr_31_0 : 32;
|
||||
uint32_t stat_buf_virt_addr_63_32 : 32;
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t looping_count : 4,
|
||||
ring_id : 8,
|
||||
empty_descriptor : 1,
|
||||
initiator : 1,
|
||||
end_reason : 2,
|
||||
link_info : 2,
|
||||
reserved_3a : 2,
|
||||
end_offset : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008
|
||||
#define MON_DESTINATION_RING_PPDU_ID_LSB 0
|
||||
#define MON_DESTINATION_RING_PPDU_ID_MSB 31
|
||||
#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff
|
||||
|
||||
#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_END_OFFSET_LSB 0
|
||||
#define MON_DESTINATION_RING_END_OFFSET_MSB 11
|
||||
#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff
|
||||
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_LSB 12
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_MSB 13
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000
|
||||
|
||||
#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_LINK_INFO_LSB 14
|
||||
#define MON_DESTINATION_RING_LINK_INFO_MSB 15
|
||||
#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000
|
||||
|
||||
#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_END_REASON_LSB 16
|
||||
#define MON_DESTINATION_RING_END_REASON_MSB 17
|
||||
#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000
|
||||
|
||||
#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_INITIATOR_LSB 18
|
||||
#define MON_DESTINATION_RING_INITIATOR_MSB 18
|
||||
#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000
|
||||
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000
|
||||
|
||||
#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_RING_ID_LSB 20
|
||||
#define MON_DESTINATION_RING_RING_ID_MSB 27
|
||||
#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000
|
||||
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
#endif
|
||||
71
drivers/staging/fw-api/hw/peach/v1/mon_drop.h
Normal file
71
drivers/staging/fw-api/hw/peach/v1/mon_drop.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MON_DROP_H_
|
||||
#define _MON_DROP_H_
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DROP 2
|
||||
|
||||
struct mon_drop {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t ppdu_drop_cnt : 10,
|
||||
mpdu_drop_cnt : 10,
|
||||
tlv_drop_cnt : 10,
|
||||
end_of_ppdu_seen : 1,
|
||||
reserved_1a : 1;
|
||||
#else
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t reserved_1a : 1,
|
||||
end_of_ppdu_seen : 1,
|
||||
tlv_drop_cnt : 10,
|
||||
mpdu_drop_cnt : 10,
|
||||
ppdu_drop_cnt : 10;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_DROP_PPDU_ID_OFFSET 0x00000000
|
||||
#define MON_DROP_PPDU_ID_LSB 0
|
||||
#define MON_DROP_PPDU_ID_MSB 31
|
||||
#define MON_DROP_PPDU_ID_MASK 0xffffffff
|
||||
|
||||
#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x00000004
|
||||
#define MON_DROP_PPDU_DROP_CNT_LSB 0
|
||||
#define MON_DROP_PPDU_DROP_CNT_MSB 9
|
||||
#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff
|
||||
|
||||
#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x00000004
|
||||
#define MON_DROP_MPDU_DROP_CNT_LSB 10
|
||||
#define MON_DROP_MPDU_DROP_CNT_MSB 19
|
||||
#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc00
|
||||
|
||||
#define MON_DROP_TLV_DROP_CNT_OFFSET 0x00000004
|
||||
#define MON_DROP_TLV_DROP_CNT_LSB 20
|
||||
#define MON_DROP_TLV_DROP_CNT_MSB 29
|
||||
#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff00000
|
||||
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000004
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_LSB 30
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_MSB 30
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x40000000
|
||||
|
||||
#define MON_DROP_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MON_DROP_RESERVED_1A_LSB 31
|
||||
#define MON_DROP_RESERVED_1A_MSB 31
|
||||
#define MON_DROP_RESERVED_1A_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
66
drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h
Normal file
66
drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MON_INGRESS_RING_H_
|
||||
#define _MON_INGRESS_RING_H_
|
||||
|
||||
#include "buffer_addr_info.h"
|
||||
#define NUM_OF_DWORDS_MON_INGRESS_RING 4
|
||||
|
||||
struct mon_ingress_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct buffer_addr_info buffer_addr_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
#else
|
||||
struct buffer_addr_info buffer_addr_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
187
drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h
Normal file
187
drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h
Normal file
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#ifndef __MSMHWIOBASE_H__
|
||||
#define __MSMHWIOBASE_H__
|
||||
|
||||
#define WCSS_WCSS_BASE 0x00000000
|
||||
#define WCSS_WCSS_BASE_SIZE 0x01000000
|
||||
#define WCSS_WCSS_BASE_PHYS 0x00000000
|
||||
|
||||
#define QDSS_STM_SIZE_BASE 0x00100000
|
||||
#define QDSS_STM_SIZE_BASE_SIZE 0x100000000
|
||||
#define QDSS_STM_SIZE_BASE_PHYS 0x00100000
|
||||
|
||||
#define BOOT_ROM_SIZE_BASE 0x00200000
|
||||
#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000
|
||||
#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000
|
||||
|
||||
#define SYSTEM_IRAM_SIZE_BASE 0x00400000
|
||||
#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000
|
||||
#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000
|
||||
|
||||
#define BOOT_ROM_START_ADDRESS_BASE 0x01200000
|
||||
#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000
|
||||
#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000
|
||||
|
||||
#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff
|
||||
#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000
|
||||
#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff
|
||||
|
||||
#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000
|
||||
#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000
|
||||
#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000
|
||||
|
||||
#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff
|
||||
#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000
|
||||
#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff
|
||||
|
||||
#define QDSS_STM_BASE 0x01800000
|
||||
#define QDSS_STM_BASE_SIZE 0x100000000
|
||||
#define QDSS_STM_BASE_PHYS 0x01800000
|
||||
|
||||
#define QDSS_STM_END_BASE 0x018fffff
|
||||
#define QDSS_STM_END_BASE_SIZE 0x100000000
|
||||
#define QDSS_STM_END_BASE_PHYS 0x018fffff
|
||||
|
||||
#define TLMM_BASE 0x01900000
|
||||
#define TLMM_BASE_SIZE 0x00200000
|
||||
#define TLMM_BASE_PHYS 0x01900000
|
||||
|
||||
#define CORE_TOP_CSR_BASE 0x01b00000
|
||||
#define CORE_TOP_CSR_BASE_SIZE 0x00040000
|
||||
#define CORE_TOP_CSR_BASE_PHYS 0x01b00000
|
||||
|
||||
#define BLSP1_BLSP_BASE 0x01b40000
|
||||
#define BLSP1_BLSP_BASE_SIZE 0x00040000
|
||||
#define BLSP1_BLSP_BASE_PHYS 0x01b40000
|
||||
|
||||
#define SOC_WFSS_CE_REG_BASE 0x01b80000
|
||||
#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000
|
||||
#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000
|
||||
|
||||
#define WL_TLMM_BASE 0x01bc0000
|
||||
#define WL_TLMM_BASE_SIZE 0x00020000
|
||||
#define WL_TLMM_BASE_PHYS 0x01bc0000
|
||||
|
||||
#define MEMSS_CSR_BASE 0x01be0000
|
||||
#define MEMSS_CSR_BASE_SIZE 0x0000001c
|
||||
#define MEMSS_CSR_BASE_PHYS 0x01be0000
|
||||
|
||||
#define TSENS_SROT_BASE 0x01bf0000
|
||||
#define TSENS_SROT_BASE_SIZE 0x00001000
|
||||
#define TSENS_SROT_BASE_PHYS 0x01bf0000
|
||||
|
||||
#define TSENS_TM_BASE 0x01bf1000
|
||||
#define TSENS_TM_BASE_SIZE 0x00001000
|
||||
#define TSENS_TM_BASE_PHYS 0x01bf1000
|
||||
|
||||
#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000
|
||||
#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000
|
||||
#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000
|
||||
|
||||
#define QDSS_WRAPPER_TOP_BASE 0x01c80000
|
||||
#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd
|
||||
#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000
|
||||
|
||||
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000
|
||||
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000
|
||||
#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000
|
||||
|
||||
#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000
|
||||
#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
|
||||
#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
|
||||
|
||||
#define SECURITY_CONTROL_WLAN_BASE 0x01e20000
|
||||
#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
|
||||
#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
|
||||
|
||||
#define EDPD_CAL_ACC_BASE 0x01e28000
|
||||
#define EDPD_CAL_ACC_BASE_SIZE 0x00003000
|
||||
#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000
|
||||
|
||||
#define CPR_CX_CPR3_BASE 0x01e30000
|
||||
#define CPR_CX_CPR3_BASE_SIZE 0x00004000
|
||||
#define CPR_CX_CPR3_BASE_PHYS 0x01e30000
|
||||
|
||||
#define CPR_MX_CPR3_BASE 0x01e34000
|
||||
#define CPR_MX_CPR3_BASE_SIZE 0x00004000
|
||||
#define CPR_MX_CPR3_BASE_PHYS 0x01e34000
|
||||
|
||||
#define GCC_GCC_BASE 0x01e40000
|
||||
#define GCC_GCC_BASE_SIZE 0x000003e8
|
||||
#define GCC_GCC_BASE_PHYS 0x01e40000
|
||||
|
||||
#define PRNG_PRNG_TOP_BASE 0x01e50000
|
||||
#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000
|
||||
#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000
|
||||
|
||||
#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000
|
||||
#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
|
||||
#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
|
||||
|
||||
#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000
|
||||
#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
|
||||
#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
|
||||
|
||||
#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000
|
||||
#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
|
||||
#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
|
||||
|
||||
#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000
|
||||
#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
|
||||
#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
|
||||
|
||||
#define RRI_PREFETCH_REG_BASE 0x01e70000
|
||||
#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000
|
||||
#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000
|
||||
|
||||
#define SYSTEM_NOC_BASE 0x01e80000
|
||||
#define SYSTEM_NOC_BASE_SIZE 0x0000a000
|
||||
#define SYSTEM_NOC_BASE_PHYS 0x01e80000
|
||||
|
||||
#define PC_NOC_BASE 0x01f00000
|
||||
#define PC_NOC_BASE_SIZE 0x00003880
|
||||
#define PC_NOC_BASE_PHYS 0x01f00000
|
||||
|
||||
#define WLAON_WL_AON_REG_BASE 0x01f80000
|
||||
#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8
|
||||
#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
|
||||
|
||||
#define SYSPM_SYSPM_REG_BASE 0x01f82000
|
||||
#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
|
||||
#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
|
||||
|
||||
#define PMU_WLAN_PMU_TOP_BASE 0x01f88000
|
||||
#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340
|
||||
#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000
|
||||
|
||||
#define PMU_NOC_BASE 0x01f8a000
|
||||
#define PMU_NOC_BASE_SIZE 0x00000080
|
||||
#define PMU_NOC_BASE_PHYS 0x01f8a000
|
||||
|
||||
#define PCIE_ATU_REGION_BASE 0x04000000
|
||||
#define PCIE_ATU_REGION_BASE_SIZE 0x100000000
|
||||
#define PCIE_ATU_REGION_BASE_PHYS 0x04000000
|
||||
|
||||
#define PCIE_ATU_REGION_SIZE_BASE 0x40000000
|
||||
#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000
|
||||
#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000
|
||||
|
||||
#define PCIE_ATU_REGION_END_BASE 0x43ffffff
|
||||
#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000
|
||||
#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff
|
||||
|
||||
#endif
|
||||
112
drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h
Normal file
112
drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __MSMHWIOREG_H__
|
||||
#define __MSMHWIOREG_H__
|
||||
|
||||
#include "msmhwiobase.h"
|
||||
|
||||
#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
|
||||
#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc
|
||||
#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2
|
||||
#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \
|
||||
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \
|
||||
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \
|
||||
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
|
||||
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \
|
||||
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \
|
||||
in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \
|
||||
out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
|
||||
out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
|
||||
#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
|
||||
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
|
||||
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
|
||||
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
|
||||
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
|
||||
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
|
||||
in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
|
||||
out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
|
||||
out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
|
||||
#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
|
||||
#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400)
|
||||
#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
|
||||
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
|
||||
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
|
||||
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
|
||||
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
|
||||
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
|
||||
in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
|
||||
out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
|
||||
out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400)
|
||||
#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058)
|
||||
|
||||
|
||||
#endif
|
||||
120
drivers/staging/fw-api/hw/peach/v1/no_ack_report.h
Normal file
120
drivers/staging/fw-api/hw/peach/v1/no_ack_report.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _NO_ACK_REPORT_H_
|
||||
#define _NO_ACK_REPORT_H_
|
||||
|
||||
#define NUM_OF_DWORDS_NO_ACK_REPORT 4
|
||||
|
||||
struct no_ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t no_ack_transmit_reason : 4,
|
||||
macrx_abort_reason : 4,
|
||||
phyrx_abort_reason : 8,
|
||||
frame_control : 16;
|
||||
uint32_t rx_ppdu_duration : 24,
|
||||
sr_ppdu_during_obss : 1,
|
||||
selfgen_response_reason_to_sr_ppdu : 4,
|
||||
reserved_1 : 3;
|
||||
uint32_t pre_bt_broadcast_status_details : 12,
|
||||
first_bt_broadcast_status_details : 12,
|
||||
reserved_2 : 8;
|
||||
uint32_t second_bt_broadcast_status_details : 12,
|
||||
reserved_3 : 20;
|
||||
#else
|
||||
uint32_t frame_control : 16,
|
||||
phyrx_abort_reason : 8,
|
||||
macrx_abort_reason : 4,
|
||||
no_ack_transmit_reason : 4;
|
||||
uint32_t reserved_1 : 3,
|
||||
selfgen_response_reason_to_sr_ppdu : 4,
|
||||
sr_ppdu_during_obss : 1,
|
||||
rx_ppdu_duration : 24;
|
||||
uint32_t reserved_2 : 8,
|
||||
first_bt_broadcast_status_details : 12,
|
||||
pre_bt_broadcast_status_details : 12;
|
||||
uint32_t reserved_3 : 20,
|
||||
second_bt_broadcast_status_details : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
|
||||
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0
|
||||
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00
|
||||
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff
|
||||
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000
|
||||
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RESERVED_1_LSB 29
|
||||
#define NO_ACK_REPORT_RESERVED_1_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_RESERVED_2_LSB 24
|
||||
#define NO_ACK_REPORT_RESERVED_2_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000
|
||||
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_RESERVED_3_LSB 12
|
||||
#define NO_ACK_REPORT_RESERVED_3_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000
|
||||
|
||||
#endif
|
||||
834
drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h
Normal file
834
drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h
Normal file
|
|
@ -0,0 +1,834 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _OFDMA_TRIGGER_DETAILS_H_
|
||||
#define _OFDMA_TRIGGER_DETAILS_H_
|
||||
|
||||
#include "mlo_sta_id_details.h"
|
||||
#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22
|
||||
|
||||
struct ofdma_trigger_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ax_trigger_source : 1,
|
||||
rx_trigger_frame_user_source : 2,
|
||||
received_bandwidth : 3,
|
||||
txop_duration_all_ones : 1,
|
||||
eht_trigger_response : 1,
|
||||
pre_rssi_comb : 8,
|
||||
rssi_comb : 8,
|
||||
rxpcu_pcie_l0_req_duration : 8;
|
||||
uint32_t he_trigger_ul_ppdu_length : 5,
|
||||
he_trigger_ru_allocation : 8,
|
||||
he_trigger_dl_tx_power : 5,
|
||||
he_trigger_ul_target_rssi : 5,
|
||||
he_trigger_ul_mcs : 2,
|
||||
he_trigger_reserved : 1,
|
||||
bss_color : 6;
|
||||
uint32_t trigger_type : 4,
|
||||
lsig_response_length : 12,
|
||||
cascade_indication : 1,
|
||||
carrier_sense : 1,
|
||||
bandwidth : 2,
|
||||
cp_ltf_size : 2,
|
||||
mu_mimo_ltf_mode : 1,
|
||||
number_of_ltfs : 3,
|
||||
stbc : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
ap_tx_power_lsb_part : 4;
|
||||
uint32_t ap_tx_power_msb_part : 2,
|
||||
packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
spatial_reuse : 16,
|
||||
doppler : 1,
|
||||
he_siga_reserved : 9,
|
||||
reserved_3b : 1;
|
||||
uint32_t aid12 : 12,
|
||||
ru_allocation : 9,
|
||||
mcs : 4,
|
||||
dcm : 1,
|
||||
start_spatial_stream : 3,
|
||||
number_of_spatial_stream : 3;
|
||||
uint32_t target_rssi : 7,
|
||||
coding_type : 1,
|
||||
mpdu_mu_spacing_factor : 2,
|
||||
tid_aggregation_limit : 3,
|
||||
reserved_5b : 1,
|
||||
prefered_ac : 2,
|
||||
bar_control_ack_policy : 1,
|
||||
bar_control_multi_tid : 1,
|
||||
bar_control_compressed_bitmap : 1,
|
||||
bar_control_reserved : 9,
|
||||
bar_control_tid_info : 4;
|
||||
uint32_t nr0_per_tid_info_reserved : 12,
|
||||
nr0_per_tid_info_tid_value : 4,
|
||||
nr0_start_seq_ctrl_frag_number : 4,
|
||||
nr0_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr1_per_tid_info_reserved : 12,
|
||||
nr1_per_tid_info_tid_value : 4,
|
||||
nr1_start_seq_ctrl_frag_number : 4,
|
||||
nr1_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr2_per_tid_info_reserved : 12,
|
||||
nr2_per_tid_info_tid_value : 4,
|
||||
nr2_start_seq_ctrl_frag_number : 4,
|
||||
nr2_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr3_per_tid_info_reserved : 12,
|
||||
nr3_per_tid_info_tid_value : 4,
|
||||
nr3_start_seq_ctrl_frag_number : 4,
|
||||
nr3_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr4_per_tid_info_reserved : 12,
|
||||
nr4_per_tid_info_tid_value : 4,
|
||||
nr4_start_seq_ctrl_frag_number : 4,
|
||||
nr4_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr5_per_tid_info_reserved : 12,
|
||||
nr5_per_tid_info_tid_value : 4,
|
||||
nr5_start_seq_ctrl_frag_number : 4,
|
||||
nr5_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr6_per_tid_info_reserved : 12,
|
||||
nr6_per_tid_info_tid_value : 4,
|
||||
nr6_start_seq_ctrl_frag_number : 4,
|
||||
nr6_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr7_per_tid_info_reserved : 12,
|
||||
nr7_per_tid_info_tid_value : 4,
|
||||
nr7_start_seq_ctrl_frag_number : 4,
|
||||
nr7_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t fb_segment_retransmission_bitmap : 8,
|
||||
reserved_14a : 2,
|
||||
u_sig_puncture_pattern_encoding : 6,
|
||||
dot11be_puncture_bitmap : 16;
|
||||
uint32_t rx_chain_mask : 8,
|
||||
rx_duration_field : 16,
|
||||
scrambler_seed : 7,
|
||||
rx_chain_mask_type : 1;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint16_t normalized_pre_rssi_comb : 8,
|
||||
normalized_rssi_comb : 8;
|
||||
uint32_t sw_peer_id : 16,
|
||||
response_tx_duration : 16;
|
||||
uint32_t __reserved_g_0005_trigger_subtype : 4,
|
||||
tbr_trigger_common_info_79_68 : 12,
|
||||
tbr_trigger_sound_reserved_20_12 : 9,
|
||||
i2r_rep : 3,
|
||||
tbr_trigger_sound_reserved_25_24 : 2,
|
||||
reserved_18a : 1,
|
||||
qos_null_only_response_tx : 1;
|
||||
uint32_t tbr_trigger_sound_sac : 16,
|
||||
reserved_19a : 8,
|
||||
u_sig_reserved2 : 5,
|
||||
reserved_19b : 3;
|
||||
uint32_t eht_special_aid12 : 12,
|
||||
phy_version : 3,
|
||||
bandwidth_ext : 2,
|
||||
eht_spatial_reuse : 8,
|
||||
u_sig_reserved1 : 7;
|
||||
uint32_t eht_trigger_special_user_info_71_40 : 32;
|
||||
#else
|
||||
uint32_t rxpcu_pcie_l0_req_duration : 8,
|
||||
rssi_comb : 8,
|
||||
pre_rssi_comb : 8,
|
||||
eht_trigger_response : 1,
|
||||
txop_duration_all_ones : 1,
|
||||
received_bandwidth : 3,
|
||||
rx_trigger_frame_user_source : 2,
|
||||
ax_trigger_source : 1;
|
||||
uint32_t bss_color : 6,
|
||||
he_trigger_reserved : 1,
|
||||
he_trigger_ul_mcs : 2,
|
||||
he_trigger_ul_target_rssi : 5,
|
||||
he_trigger_dl_tx_power : 5,
|
||||
he_trigger_ru_allocation : 8,
|
||||
he_trigger_ul_ppdu_length : 5;
|
||||
uint32_t ap_tx_power_lsb_part : 4,
|
||||
ldpc_extra_symbol : 1,
|
||||
stbc : 1,
|
||||
number_of_ltfs : 3,
|
||||
mu_mimo_ltf_mode : 1,
|
||||
cp_ltf_size : 2,
|
||||
bandwidth : 2,
|
||||
carrier_sense : 1,
|
||||
cascade_indication : 1,
|
||||
lsig_response_length : 12,
|
||||
trigger_type : 4;
|
||||
uint32_t reserved_3b : 1,
|
||||
he_siga_reserved : 9,
|
||||
doppler : 1,
|
||||
spatial_reuse : 16,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2,
|
||||
ap_tx_power_msb_part : 2;
|
||||
uint32_t number_of_spatial_stream : 3,
|
||||
start_spatial_stream : 3,
|
||||
dcm : 1,
|
||||
mcs : 4,
|
||||
ru_allocation : 9,
|
||||
aid12 : 12;
|
||||
uint32_t bar_control_tid_info : 4,
|
||||
bar_control_reserved : 9,
|
||||
bar_control_compressed_bitmap : 1,
|
||||
bar_control_multi_tid : 1,
|
||||
bar_control_ack_policy : 1,
|
||||
prefered_ac : 2,
|
||||
reserved_5b : 1,
|
||||
tid_aggregation_limit : 3,
|
||||
mpdu_mu_spacing_factor : 2,
|
||||
coding_type : 1,
|
||||
target_rssi : 7;
|
||||
uint32_t nr0_start_seq_ctrl_start_seq_number : 12,
|
||||
nr0_start_seq_ctrl_frag_number : 4,
|
||||
nr0_per_tid_info_tid_value : 4,
|
||||
nr0_per_tid_info_reserved : 12;
|
||||
uint32_t nr1_start_seq_ctrl_start_seq_number : 12,
|
||||
nr1_start_seq_ctrl_frag_number : 4,
|
||||
nr1_per_tid_info_tid_value : 4,
|
||||
nr1_per_tid_info_reserved : 12;
|
||||
uint32_t nr2_start_seq_ctrl_start_seq_number : 12,
|
||||
nr2_start_seq_ctrl_frag_number : 4,
|
||||
nr2_per_tid_info_tid_value : 4,
|
||||
nr2_per_tid_info_reserved : 12;
|
||||
uint32_t nr3_start_seq_ctrl_start_seq_number : 12,
|
||||
nr3_start_seq_ctrl_frag_number : 4,
|
||||
nr3_per_tid_info_tid_value : 4,
|
||||
nr3_per_tid_info_reserved : 12;
|
||||
uint32_t nr4_start_seq_ctrl_start_seq_number : 12,
|
||||
nr4_start_seq_ctrl_frag_number : 4,
|
||||
nr4_per_tid_info_tid_value : 4,
|
||||
nr4_per_tid_info_reserved : 12;
|
||||
uint32_t nr5_start_seq_ctrl_start_seq_number : 12,
|
||||
nr5_start_seq_ctrl_frag_number : 4,
|
||||
nr5_per_tid_info_tid_value : 4,
|
||||
nr5_per_tid_info_reserved : 12;
|
||||
uint32_t nr6_start_seq_ctrl_start_seq_number : 12,
|
||||
nr6_start_seq_ctrl_frag_number : 4,
|
||||
nr6_per_tid_info_tid_value : 4,
|
||||
nr6_per_tid_info_reserved : 12;
|
||||
uint32_t nr7_start_seq_ctrl_start_seq_number : 12,
|
||||
nr7_start_seq_ctrl_frag_number : 4,
|
||||
nr7_per_tid_info_tid_value : 4,
|
||||
nr7_per_tid_info_reserved : 12;
|
||||
uint32_t dot11be_puncture_bitmap : 16,
|
||||
u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_14a : 2,
|
||||
fb_segment_retransmission_bitmap : 8;
|
||||
uint32_t rx_chain_mask_type : 1,
|
||||
scrambler_seed : 7,
|
||||
rx_duration_field : 16,
|
||||
rx_chain_mask : 8;
|
||||
uint32_t normalized_rssi_comb : 8,
|
||||
normalized_pre_rssi_comb : 8;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint32_t response_tx_duration : 16,
|
||||
sw_peer_id : 16;
|
||||
uint32_t qos_null_only_response_tx : 1,
|
||||
reserved_18a : 1,
|
||||
tbr_trigger_sound_reserved_25_24 : 2,
|
||||
i2r_rep : 3,
|
||||
tbr_trigger_sound_reserved_20_12 : 9,
|
||||
tbr_trigger_common_info_79_68 : 12,
|
||||
__reserved_g_0005_trigger_subtype : 4;
|
||||
uint32_t reserved_19b : 3,
|
||||
u_sig_reserved2 : 5,
|
||||
reserved_19a : 8,
|
||||
tbr_trigger_sound_sac : 16;
|
||||
uint32_t u_sig_reserved1 : 7,
|
||||
eht_spatial_reuse : 8,
|
||||
bandwidth_ext : 2,
|
||||
phy_version : 3,
|
||||
eht_special_aid12 : 12;
|
||||
uint32_t eht_trigger_special_user_info_71_40 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000001
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x00000006
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x00000038
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x00000040
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x00000080
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x0000ff00
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x00ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x00000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0xff000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 5
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe0
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 13
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 18
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 22
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x01800000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x02000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x00000004
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0000fff0
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x00010000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x00020000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x000c0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x00300000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x00400000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x03800000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x04000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x08000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x00000008
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0xf0000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 1
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x00000003
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 2
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000010
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 5
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe0
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 21
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 21
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x00200000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 22
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 30
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x80000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x00000010
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x00000010
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x001ff000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x00000010
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x01e00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x00000010
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x02000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x00000010
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x1c000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x00000010
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0xe0000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 6
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x00000080
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 8
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 9
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x00000300
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c00
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 13
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 13
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x00002000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 14
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x00010000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x00020000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 18
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 18
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x00040000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff80000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x00000014
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf0000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x00000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x00000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000001c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000001c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000001c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000001c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x00000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x00000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x00000024
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x00000024
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000024
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000024
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x00000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x00000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000002c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000002c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000002c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000002c
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x00000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x00000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x00000034
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x00000034
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000034
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000034
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x00000038
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x000000ff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x00000038
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x00000300
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000038
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000fc00
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000038
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0xffff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000003c
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000003c
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 8
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff00
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000003c
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 30
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000003c
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x80000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x00000040
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0xff000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x00000044
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x00000044
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x0000000f
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x0000fff0
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x01ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x0e000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x30000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x40000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x00000048
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x80000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000004c
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000004c
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000004c
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000004c
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 29
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe0000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x00000050
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x00000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x00000050
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x00007000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x00000050
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x00018000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x00000050
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x01fe0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x00000050
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0xfe000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x00000054
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
2282
drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h
Normal file
2282
drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h
Normal file
File diff suppressed because it is too large
Load diff
473
drivers/staging/fw-api/hw/peach/v1/pdg_response.h
Normal file
473
drivers/staging/fw-api/hw/peach/v1/pdg_response.h
Normal file
|
|
@ -0,0 +1,473 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PDG_RESPONSE_H_
|
||||
#define _PDG_RESPONSE_H_
|
||||
|
||||
#include "pdg_response_rate_setting.h"
|
||||
#define NUM_OF_DWORDS_PDG_RESPONSE 12
|
||||
|
||||
struct pdg_response {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct pdg_response_rate_setting hw_response_rate_info;
|
||||
uint32_t hw_response_tx_duration : 16,
|
||||
rx_duration_field : 16;
|
||||
uint32_t punctured_response_transmission : 1,
|
||||
cca_subband_channel_bonding_mask : 16,
|
||||
scrambler_seed_override : 2,
|
||||
response_density_valid : 1,
|
||||
response_density : 5,
|
||||
more_data : 1,
|
||||
duration_indication : 1,
|
||||
relayed_frame : 1,
|
||||
address_indicator : 1,
|
||||
bandwidth : 3;
|
||||
uint32_t ack_id : 16,
|
||||
block_ack_bitmap : 16;
|
||||
uint32_t response_frame_type : 4,
|
||||
ack_id_ext : 10,
|
||||
ftm_en : 1,
|
||||
group_id : 6,
|
||||
sta_partial_aid : 11;
|
||||
uint32_t ndp_ba_start_seq_ctrl : 12,
|
||||
active_channel : 3,
|
||||
txop_duration_all_ones : 1,
|
||||
frame_length : 16;
|
||||
#else
|
||||
struct pdg_response_rate_setting hw_response_rate_info;
|
||||
uint32_t rx_duration_field : 16,
|
||||
hw_response_tx_duration : 16;
|
||||
uint32_t bandwidth : 3,
|
||||
address_indicator : 1,
|
||||
relayed_frame : 1,
|
||||
duration_indication : 1,
|
||||
more_data : 1,
|
||||
response_density : 5,
|
||||
response_density_valid : 1,
|
||||
scrambler_seed_override : 2,
|
||||
cca_subband_channel_bonding_mask : 16,
|
||||
punctured_response_transmission : 1;
|
||||
uint32_t block_ack_bitmap : 16,
|
||||
ack_id : 16;
|
||||
uint32_t sta_partial_aid : 11,
|
||||
group_id : 6,
|
||||
ftm_en : 1,
|
||||
ack_id_ext : 10,
|
||||
response_frame_type : 4;
|
||||
uint32_t frame_length : 16,
|
||||
txop_duration_all_ones : 1,
|
||||
active_channel : 3,
|
||||
ndp_ba_start_seq_ctrl : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x1e000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x20000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x40000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x80000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 18
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x00070000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 19
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 26
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f80000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 27
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 29
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x38000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 30
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 30
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x40000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x80000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x00000070
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x00000080
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x00ff0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0xff000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 8
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 9
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x00000300
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c00
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 14
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 23
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x00002000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x00008000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x001c0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x00200000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x04000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0xf8000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 3
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 4
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 8
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 9
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x00000300
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x00000400
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x00003800
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 14
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 18
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 20
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f00000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000001c
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff
|
||||
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000001c
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 16
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 31
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff0000
|
||||
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x0001fffe
|
||||
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x00060000
|
||||
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x00080000
|
||||
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x01f00000
|
||||
|
||||
#define PDG_RESPONSE_MORE_DATA_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_MORE_DATA_LSB 25
|
||||
#define PDG_RESPONSE_MORE_DATA_MSB 25
|
||||
#define PDG_RESPONSE_MORE_DATA_MASK 0x02000000
|
||||
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_LSB 26
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_MSB 26
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x04000000
|
||||
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_LSB 27
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_MSB 27
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x08000000
|
||||
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x10000000
|
||||
|
||||
#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x00000020
|
||||
#define PDG_RESPONSE_BANDWIDTH_LSB 29
|
||||
#define PDG_RESPONSE_BANDWIDTH_MSB 31
|
||||
#define PDG_RESPONSE_BANDWIDTH_MASK 0xe0000000
|
||||
|
||||
#define PDG_RESPONSE_ACK_ID_OFFSET 0x00000024
|
||||
#define PDG_RESPONSE_ACK_ID_LSB 0
|
||||
#define PDG_RESPONSE_ACK_ID_MSB 15
|
||||
#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff
|
||||
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x00000024
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 16
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 31
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff0000
|
||||
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x00000028
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x00000028
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_LSB 4
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_MSB 13
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x00003ff0
|
||||
|
||||
#define PDG_RESPONSE_FTM_EN_OFFSET 0x00000028
|
||||
#define PDG_RESPONSE_FTM_EN_LSB 14
|
||||
#define PDG_RESPONSE_FTM_EN_MSB 14
|
||||
#define PDG_RESPONSE_FTM_EN_MASK 0x00004000
|
||||
|
||||
#define PDG_RESPONSE_GROUP_ID_OFFSET 0x00000028
|
||||
#define PDG_RESPONSE_GROUP_ID_LSB 15
|
||||
#define PDG_RESPONSE_GROUP_ID_MSB 20
|
||||
#define PDG_RESPONSE_GROUP_ID_MASK 0x001f8000
|
||||
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x00000028
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0xffe00000
|
||||
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000002c
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 0
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 11
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff
|
||||
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000002c
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 12
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 14
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x00007000
|
||||
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000002c
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 15
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 15
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x00008000
|
||||
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000002c
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_LSB 16
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_MSB 31
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
414
drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h
Normal file
414
drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h
Normal file
|
|
@ -0,0 +1,414 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PDG_RESPONSE_RATE_SETTING_H_
|
||||
#define _PDG_RESPONSE_RATE_SETTING_H_
|
||||
|
||||
#include "mlo_sta_id_details.h"
|
||||
#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
|
||||
|
||||
struct pdg_response_rate_setting {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 1,
|
||||
tx_antenna_sector_ctrl : 24,
|
||||
pkt_type : 4,
|
||||
smoothing : 1,
|
||||
ldpc : 1,
|
||||
stbc : 1;
|
||||
uint32_t alt_tx_pwr : 8,
|
||||
alt_min_tx_pwr : 8,
|
||||
alt_nss : 3,
|
||||
alt_tx_chain_mask : 8,
|
||||
alt_bw : 3,
|
||||
stf_ltf_3db_boost : 1,
|
||||
force_extra_symbol : 1;
|
||||
uint32_t alt_rate_mcs : 4,
|
||||
nss : 3,
|
||||
dpd_enable : 1,
|
||||
tx_pwr : 8,
|
||||
min_tx_pwr : 8,
|
||||
tx_chain_mask : 8;
|
||||
uint32_t reserved_3a : 8,
|
||||
sgi : 2,
|
||||
rate_mcs : 4,
|
||||
reserved_3b : 2,
|
||||
tx_pwr_1 : 8,
|
||||
alt_tx_pwr_1 : 8;
|
||||
uint32_t aggregation : 1,
|
||||
dot11ax_bss_color_id : 6,
|
||||
dot11ax_spatial_reuse : 4,
|
||||
dot11ax_cp_ltf_size : 2,
|
||||
dot11ax_dcm : 1,
|
||||
dot11ax_doppler_indication : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_min_packet_extension : 2,
|
||||
dot11ax_pe_nss : 3,
|
||||
dot11ax_pe_content : 1,
|
||||
dot11ax_pe_ltf_size : 2,
|
||||
dot11ax_chain_csd_en : 1,
|
||||
dot11ax_pe_chain_csd_en : 1,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
reserved_4a : 5;
|
||||
uint32_t dot11ax_ext_ru_start_index : 4,
|
||||
dot11ax_ext_ru_size : 4,
|
||||
eht_duplicate_mode : 2,
|
||||
he_sigb_dcm : 1,
|
||||
he_sigb_0_mcs : 3,
|
||||
num_he_sigb_sym : 5,
|
||||
required_response_time_source : 1,
|
||||
reserved_5a : 6,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint16_t required_response_time : 12,
|
||||
dot11be_params_placeholder : 4;
|
||||
#else
|
||||
uint32_t stbc : 1,
|
||||
ldpc : 1,
|
||||
smoothing : 1,
|
||||
pkt_type : 4,
|
||||
tx_antenna_sector_ctrl : 24,
|
||||
reserved_0a : 1;
|
||||
uint32_t force_extra_symbol : 1,
|
||||
stf_ltf_3db_boost : 1,
|
||||
alt_bw : 3,
|
||||
alt_tx_chain_mask : 8,
|
||||
alt_nss : 3,
|
||||
alt_min_tx_pwr : 8,
|
||||
alt_tx_pwr : 8;
|
||||
uint32_t tx_chain_mask : 8,
|
||||
min_tx_pwr : 8,
|
||||
tx_pwr : 8,
|
||||
dpd_enable : 1,
|
||||
nss : 3,
|
||||
alt_rate_mcs : 4;
|
||||
uint32_t alt_tx_pwr_1 : 8,
|
||||
tx_pwr_1 : 8,
|
||||
reserved_3b : 2,
|
||||
rate_mcs : 4,
|
||||
sgi : 2,
|
||||
reserved_3a : 8;
|
||||
uint32_t reserved_4a : 5,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
dot11ax_pe_chain_csd_en : 1,
|
||||
dot11ax_chain_csd_en : 1,
|
||||
dot11ax_pe_ltf_size : 2,
|
||||
dot11ax_pe_content : 1,
|
||||
dot11ax_pe_nss : 3,
|
||||
dot11ax_min_packet_extension : 2,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_doppler_indication : 1,
|
||||
dot11ax_dcm : 1,
|
||||
dot11ax_cp_ltf_size : 2,
|
||||
dot11ax_spatial_reuse : 4,
|
||||
dot11ax_bss_color_id : 6,
|
||||
aggregation : 1;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_5a : 6,
|
||||
required_response_time_source : 1,
|
||||
num_he_sigb_sym : 5,
|
||||
he_sigb_0_mcs : 3,
|
||||
he_sigb_dcm : 1,
|
||||
eht_duplicate_mode : 2,
|
||||
dot11ax_ext_ru_size : 4,
|
||||
dot11ax_ext_ru_start_index : 4;
|
||||
uint32_t dot11be_params_placeholder : 4,
|
||||
required_response_time : 12;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
|
||||
|
||||
#endif
|
||||
99
drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h
Normal file
99
drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PDG_TX_REQ_H_
|
||||
#define _PDG_TX_REQ_H_
|
||||
|
||||
#define NUM_OF_DWORDS_PDG_TX_REQ 2
|
||||
|
||||
struct pdg_tx_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_reason : 2,
|
||||
use_puncture_pattern : 2,
|
||||
req_bw : 3,
|
||||
puncture_pattern_number : 6,
|
||||
reserved_0b : 1,
|
||||
req_paprd : 1,
|
||||
duration_field_boundary_valid : 1,
|
||||
duration_field_boundary : 16;
|
||||
uint32_t puncture_subband_mask : 16,
|
||||
reserved_0c : 16;
|
||||
#else
|
||||
uint32_t duration_field_boundary : 16,
|
||||
duration_field_boundary_valid : 1,
|
||||
req_paprd : 1,
|
||||
reserved_0b : 1,
|
||||
puncture_pattern_number : 6,
|
||||
req_bw : 3,
|
||||
use_puncture_pattern : 2,
|
||||
tx_reason : 2;
|
||||
uint32_t reserved_0c : 16,
|
||||
puncture_subband_mask : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PDG_TX_REQ_TX_REASON_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_TX_REASON_LSB 0
|
||||
#define PDG_TX_REQ_TX_REASON_MSB 1
|
||||
#define PDG_TX_REQ_TX_REASON_MASK 0x00000003
|
||||
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x0000000c
|
||||
|
||||
#define PDG_TX_REQ_REQ_BW_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_REQ_BW_LSB 4
|
||||
#define PDG_TX_REQ_REQ_BW_MSB 6
|
||||
#define PDG_TX_REQ_REQ_BW_MASK 0x00000070
|
||||
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x00001f80
|
||||
|
||||
#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_RESERVED_0B_LSB 13
|
||||
#define PDG_TX_REQ_RESERVED_0B_MSB 13
|
||||
#define PDG_TX_REQ_RESERVED_0B_MASK 0x00002000
|
||||
|
||||
#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_REQ_PAPRD_LSB 14
|
||||
#define PDG_TX_REQ_REQ_PAPRD_MSB 14
|
||||
#define PDG_TX_REQ_REQ_PAPRD_MASK 0x00004000
|
||||
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x00008000
|
||||
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x00000000
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0xffff0000
|
||||
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x00000004
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 0
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 15
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff
|
||||
|
||||
#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x00000004
|
||||
#define PDG_TX_REQ_RESERVED_0C_LSB 16
|
||||
#define PDG_TX_REQ_RESERVED_0C_MSB 31
|
||||
#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
|
||||
#define _PHYRX_ABORT_REQUEST_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
|
||||
|
||||
struct phyrx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phyrx_abort_reason : 8,
|
||||
phy_enters_nap_state : 1,
|
||||
phy_enters_defer_state : 1,
|
||||
gain_change_by_main : 1,
|
||||
gain_change_by_bt : 1,
|
||||
main_tx_indication : 1,
|
||||
bt_tx_indication : 1,
|
||||
concurrent_mode : 1,
|
||||
reserved_0 : 1,
|
||||
receive_duration : 16;
|
||||
#else
|
||||
uint32_t receive_duration : 16,
|
||||
reserved_0 : 1,
|
||||
concurrent_mode : 1,
|
||||
bt_tx_indication : 1,
|
||||
main_tx_indication : 1,
|
||||
gain_change_by_bt : 1,
|
||||
gain_change_by_main : 1,
|
||||
phy_enters_defer_state : 1,
|
||||
phy_enters_nap_state : 1,
|
||||
phyrx_abort_reason : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11
|
||||
#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12
|
||||
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12
|
||||
#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13
|
||||
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13
|
||||
#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14
|
||||
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14
|
||||
#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
176
drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h
Normal file
176
drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_COMMON_USER_INFO_H_
|
||||
#define _PHYRX_COMMON_USER_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
|
||||
|
||||
struct phyrx_common_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t receive_duration : 16,
|
||||
reserved_0a : 16;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_1a : 9,
|
||||
obss_nav_update_enable : 1,
|
||||
obss_nav_value : 16;
|
||||
uint32_t eht_ppdu_type : 2,
|
||||
bss_color_id : 6,
|
||||
dl_ul_flag : 1,
|
||||
txop_duration : 7,
|
||||
cp_setting : 2,
|
||||
ltf_size : 2,
|
||||
spatial_reuse : 4,
|
||||
rx_ndp : 1,
|
||||
dot11be_su_extended : 1,
|
||||
reserved_2a : 6;
|
||||
uint32_t eht_duplicate : 2,
|
||||
eht_sig_cmn_field_type : 2,
|
||||
doppler_indication : 1,
|
||||
sta_id : 11,
|
||||
puncture_bitmap : 16;
|
||||
#else
|
||||
uint32_t reserved_0a : 16,
|
||||
receive_duration : 16;
|
||||
uint32_t obss_nav_value : 16,
|
||||
obss_nav_update_enable : 1,
|
||||
reserved_1a : 9,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
uint32_t reserved_2a : 6,
|
||||
dot11be_su_extended : 1,
|
||||
rx_ndp : 1,
|
||||
spatial_reuse : 4,
|
||||
ltf_size : 2,
|
||||
cp_setting : 2,
|
||||
txop_duration : 7,
|
||||
dl_ul_flag : 1,
|
||||
bss_color_id : 6,
|
||||
eht_ppdu_type : 2;
|
||||
uint32_t puncture_bitmap : 16,
|
||||
sta_id : 11,
|
||||
doppler_indication : 1,
|
||||
eht_sig_cmn_field_type : 2,
|
||||
eht_duplicate : 2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x00000000
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000004
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 0
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 5
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 6
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 14
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007fc0
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x00000004
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x00008000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x00000004
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 16
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 31
|
||||
#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x00000003
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x000000fc
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x00000100
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x0000fe00
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x00030000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x000c0000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x00f00000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x01000000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x02000000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x00000008
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0xfc000000
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000c
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 0
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 1
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x00000003
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000c
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 2
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 3
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000c
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 4
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 4
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x00000010
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000c
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 5
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe0
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000c
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 16
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 31
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
142
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h
Normal file
142
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
|
||||
#define _PHYRX_HE_SIG_A_MU_DL_H_
|
||||
|
||||
#include "he_sig_a_mu_dl_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
|
||||
|
||||
struct phyrx_he_sig_a_mu_dl {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
92
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h
Normal file
92
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
|
||||
#define _PHYRX_HE_SIG_A_MU_UL_H_
|
||||
|
||||
#include "he_sig_a_mu_ul_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
|
||||
|
||||
struct phyrx_he_sig_a_mu_ul {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
167
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h
Normal file
167
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h
Normal file
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_A_SU_H_
|
||||
#define _PHYRX_HE_SIG_A_SU_H_
|
||||
|
||||
#include "he_sig_a_su_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
|
||||
|
||||
struct phyrx_he_sig_a_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
|
||||
#else
|
||||
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
47
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h
Normal file
47
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_B1_MU_H_
|
||||
#define _PHYRX_HE_SIG_B1_MU_H_
|
||||
|
||||
#include "he_sig_b1_mu_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
|
||||
|
||||
struct phyrx_he_sig_b1_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
87
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h
Normal file
87
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_B2_MU_H_
|
||||
#define _PHYRX_HE_SIG_B2_MU_H_
|
||||
|
||||
#include "he_sig_b2_mu_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
|
||||
|
||||
struct phyrx_he_sig_b2_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
87
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h
Normal file
87
drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
|
||||
#define _PHYRX_HE_SIG_B2_OFDMA_H_
|
||||
|
||||
#include "he_sig_b2_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
|
||||
|
||||
struct phyrx_he_sig_b2_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
|
||||
#else
|
||||
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
112
drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h
Normal file
112
drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_HT_SIG_H_
|
||||
#define _PHYRX_HT_SIG_H_
|
||||
|
||||
#include "ht_sig_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
|
||||
|
||||
struct phyrx_ht_sig {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct ht_sig_info phyrx_ht_sig_info_details;
|
||||
#else
|
||||
struct ht_sig_info phyrx_ht_sig_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 5
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 17
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
77
drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h
Normal file
77
drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_L_SIG_A_H_
|
||||
#define _PHYRX_L_SIG_A_H_
|
||||
|
||||
#include "l_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
|
||||
|
||||
struct phyrx_l_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_a_info phyrx_l_sig_a_info_details;
|
||||
#else
|
||||
struct l_sig_a_info phyrx_l_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
52
drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h
Normal file
52
drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_L_SIG_B_H_
|
||||
#define _PHYRX_L_SIG_B_H_
|
||||
|
||||
#include "l_sig_b_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
|
||||
|
||||
struct phyrx_l_sig_b {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_b_info phyrx_l_sig_b_info_details;
|
||||
#else
|
||||
struct l_sig_b_info phyrx_l_sig_b_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
347
drivers/staging/fw-api/hw/peach/v1/phyrx_location.h
Normal file
347
drivers/staging/fw-api/hw/peach/v1/phyrx_location.h
Normal file
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_LOCATION_H_
|
||||
#define _PHYRX_LOCATION_H_
|
||||
|
||||
#include "rx_location_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_LOCATION 28
|
||||
|
||||
struct phyrx_location {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct rx_location_info rx_location_info_details;
|
||||
#else
|
||||
struct rx_location_info rx_location_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x00000001
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x00000002
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x0000000c
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x000000f0
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x00000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0xff000000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 7
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 8
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x00000004
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 23
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x00000004
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 24
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff000000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 8
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 19
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 20
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 23
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f00000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 24
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff000000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0xff000000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000014
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x00000018
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000001c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x00000020
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x00000024
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x00000024
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x00000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x00000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000002c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000002c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x00000030
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x00000030
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x00000034
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x00000034
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x00000038
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x00000038
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000003c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000003c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x00000040
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x00000040
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x00000044
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x00000044
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x00000048
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x00000048
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000004c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000004c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x00000050
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x00000050
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x00000054
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x00000054
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x00000058
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x00000058
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000005c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000005c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x00000060
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x00000060
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x00000064
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x00000064
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x00000068
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x00000068
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
|
||||
#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3
|
||||
|
||||
struct phyrx_other_receive_info_ru_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ru_details_channel_0 : 32;
|
||||
uint32_t ru_details_channel_1 : 32;
|
||||
uint32_t spare : 32;
|
||||
#else
|
||||
uint32_t ru_details_channel_0 : 32;
|
||||
uint32_t ru_details_channel_1 : 32;
|
||||
uint32_t spare : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 31
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x00000008
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
432
drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h
Normal file
432
drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h
Normal file
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_PKT_END_H_
|
||||
#define _PHYRX_PKT_END_H_
|
||||
|
||||
#include "phyrx_pkt_end_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_PKT_END 24
|
||||
|
||||
struct phyrx_pkt_end {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct phyrx_pkt_end_info rx_pkt_end_details;
|
||||
#else
|
||||
struct phyrx_pkt_end_info rx_pkt_end_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000010
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x000000c0
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x00000058
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 31
|
||||
#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
457
drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h
Normal file
457
drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h
Normal file
|
|
@ -0,0 +1,457 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_PKT_END_INFO_H_
|
||||
#define _PHYRX_PKT_END_INFO_H_
|
||||
|
||||
#include "receive_rssi_info.h"
|
||||
#include "rx_timing_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
|
||||
|
||||
struct phyrx_pkt_end_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t __reserved_g_0001 : 1,
|
||||
location_info_valid : 1,
|
||||
timing_info_valid : 1,
|
||||
rssi_info_valid : 1,
|
||||
reserved_0a : 1,
|
||||
frameless_frame_received : 1,
|
||||
reserved_0b : 2,
|
||||
rssi_comb : 8,
|
||||
reserved_0c : 16;
|
||||
struct rx_timing_info rx_timing_info_details;
|
||||
struct receive_rssi_info post_rssi_info_details;
|
||||
uint32_t phy_sw_status_31_0 : 32;
|
||||
uint32_t phy_sw_status_63_32 : 32;
|
||||
#else
|
||||
uint32_t reserved_0c : 16,
|
||||
rssi_comb : 8,
|
||||
reserved_0b : 2,
|
||||
frameless_frame_received : 1,
|
||||
reserved_0a : 1,
|
||||
rssi_info_valid : 1,
|
||||
timing_info_valid : 1,
|
||||
location_info_valid : 1,
|
||||
__reserved_g_0001 : 1;
|
||||
struct rx_timing_info rx_timing_info_details;
|
||||
struct receive_rssi_info post_rssi_info_details;
|
||||
uint32_t phy_sw_status_31_0 : 32;
|
||||
uint32_t phy_sw_status_63_32 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1
|
||||
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1
|
||||
#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002
|
||||
|
||||
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2
|
||||
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2
|
||||
#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3
|
||||
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3
|
||||
#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010
|
||||
|
||||
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5
|
||||
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5
|
||||
#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31
|
||||
#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
811
drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h
Normal file
811
drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h
Normal file
|
|
@ -0,0 +1,811 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_RSSI_LEGACY_H_
|
||||
#define _PHYRX_RSSI_LEGACY_H_
|
||||
|
||||
#include "receive_rssi_info.h"
|
||||
#include "receive_pkt_start_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
|
||||
|
||||
struct phyrx_rssi_legacy {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct receive_pkt_start_info rx_pkt_start_details;
|
||||
uint32_t sw_phy_meta_data : 32;
|
||||
uint32_t reserved_4a : 32;
|
||||
uint32_t reserved_6a : 32;
|
||||
uint32_t reserved_7a : 32;
|
||||
struct receive_rssi_info pre_rssi_info_details;
|
||||
struct receive_rssi_info preamble_rssi_info_details;
|
||||
uint32_t pre_rssi_comb : 8,
|
||||
rssi_comb : 8,
|
||||
normalized_pre_rssi_comb : 8,
|
||||
normalized_rssi_comb : 8;
|
||||
uint32_t rssi_comb_ppdu : 8,
|
||||
rssi_db_to_dbm_offset : 8,
|
||||
rssi_for_spatial_reuse : 8,
|
||||
rssi_for_trigger_resp : 8;
|
||||
#else
|
||||
struct receive_pkt_start_info rx_pkt_start_details;
|
||||
uint32_t sw_phy_meta_data : 32;
|
||||
uint32_t reserved_4a : 32;
|
||||
uint32_t reserved_6a : 32;
|
||||
uint32_t reserved_7a : 32;
|
||||
struct receive_rssi_info pre_rssi_info_details;
|
||||
struct receive_rssi_info preamble_rssi_info_details;
|
||||
uint32_t normalized_rssi_comb : 8,
|
||||
normalized_pre_rssi_comb : 8,
|
||||
rssi_comb : 8,
|
||||
pre_rssi_comb : 8;
|
||||
uint32_t rssi_for_trigger_resp : 8,
|
||||
rssi_for_spatial_reuse : 8,
|
||||
rssi_db_to_dbm_offset : 8,
|
||||
rssi_comb_ppdu : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x00000000
|
||||
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3
|
||||
#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x0000000f
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x00000010
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x00000000
|
||||
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5
|
||||
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x000000e0
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x00000000
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x00000000
|
||||
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0xffff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
|
||||
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MSB 8
|
||||
#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MASK 0x00000100
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_3A_LSB 9
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_3A_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_3A_MASK 0xfffffe00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010
|
||||
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x00000014
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x00000018
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000020
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000024
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000028
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000028
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000028
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000028
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000002c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000002c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000002c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000002c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000030
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000034
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000038
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000038
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000038
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000038
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000003c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000003c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000003c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000003c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000040
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000044
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000048
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000048
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000048
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000048
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000004c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000004c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000004c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000004c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000050
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000054
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000058
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000058
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000058
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000058
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000005c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000005c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000005c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000005c
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000060
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000060
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000060
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000060
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000064
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000064
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000064
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000064
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000068
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000068
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000068
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000068
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000006c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000006c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000006c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000006c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000070
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000070
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000070
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000070
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000074
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000074
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000074
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000074
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000078
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000078
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000078
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000078
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000007c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000007c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000007c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000007c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000080
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000080
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000080
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000080
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000084
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000084
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000084
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000084
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000088
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000088
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000088
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000088
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000008c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000008c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000008c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000008c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000090
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000090
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000090
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000090
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000094
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000094
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000094
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000094
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000098
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000098
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000098
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000098
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000009c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000009c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000009c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000009c
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x000000a0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x000000a0
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x000000a0
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x000000a0
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0xff000000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x000000a4
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 0
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 7
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x000000a4
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 8
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 15
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x000000a4
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 16
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 23
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x000000a4
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 24
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 31
|
||||
#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
202
drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h
Normal file
202
drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h
Normal file
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_USER_INFO_H_
|
||||
#define _PHYRX_USER_INFO_H_
|
||||
|
||||
#include "receive_user_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
|
||||
|
||||
struct phyrx_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct receive_user_info receive_user_info_details;
|
||||
#else
|
||||
struct receive_user_info receive_user_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff
|
||||
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31
|
||||
#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
122
drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h
Normal file
122
drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYRX_VHT_SIG_A_H_
|
||||
#define _PHYRX_VHT_SIG_A_H_
|
||||
|
||||
#include "vht_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
|
||||
|
||||
struct phyrx_vht_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
|
||||
#else
|
||||
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#define _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
|
||||
|
||||
struct phytx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t phytx_abort_reason : 8,
|
||||
user_number : 6,
|
||||
reserved : 2;
|
||||
#else
|
||||
uint16_t reserved : 2,
|
||||
user_number : 6,
|
||||
phytx_abort_reason : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000
|
||||
|
||||
#endif
|
||||
241
drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h
Normal file
241
drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYTX_PKT_END_H_
|
||||
#define _PHYTX_PKT_END_H_
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_PKT_END 26
|
||||
|
||||
#define NUM_OF_DWORDS_PHYTX_PKT_END 13
|
||||
|
||||
struct phytx_pkt_end {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t start_of_frame_timestamp_15_0 : 16;
|
||||
uint16_t start_of_frame_timestamp_31_16 : 16;
|
||||
uint16_t end_of_frame_timestamp_15_0 : 16;
|
||||
uint16_t end_of_frame_timestamp_31_16 : 16;
|
||||
uint16_t tx_group_delay : 12,
|
||||
timing_status : 2,
|
||||
phyrx_entered_nap_state : 1,
|
||||
dpdtrain_done : 1;
|
||||
uint16_t transmit_delay : 16;
|
||||
uint16_t tpc_dbg_info_cmn_15_0 : 16;
|
||||
uint16_t tpc_dbg_info_cmn_31_16 : 16;
|
||||
uint16_t tpc_dbg_info_cmn_47_32 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_15_0 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_31_16 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_47_32 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_63_48 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_79_64 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_15_0 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_31_16 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_47_32 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_63_48 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_79_64 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_15_0 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_31_16 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_47_32 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_63_48 : 16;
|
||||
uint16_t beamform_masked_user_bitmap_15_0 : 16;
|
||||
uint16_t beamform_masked_user_bitmap_31_16 : 16;
|
||||
uint16_t beamform_masked_user_bitmap_36_32 : 5,
|
||||
reserved_23 : 11;
|
||||
#else
|
||||
uint16_t start_of_frame_timestamp_15_0 : 16;
|
||||
uint16_t start_of_frame_timestamp_31_16 : 16;
|
||||
uint16_t end_of_frame_timestamp_15_0 : 16;
|
||||
uint16_t end_of_frame_timestamp_31_16 : 16;
|
||||
uint16_t dpdtrain_done : 1,
|
||||
phyrx_entered_nap_state : 1,
|
||||
timing_status : 2,
|
||||
tx_group_delay : 12;
|
||||
uint16_t transmit_delay : 16;
|
||||
uint16_t tpc_dbg_info_cmn_15_0 : 16;
|
||||
uint16_t tpc_dbg_info_cmn_31_16 : 16;
|
||||
uint16_t tpc_dbg_info_cmn_47_32 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_15_0 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_31_16 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_47_32 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_63_48 : 16;
|
||||
uint16_t tpc_dbg_info_chn1_79_64 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_15_0 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_31_16 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_47_32 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_63_48 : 16;
|
||||
uint16_t tpc_dbg_info_chn2_79_64 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_15_0 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_31_16 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_47_32 : 16;
|
||||
uint16_t phytx_tx_end_sw_info_63_48 : 16;
|
||||
uint16_t beamform_masked_user_bitmap_15_0 : 16;
|
||||
uint16_t beamform_masked_user_bitmap_31_16 : 16;
|
||||
uint16_t reserved_23 : 11,
|
||||
beamform_masked_user_bitmap_36_32 : 5;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008
|
||||
#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0
|
||||
#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11
|
||||
#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff
|
||||
|
||||
#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008
|
||||
#define PHYTX_PKT_END_TIMING_STATUS_LSB 12
|
||||
#define PHYTX_PKT_END_TIMING_STATUS_MSB 13
|
||||
#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000
|
||||
|
||||
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008
|
||||
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14
|
||||
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14
|
||||
#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000
|
||||
|
||||
#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008
|
||||
#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15
|
||||
#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15
|
||||
#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000
|
||||
|
||||
#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a
|
||||
#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0
|
||||
#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15
|
||||
#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15
|
||||
#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15
|
||||
#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff
|
||||
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4
|
||||
#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f
|
||||
|
||||
#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032
|
||||
#define PHYTX_PKT_END_RESERVED_23_LSB 5
|
||||
#define PHYTX_PKT_END_RESERVED_23_MSB 15
|
||||
#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
|
||||
#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
|
||||
|
||||
#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
|
||||
|
||||
struct phytx_ppdu_header_info_request {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t request_type : 5,
|
||||
reserved : 11;
|
||||
uint16_t tlv32_padding : 16;
|
||||
#else
|
||||
uint16_t reserved : 11,
|
||||
request_type : 5;
|
||||
uint16_t tlv32_padding : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff
|
||||
|
||||
#endif
|
||||
99
drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h
Normal file
99
drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RECEIVE_PKT_START_INFO_H_
|
||||
#define _RECEIVE_PKT_START_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
|
||||
|
||||
struct receive_pkt_start_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reception_type : 4,
|
||||
rx_chain_mask_type : 1,
|
||||
receive_bandwidth : 3,
|
||||
rx_chain_mask : 8,
|
||||
phy_ppdu_id : 16;
|
||||
uint32_t ppdu_start_timestamp_31_0 : 32;
|
||||
uint32_t ppdu_start_timestamp_63_32 : 32;
|
||||
uint32_t preamble_time_to_rxframe : 8,
|
||||
standalone_sniffer_mode : 1,
|
||||
reserved_3a : 23;
|
||||
#else
|
||||
uint32_t phy_ppdu_id : 16,
|
||||
rx_chain_mask : 8,
|
||||
receive_bandwidth : 3,
|
||||
rx_chain_mask_type : 1,
|
||||
reception_type : 4;
|
||||
uint32_t ppdu_start_timestamp_31_0 : 32;
|
||||
uint32_t ppdu_start_timestamp_63_32 : 32;
|
||||
uint32_t reserved_3a : 23,
|
||||
standalone_sniffer_mode : 1,
|
||||
preamble_time_to_rxframe : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0
|
||||
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3
|
||||
#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000
|
||||
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5
|
||||
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7
|
||||
#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15
|
||||
#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000
|
||||
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16
|
||||
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31
|
||||
#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31
|
||||
#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
|
||||
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0
|
||||
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7
|
||||
#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
|
||||
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8
|
||||
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8
|
||||
#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100
|
||||
|
||||
#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9
|
||||
#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31
|
||||
#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00
|
||||
|
||||
#endif
|
||||
477
drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h
Normal file
477
drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h
Normal file
|
|
@ -0,0 +1,477 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RECEIVE_RSSI_INFO_H_
|
||||
#define _RECEIVE_RSSI_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
|
||||
|
||||
struct receive_rssi_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rssi_pri20_chain0 : 8,
|
||||
rssi_ext20_chain0 : 8,
|
||||
rssi_ext40_low20_chain0 : 8,
|
||||
rssi_ext40_high20_chain0 : 8;
|
||||
uint32_t rssi_ext80_low20_chain0 : 8,
|
||||
rssi_ext80_low_high20_chain0 : 8,
|
||||
rssi_ext80_high_low20_chain0 : 8,
|
||||
rssi_ext80_high20_chain0 : 8;
|
||||
uint32_t rssi_ext160_0_chain0 : 8,
|
||||
rssi_ext160_1_chain0 : 8,
|
||||
rssi_ext160_2_chain0 : 8,
|
||||
rssi_ext160_3_chain0 : 8;
|
||||
uint32_t rssi_ext160_4_chain0 : 8,
|
||||
rssi_ext160_5_chain0 : 8,
|
||||
rssi_ext160_6_chain0 : 8,
|
||||
rssi_ext160_7_chain0 : 8;
|
||||
uint32_t rssi_pri20_chain1 : 8,
|
||||
rssi_ext20_chain1 : 8,
|
||||
rssi_ext40_low20_chain1 : 8,
|
||||
rssi_ext40_high20_chain1 : 8;
|
||||
uint32_t rssi_ext80_low20_chain1 : 8,
|
||||
rssi_ext80_low_high20_chain1 : 8,
|
||||
rssi_ext80_high_low20_chain1 : 8,
|
||||
rssi_ext80_high20_chain1 : 8;
|
||||
uint32_t rssi_ext160_0_chain1 : 8,
|
||||
rssi_ext160_1_chain1 : 8,
|
||||
rssi_ext160_2_chain1 : 8,
|
||||
rssi_ext160_3_chain1 : 8;
|
||||
uint32_t rssi_ext160_4_chain1 : 8,
|
||||
rssi_ext160_5_chain1 : 8,
|
||||
rssi_ext160_6_chain1 : 8,
|
||||
rssi_ext160_7_chain1 : 8;
|
||||
uint32_t rssi_pri20_chain2 : 8,
|
||||
rssi_ext20_chain2 : 8,
|
||||
rssi_ext40_low20_chain2 : 8,
|
||||
rssi_ext40_high20_chain2 : 8;
|
||||
uint32_t rssi_ext80_low20_chain2 : 8,
|
||||
rssi_ext80_low_high20_chain2 : 8,
|
||||
rssi_ext80_high_low20_chain2 : 8,
|
||||
rssi_ext80_high20_chain2 : 8;
|
||||
uint32_t rssi_ext160_0_chain2 : 8,
|
||||
rssi_ext160_1_chain2 : 8,
|
||||
rssi_ext160_2_chain2 : 8,
|
||||
rssi_ext160_3_chain2 : 8;
|
||||
uint32_t rssi_ext160_4_chain2 : 8,
|
||||
rssi_ext160_5_chain2 : 8,
|
||||
rssi_ext160_6_chain2 : 8,
|
||||
rssi_ext160_7_chain2 : 8;
|
||||
uint32_t rssi_pri20_chain3 : 8,
|
||||
rssi_ext20_chain3 : 8,
|
||||
rssi_ext40_low20_chain3 : 8,
|
||||
rssi_ext40_high20_chain3 : 8;
|
||||
uint32_t rssi_ext80_low20_chain3 : 8,
|
||||
rssi_ext80_low_high20_chain3 : 8,
|
||||
rssi_ext80_high_low20_chain3 : 8,
|
||||
rssi_ext80_high20_chain3 : 8;
|
||||
uint32_t rssi_ext160_0_chain3 : 8,
|
||||
rssi_ext160_1_chain3 : 8,
|
||||
rssi_ext160_2_chain3 : 8,
|
||||
rssi_ext160_3_chain3 : 8;
|
||||
uint32_t rssi_ext160_4_chain3 : 8,
|
||||
rssi_ext160_5_chain3 : 8,
|
||||
rssi_ext160_6_chain3 : 8,
|
||||
rssi_ext160_7_chain3 : 8;
|
||||
#else
|
||||
uint32_t rssi_ext40_high20_chain0 : 8,
|
||||
rssi_ext40_low20_chain0 : 8,
|
||||
rssi_ext20_chain0 : 8,
|
||||
rssi_pri20_chain0 : 8;
|
||||
uint32_t rssi_ext80_high20_chain0 : 8,
|
||||
rssi_ext80_high_low20_chain0 : 8,
|
||||
rssi_ext80_low_high20_chain0 : 8,
|
||||
rssi_ext80_low20_chain0 : 8;
|
||||
uint32_t rssi_ext160_3_chain0 : 8,
|
||||
rssi_ext160_2_chain0 : 8,
|
||||
rssi_ext160_1_chain0 : 8,
|
||||
rssi_ext160_0_chain0 : 8;
|
||||
uint32_t rssi_ext160_7_chain0 : 8,
|
||||
rssi_ext160_6_chain0 : 8,
|
||||
rssi_ext160_5_chain0 : 8,
|
||||
rssi_ext160_4_chain0 : 8;
|
||||
uint32_t rssi_ext40_high20_chain1 : 8,
|
||||
rssi_ext40_low20_chain1 : 8,
|
||||
rssi_ext20_chain1 : 8,
|
||||
rssi_pri20_chain1 : 8;
|
||||
uint32_t rssi_ext80_high20_chain1 : 8,
|
||||
rssi_ext80_high_low20_chain1 : 8,
|
||||
rssi_ext80_low_high20_chain1 : 8,
|
||||
rssi_ext80_low20_chain1 : 8;
|
||||
uint32_t rssi_ext160_3_chain1 : 8,
|
||||
rssi_ext160_2_chain1 : 8,
|
||||
rssi_ext160_1_chain1 : 8,
|
||||
rssi_ext160_0_chain1 : 8;
|
||||
uint32_t rssi_ext160_7_chain1 : 8,
|
||||
rssi_ext160_6_chain1 : 8,
|
||||
rssi_ext160_5_chain1 : 8,
|
||||
rssi_ext160_4_chain1 : 8;
|
||||
uint32_t rssi_ext40_high20_chain2 : 8,
|
||||
rssi_ext40_low20_chain2 : 8,
|
||||
rssi_ext20_chain2 : 8,
|
||||
rssi_pri20_chain2 : 8;
|
||||
uint32_t rssi_ext80_high20_chain2 : 8,
|
||||
rssi_ext80_high_low20_chain2 : 8,
|
||||
rssi_ext80_low_high20_chain2 : 8,
|
||||
rssi_ext80_low20_chain2 : 8;
|
||||
uint32_t rssi_ext160_3_chain2 : 8,
|
||||
rssi_ext160_2_chain2 : 8,
|
||||
rssi_ext160_1_chain2 : 8,
|
||||
rssi_ext160_0_chain2 : 8;
|
||||
uint32_t rssi_ext160_7_chain2 : 8,
|
||||
rssi_ext160_6_chain2 : 8,
|
||||
rssi_ext160_5_chain2 : 8,
|
||||
rssi_ext160_4_chain2 : 8;
|
||||
uint32_t rssi_ext40_high20_chain3 : 8,
|
||||
rssi_ext40_low20_chain3 : 8,
|
||||
rssi_ext20_chain3 : 8,
|
||||
rssi_pri20_chain3 : 8;
|
||||
uint32_t rssi_ext80_high20_chain3 : 8,
|
||||
rssi_ext80_high_low20_chain3 : 8,
|
||||
rssi_ext80_low_high20_chain3 : 8,
|
||||
rssi_ext80_low20_chain3 : 8;
|
||||
uint32_t rssi_ext160_3_chain3 : 8,
|
||||
rssi_ext160_2_chain3 : 8,
|
||||
rssi_ext160_1_chain3 : 8,
|
||||
rssi_ext160_0_chain3 : 8;
|
||||
uint32_t rssi_ext160_7_chain3 : 8,
|
||||
rssi_ext160_6_chain3 : 8,
|
||||
rssi_ext160_5_chain3 : 8,
|
||||
rssi_ext160_4_chain3 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
269
drivers/staging/fw-api/hw/peach/v1/receive_user_info.h
Normal file
269
drivers/staging/fw-api/hw/peach/v1/receive_user_info.h
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RECEIVE_USER_INFO_H_
|
||||
#define _RECEIVE_USER_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
|
||||
|
||||
struct receive_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phy_ppdu_id : 16,
|
||||
user_rssi : 8,
|
||||
pkt_type : 4,
|
||||
stbc : 1,
|
||||
reception_type : 3;
|
||||
uint32_t rate_mcs : 4,
|
||||
sgi : 2,
|
||||
__reserved_g_0004 : 1,
|
||||
reserved_1a : 1,
|
||||
mimo_ss_bitmap : 8,
|
||||
receive_bandwidth : 3,
|
||||
reserved_1b : 5,
|
||||
dl_ofdma_user_index : 8;
|
||||
uint32_t dl_ofdma_content_channel : 1,
|
||||
reserved_2a : 7,
|
||||
nss : 3,
|
||||
stream_offset : 3,
|
||||
sta_dcm : 1,
|
||||
ldpc : 1,
|
||||
ru_type_80_0 : 4,
|
||||
ru_type_80_1 : 4,
|
||||
ru_type_80_2 : 4,
|
||||
ru_type_80_3 : 4;
|
||||
uint32_t ru_start_index_80_0 : 6,
|
||||
reserved_3a : 2,
|
||||
ru_start_index_80_1 : 6,
|
||||
reserved_3b : 2,
|
||||
ru_start_index_80_2 : 6,
|
||||
reserved_3c : 2,
|
||||
ru_start_index_80_3 : 6,
|
||||
reserved_3d : 2;
|
||||
uint32_t user_fd_rssi_seg0 : 32;
|
||||
uint32_t user_fd_rssi_seg1 : 32;
|
||||
uint32_t user_fd_rssi_seg2 : 32;
|
||||
uint32_t user_fd_rssi_seg3 : 32;
|
||||
#else
|
||||
uint32_t reception_type : 3,
|
||||
stbc : 1,
|
||||
pkt_type : 4,
|
||||
user_rssi : 8,
|
||||
phy_ppdu_id : 16;
|
||||
uint32_t dl_ofdma_user_index : 8,
|
||||
reserved_1b : 5,
|
||||
receive_bandwidth : 3,
|
||||
mimo_ss_bitmap : 8,
|
||||
reserved_1a : 1,
|
||||
__reserved_g_0004 : 1,
|
||||
sgi : 2,
|
||||
rate_mcs : 4;
|
||||
uint32_t ru_type_80_3 : 4,
|
||||
ru_type_80_2 : 4,
|
||||
ru_type_80_1 : 4,
|
||||
ru_type_80_0 : 4,
|
||||
ldpc : 1,
|
||||
sta_dcm : 1,
|
||||
stream_offset : 3,
|
||||
nss : 3,
|
||||
reserved_2a : 7,
|
||||
dl_ofdma_content_channel : 1;
|
||||
uint32_t reserved_3d : 2,
|
||||
ru_start_index_80_3 : 6,
|
||||
reserved_3c : 2,
|
||||
ru_start_index_80_2 : 6,
|
||||
reserved_3b : 2,
|
||||
ru_start_index_80_1 : 6,
|
||||
reserved_3a : 2,
|
||||
ru_start_index_80_0 : 6;
|
||||
uint32_t user_fd_rssi_seg0 : 32;
|
||||
uint32_t user_fd_rssi_seg1 : 32;
|
||||
uint32_t user_fd_rssi_seg2 : 32;
|
||||
uint32_t user_fd_rssi_seg3 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_STBC_LSB 28
|
||||
#define RECEIVE_USER_INFO_STBC_MSB 28
|
||||
#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
|
||||
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
|
||||
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_MSB 3
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_SGI_LSB 4
|
||||
#define RECEIVE_USER_INFO_SGI_MSB 5
|
||||
#define RECEIVE_USER_INFO_SGI_MASK 0x00000030
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
|
||||
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
|
||||
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe
|
||||
|
||||
#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_NSS_LSB 8
|
||||
#define RECEIVE_USER_INFO_NSS_MSB 10
|
||||
#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
|
||||
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
|
||||
|
||||
#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_STA_DCM_LSB 14
|
||||
#define RECEIVE_USER_INFO_STA_DCM_MSB 14
|
||||
#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
|
||||
|
||||
#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_LDPC_LSB 15
|
||||
#define RECEIVE_USER_INFO_LDPC_MSB 15
|
||||
#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h
Normal file
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h
Normal file
File diff suppressed because it is too large
Load diff
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h
Normal file
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h
Normal file
File diff suppressed because it is too large
Load diff
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h
Normal file
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,715 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
|
||||
#define _RECEIVED_RESPONSE_USER_36_32_H_
|
||||
|
||||
#include "received_response_user_info.h"
|
||||
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
|
||||
|
||||
struct received_response_user_36_32 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct received_response_user_info received_response_details_user32;
|
||||
struct received_response_user_info received_response_details_user33;
|
||||
struct received_response_user_info received_response_details_user34;
|
||||
struct received_response_user_info received_response_details_user35;
|
||||
struct received_response_user_info received_response_details_user36;
|
||||
#else
|
||||
struct received_response_user_info received_response_details_user32;
|
||||
struct received_response_user_info received_response_details_user33;
|
||||
struct received_response_user_info received_response_details_user34;
|
||||
struct received_response_user_info received_response_details_user35;
|
||||
struct received_response_user_info received_response_details_user36;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x00000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x00000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x00000024
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x00000024
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x00000024
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x00000028
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000002c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000002c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x00000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x00000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x00000044
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x00000044
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x00000044
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x00000048
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000004c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000004c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x00000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x00000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x00000064
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x00000064
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x00000064
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x00000068
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000006c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000006c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x00000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x00000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x00000084
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x00000084
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x00000084
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x00000088
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000008c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000008c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h
Normal file
1126
drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h
Normal file
File diff suppressed because it is too large
Load diff
218
drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h
Normal file
218
drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
|
||||
#define _RECEIVED_RESPONSE_USER_INFO_H_
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
|
||||
|
||||
struct received_response_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mpdu_fcs_pass_count : 12,
|
||||
mpdu_fcs_fail_count : 12,
|
||||
qosnull_frame_count : 4,
|
||||
reserved_0a : 3,
|
||||
user_info_valid : 1;
|
||||
uint32_t null_delimiter_count : 22,
|
||||
reserved_1a : 9,
|
||||
ht_control_valid : 1;
|
||||
uint32_t ht_control : 32;
|
||||
uint32_t qos_control_valid : 16,
|
||||
eosp : 16;
|
||||
uint32_t qos_control_15_8_tid_0 : 8,
|
||||
qos_control_15_8_tid_1 : 8,
|
||||
qos_control_15_8_tid_2 : 8,
|
||||
qos_control_15_8_tid_3 : 8;
|
||||
uint32_t qos_control_15_8_tid_4 : 8,
|
||||
qos_control_15_8_tid_5 : 8,
|
||||
qos_control_15_8_tid_6 : 8,
|
||||
qos_control_15_8_tid_7 : 8;
|
||||
uint32_t qos_control_15_8_tid_8 : 8,
|
||||
qos_control_15_8_tid_9 : 8,
|
||||
qos_control_15_8_tid_10 : 8,
|
||||
qos_control_15_8_tid_11 : 8;
|
||||
uint32_t qos_control_15_8_tid_12 : 8,
|
||||
qos_control_15_8_tid_13 : 8,
|
||||
qos_control_15_8_tid_14 : 8,
|
||||
qos_control_15_8_tid_15 : 8;
|
||||
#else
|
||||
uint32_t user_info_valid : 1,
|
||||
reserved_0a : 3,
|
||||
qosnull_frame_count : 4,
|
||||
mpdu_fcs_fail_count : 12,
|
||||
mpdu_fcs_pass_count : 12;
|
||||
uint32_t ht_control_valid : 1,
|
||||
reserved_1a : 9,
|
||||
null_delimiter_count : 22;
|
||||
uint32_t ht_control : 32;
|
||||
uint32_t eosp : 16,
|
||||
qos_control_valid : 16;
|
||||
uint32_t qos_control_15_8_tid_3 : 8,
|
||||
qos_control_15_8_tid_2 : 8,
|
||||
qos_control_15_8_tid_1 : 8,
|
||||
qos_control_15_8_tid_0 : 8;
|
||||
uint32_t qos_control_15_8_tid_7 : 8,
|
||||
qos_control_15_8_tid_6 : 8,
|
||||
qos_control_15_8_tid_5 : 8,
|
||||
qos_control_15_8_tid_4 : 8;
|
||||
uint32_t qos_control_15_8_tid_11 : 8,
|
||||
qos_control_15_8_tid_10 : 8,
|
||||
qos_control_15_8_tid_9 : 8,
|
||||
qos_control_15_8_tid_8 : 8;
|
||||
uint32_t qos_control_15_8_tid_15 : 8,
|
||||
qos_control_15_8_tid_14 : 8,
|
||||
qos_control_15_8_tid_13 : 8,
|
||||
qos_control_15_8_tid_12 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
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