mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits) [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports [ARM] 4140/1: AACI stability add ac97 timeout and retries [ARM] 4139/1: AACI record support [ARM] 4138/1: AACI: multiple channel support for IRQ handling [ARM] 4211/1: Provide a defconfig for ns9xxx [ARM] 4210/1: base for new machine type "NetSilicon NS9360" [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM [ARM] 4221/1: S3C2443: DMA support [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev [ARM] 4219/1: S3C2443: DMA source definitions [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443 [ARM] 4217/1: S3C24XX: remove the dma channel show at startup [ARM] 4090/2: avoid clash between PXA and SA1111 defines [ARM] 4216/1: add .gitignore entries for ARM specific files [ARM] 4214/2: S3C2410: Add Armzone QT2410 [ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos [ARM] 4137/1: Add kexec support [ARM] 4201/1: SMP barriers pair needed for the secondary boot process ... Fix up conflict due to typedef removal in sound/arm/aaci.h
This commit is contained in:
Linus Torvalds
commit
59b8175c77
320 changed files with 16182 additions and 5749 deletions
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@ -83,7 +83,7 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
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* Every time unit enable is asserted, GPOD needs to be cleared
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* on IOP3XX to avoid data corruption on the bus.
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*/
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#ifdef CONFIG_PLAT_IOP
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#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
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if (iop3xx_adap->id == 0) {
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gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW);
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gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW);
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@ -34,6 +34,7 @@
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/arch/i2c.h>
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#include <asm/arch/pxa-regs.h>
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@ -54,8 +55,21 @@ struct pxa_i2c {
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unsigned int irqlogidx;
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u32 isrlog[32];
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u32 icrlog[32];
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void __iomem *reg_base;
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unsigned long iobase;
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unsigned long iosize;
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int irq;
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};
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#define _IBMR(i2c) ((i2c)->reg_base + 0)
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#define _IDBR(i2c) ((i2c)->reg_base + 8)
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#define _ICR(i2c) ((i2c)->reg_base + 0x10)
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#define _ISR(i2c) ((i2c)->reg_base + 0x18)
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#define _ISAR(i2c) ((i2c)->reg_base + 0x20)
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/*
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* I2C Slave mode address
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*/
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@ -130,7 +144,8 @@ static unsigned int i2c_debug = DEBUG;
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static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
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{
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dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
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dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
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readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
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}
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#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
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@ -153,7 +168,7 @@ static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
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printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
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i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
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printk("i2c: ICR: %08x ISR: %08x\n"
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"i2c: log: ", ICR, ISR);
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"i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
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for (i = 0; i < i2c->irqlogidx; i++)
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printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
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printk("\n");
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@ -161,7 +176,7 @@ static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
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static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
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{
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return !(ICR & ICR_SCLE);
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return !(readl(_ICR(i2c)) & ICR_SCLE);
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}
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static void i2c_pxa_abort(struct pxa_i2c *i2c)
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@ -173,28 +188,29 @@ static void i2c_pxa_abort(struct pxa_i2c *i2c)
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return;
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}
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while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
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unsigned long icr = ICR;
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while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
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unsigned long icr = readl(_ICR(i2c));
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icr &= ~ICR_START;
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icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
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ICR = icr;
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writel(icr, _ICR(i2c));
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show_state(i2c);
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msleep(1);
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}
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ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
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writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
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_ICR(i2c));
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}
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static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
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{
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int timeout = DEF_TIMEOUT;
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while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
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if ((ISR & ISR_SAD) != 0)
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while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
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if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
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timeout += 4;
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msleep(2);
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@ -214,9 +230,9 @@ static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
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while (time_before(jiffies, timeout)) {
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if (i2c_debug > 1)
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dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
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__func__, (long)jiffies, ISR, ICR, IBMR);
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__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
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if (ISR & ISR_SAD) {
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if (readl(_ISR(i2c)) & ISR_SAD) {
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if (i2c_debug > 0)
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dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
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goto out;
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@ -226,7 +242,7 @@ static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
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* quick check of the i2c lines themselves to ensure they've
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* gone high...
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*/
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if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
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if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
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if (i2c_debug > 0)
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dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
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return 1;
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@ -246,7 +262,7 @@ static int i2c_pxa_set_master(struct pxa_i2c *i2c)
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if (i2c_debug)
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dev_dbg(&i2c->adap.dev, "setting to bus master\n");
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if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
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if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
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dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
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if (!i2c_pxa_wait_master(i2c)) {
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dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
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@ -254,7 +270,7 @@ static int i2c_pxa_set_master(struct pxa_i2c *i2c)
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}
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}
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ICR |= ICR_SCLE;
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writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
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return 0;
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}
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@ -270,11 +286,11 @@ static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
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while (time_before(jiffies, timeout)) {
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if (i2c_debug > 1)
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dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
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__func__, (long)jiffies, ISR, ICR, IBMR);
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__func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
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if ((ISR & (ISR_UB|ISR_IBB)) == 0 ||
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(ISR & ISR_SAD) != 0 ||
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(ICR & ICR_SCLE) == 0) {
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if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
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(readl(_ISR(i2c)) & ISR_SAD) != 0 ||
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(readl(_ICR(i2c)) & ICR_SCLE) == 0) {
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if (i2c_debug > 1)
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dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
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return 1;
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@ -302,9 +318,9 @@ static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
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/* we need to wait for the stop condition to end */
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/* if we where in stop, then clear... */
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if (ICR & ICR_STOP) {
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if (readl(_ICR(i2c)) & ICR_STOP) {
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udelay(100);
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ICR &= ~ICR_STOP;
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writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
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}
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if (!i2c_pxa_wait_slave(i2c)) {
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@ -314,12 +330,12 @@ static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
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}
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}
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ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
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ICR &= ~ICR_SCLE;
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writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
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writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
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if (i2c_debug) {
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dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
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decode_ICR(ICR);
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dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
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decode_ICR(readl(_ICR(i2c)));
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}
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}
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#else
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@ -334,24 +350,24 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
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i2c_pxa_abort(i2c);
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/* reset according to 9.8 */
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ICR = ICR_UR;
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ISR = I2C_ISR_INIT;
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ICR &= ~ICR_UR;
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writel(ICR_UR, _ICR(i2c));
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writel(I2C_ISR_INIT, _ISR(i2c));
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writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
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ISAR = i2c->slave_addr;
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writel(i2c->slave_addr, _ISAR(i2c));
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/* set control register values */
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ICR = I2C_ICR_INIT;
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writel(I2C_ICR_INIT, _ICR(i2c));
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#ifdef CONFIG_I2C_PXA_SLAVE
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dev_info(&i2c->adap.dev, "Enabling slave mode\n");
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ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
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writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
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#endif
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i2c_pxa_set_slave(i2c, 0);
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/* enable unit */
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ICR |= ICR_IUE;
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writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
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udelay(100);
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}
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@ -371,19 +387,19 @@ static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
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if (i2c->slave != NULL)
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ret = i2c->slave->read(i2c->slave->data);
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IDBR = ret;
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ICR |= ICR_TB; /* allow next byte */
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writel(ret, _IDBR(i2c));
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writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
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}
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}
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static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
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{
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unsigned int byte = IDBR;
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unsigned int byte = readl(_IDBR(i2c));
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if (i2c->slave != NULL)
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i2c->slave->write(i2c->slave->data, byte);
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ICR |= ICR_TB;
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writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
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}
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static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
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@ -403,13 +419,13 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
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* start condition... if this happens, we'd better back off
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* and stop holding the poor thing up
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*/
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ICR &= ~(ICR_START|ICR_STOP);
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ICR |= ICR_TB;
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writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
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writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
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timeout = 0x10000;
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while (1) {
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if ((IBMR & 2) == 2)
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if ((readl(_IBMR(i2c)) & 2) == 2)
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break;
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timeout--;
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@ -420,7 +436,7 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
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}
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}
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ICR &= ~ICR_SCLE;
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writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
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}
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static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
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@ -447,14 +463,14 @@ static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
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if (isr & ISR_BED) {
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/* what should we do here? */
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} else {
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IDBR = 0;
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ICR |= ICR_TB;
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writel(0, _IDBR(i2c));
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writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
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}
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}
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|
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static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
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{
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ICR |= ICR_TB | ICR_ACKNAK;
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writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
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}
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|
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static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
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|
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@ -466,13 +482,13 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
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* start condition... if this happens, we'd better back off
|
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* and stop holding the poor thing up
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*/
|
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ICR &= ~(ICR_START|ICR_STOP);
|
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ICR |= ICR_TB | ICR_ACKNAK;
|
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writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
|
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writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
|
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|
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timeout = 0x10000;
|
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|
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while (1) {
|
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if ((IBMR & 2) == 2)
|
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if ((readl(_IBMR(i2c)) & 2) == 2)
|
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break;
|
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|
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timeout--;
|
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|
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@ -483,7 +499,7 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
|
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}
|
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}
|
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|
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ICR &= ~ICR_SCLE;
|
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writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
|
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}
|
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|
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static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
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|
|
@ -514,13 +530,13 @@ static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
|
|||
/*
|
||||
* Step 1: target slave address into IDBR
|
||||
*/
|
||||
IDBR = i2c_pxa_addr_byte(i2c->msg);
|
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writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
|
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|
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/*
|
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* Step 2: initiate the write.
|
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*/
|
||||
icr = ICR & ~(ICR_STOP | ICR_ALDIE);
|
||||
ICR = icr | ICR_START | ICR_TB;
|
||||
icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
|
||||
writel(icr | ICR_START | ICR_TB, _ICR(i2c));
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -594,7 +610,7 @@ static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
|
|||
|
||||
static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
|
||||
{
|
||||
u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
|
||||
u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
|
||||
|
||||
again:
|
||||
/*
|
||||
|
|
@ -645,7 +661,7 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
|
|||
/*
|
||||
* Write mode. Write the next data byte.
|
||||
*/
|
||||
IDBR = i2c->msg->buf[i2c->msg_ptr++];
|
||||
writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
|
||||
|
||||
icr |= ICR_ALDIE | ICR_TB;
|
||||
|
||||
|
|
@ -675,7 +691,7 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
|
|||
/*
|
||||
* Write the next address.
|
||||
*/
|
||||
IDBR = i2c_pxa_addr_byte(i2c->msg);
|
||||
writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
|
||||
|
||||
/*
|
||||
* And trigger a repeated start, and send the byte.
|
||||
|
|
@ -696,18 +712,18 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
|
|||
|
||||
i2c->icrlog[i2c->irqlogidx-1] = icr;
|
||||
|
||||
ICR = icr;
|
||||
writel(icr, _ICR(i2c));
|
||||
show_state(i2c);
|
||||
}
|
||||
|
||||
static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
|
||||
{
|
||||
u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
|
||||
u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
|
||||
|
||||
/*
|
||||
* Read the byte.
|
||||
*/
|
||||
i2c->msg->buf[i2c->msg_ptr++] = IDBR;
|
||||
i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
|
||||
|
||||
if (i2c->msg_ptr < i2c->msg->len) {
|
||||
/*
|
||||
|
|
@ -724,17 +740,17 @@ static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
|
|||
|
||||
i2c->icrlog[i2c->irqlogidx-1] = icr;
|
||||
|
||||
ICR = icr;
|
||||
writel(icr, _ICR(i2c));
|
||||
}
|
||||
|
||||
static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
|
||||
{
|
||||
struct pxa_i2c *i2c = dev_id;
|
||||
u32 isr = ISR;
|
||||
u32 isr = readl(_ISR(i2c));
|
||||
|
||||
if (i2c_debug > 2 && 0) {
|
||||
dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
|
||||
__func__, isr, ICR, IBMR);
|
||||
__func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
|
||||
decode_ISR(isr);
|
||||
}
|
||||
|
||||
|
|
@ -746,7 +762,7 @@ static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
|
|||
/*
|
||||
* Always clear all pending IRQs.
|
||||
*/
|
||||
ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
|
||||
writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
|
||||
|
||||
if (isr & ISR_SAD)
|
||||
i2c_pxa_slave_start(i2c, isr);
|
||||
|
|
@ -779,7 +795,7 @@ static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num
|
|||
/* If the I2C controller is disabled we need to reset it (probably due
|
||||
to a suspend/resume destroying state). We do this here as we can then
|
||||
avoid worrying about resuming the controller before its users. */
|
||||
if (!(ICR & ICR_IUE))
|
||||
if (!(readl(_ICR(i2c)) & ICR_IUE))
|
||||
i2c_pxa_reset(i2c);
|
||||
|
||||
for (i = adap->retries; i >= 0; i--) {
|
||||
|
|
@ -810,28 +826,53 @@ static const struct i2c_algorithm i2c_pxa_algorithm = {
|
|||
|
||||
static struct pxa_i2c i2c_pxa = {
|
||||
.lock = SPIN_LOCK_UNLOCKED,
|
||||
.wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
|
||||
.adap = {
|
||||
.owner = THIS_MODULE,
|
||||
.algo = &i2c_pxa_algorithm,
|
||||
.name = "pxa2xx-i2c",
|
||||
.name = "pxa2xx-i2c.0",
|
||||
.retries = 5,
|
||||
},
|
||||
};
|
||||
|
||||
#define res_len(r) ((r)->end - (r)->start + 1)
|
||||
static int i2c_pxa_probe(struct platform_device *dev)
|
||||
{
|
||||
struct pxa_i2c *i2c = &i2c_pxa;
|
||||
struct resource *res;
|
||||
#ifdef CONFIG_I2C_PXA_SLAVE
|
||||
struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
|
||||
#endif
|
||||
int ret;
|
||||
int irq;
|
||||
|
||||
#ifdef CONFIG_PXA27x
|
||||
pxa_gpio_mode(GPIO117_I2CSCL_MD);
|
||||
pxa_gpio_mode(GPIO118_I2CSDA_MD);
|
||||
udelay(100);
|
||||
#endif
|
||||
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
||||
irq = platform_get_irq(dev, 0);
|
||||
if (res == NULL || irq < 0)
|
||||
return -ENODEV;
|
||||
|
||||
if (!request_mem_region(res->start, res_len(res), res->name))
|
||||
return -ENOMEM;
|
||||
|
||||
i2c = kmalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
|
||||
if (!i2c) {
|
||||
ret = -ENOMEM;
|
||||
goto emalloc;
|
||||
}
|
||||
|
||||
memcpy(i2c, &i2c_pxa, sizeof(struct pxa_i2c));
|
||||
init_waitqueue_head(&i2c->wait);
|
||||
i2c->adap.name[strlen(i2c->adap.name) - 1] = '0' + dev->id % 10;
|
||||
|
||||
i2c->reg_base = ioremap(res->start, res_len(res));
|
||||
if (!i2c->reg_base) {
|
||||
ret = -EIO;
|
||||
goto eremap;
|
||||
}
|
||||
|
||||
i2c->iobase = res->start;
|
||||
i2c->iosize = res_len(res);
|
||||
|
||||
i2c->irq = irq;
|
||||
|
||||
i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
|
||||
|
||||
|
|
@ -842,11 +883,28 @@ static int i2c_pxa_probe(struct platform_device *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
pxa_set_cken(CKEN14_I2C, 1);
|
||||
ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED,
|
||||
"pxa2xx-i2c", i2c);
|
||||
switch (dev->id) {
|
||||
case 0:
|
||||
#ifdef CONFIG_PXA27x
|
||||
pxa_gpio_mode(GPIO117_I2CSCL_MD);
|
||||
pxa_gpio_mode(GPIO118_I2CSDA_MD);
|
||||
#endif
|
||||
pxa_set_cken(CKEN14_I2C, 1);
|
||||
break;
|
||||
#ifdef CONFIG_PXA27x
|
||||
case 1:
|
||||
local_irq_disable();
|
||||
PCFR |= PCFR_PI2CEN;
|
||||
local_irq_enable();
|
||||
pxa_set_cken(CKEN15_PWRI2C, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
|
||||
i2c->adap.name, i2c);
|
||||
if (ret)
|
||||
goto out;
|
||||
goto ereqirq;
|
||||
|
||||
|
||||
i2c_pxa_reset(i2c);
|
||||
|
||||
|
|
@ -856,7 +914,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
|
|||
ret = i2c_add_adapter(&i2c->adap);
|
||||
if (ret < 0) {
|
||||
printk(KERN_INFO "I2C: Failed to add bus\n");
|
||||
goto err_irq;
|
||||
goto eadapt;
|
||||
}
|
||||
|
||||
platform_set_drvdata(dev, i2c);
|
||||
|
|
@ -870,9 +928,25 @@ static int i2c_pxa_probe(struct platform_device *dev)
|
|||
#endif
|
||||
return 0;
|
||||
|
||||
err_irq:
|
||||
free_irq(IRQ_I2C, i2c);
|
||||
out:
|
||||
eadapt:
|
||||
free_irq(irq, i2c);
|
||||
ereqirq:
|
||||
switch (dev->id) {
|
||||
case 0:
|
||||
pxa_set_cken(CKEN14_I2C, 0);
|
||||
break;
|
||||
#ifdef CONFIG_PXA27x
|
||||
case 1:
|
||||
pxa_set_cken(CKEN15_PWRI2C, 0);
|
||||
local_irq_disable();
|
||||
PCFR &= ~PCFR_PI2CEN;
|
||||
local_irq_enable();
|
||||
#endif
|
||||
}
|
||||
eremap:
|
||||
kfree(i2c);
|
||||
emalloc:
|
||||
release_mem_region(res->start, res_len(res));
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -883,8 +957,21 @@ static int i2c_pxa_remove(struct platform_device *dev)
|
|||
platform_set_drvdata(dev, NULL);
|
||||
|
||||
i2c_del_adapter(&i2c->adap);
|
||||
free_irq(IRQ_I2C, i2c);
|
||||
pxa_set_cken(CKEN14_I2C, 0);
|
||||
free_irq(i2c->irq, i2c);
|
||||
switch (dev->id) {
|
||||
case 0:
|
||||
pxa_set_cken(CKEN14_I2C, 0);
|
||||
break;
|
||||
#ifdef CONFIG_PXA27x
|
||||
case 1:
|
||||
pxa_set_cken(CKEN15_PWRI2C, 0);
|
||||
local_irq_disable();
|
||||
PCFR &= ~PCFR_PI2CEN;
|
||||
local_irq_enable();
|
||||
#endif
|
||||
}
|
||||
release_mem_region(i2c->iobase, i2c->iosize);
|
||||
kfree(i2c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/atmel_pdc.h>
|
||||
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/protocol.h>
|
||||
|
|
@ -75,7 +76,6 @@
|
|||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/at91_mci.h>
|
||||
#include <asm/arch/at91_pdc.h>
|
||||
|
||||
#define DRIVER_NAME "at91_mci"
|
||||
|
||||
|
|
@ -211,13 +211,13 @@ static void at91mci_pre_dma_read(struct at91mci_host *host)
|
|||
|
||||
/* Check to see if this needs filling */
|
||||
if (i == 0) {
|
||||
if (at91_mci_read(host, AT91_PDC_RCR) != 0) {
|
||||
if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) {
|
||||
pr_debug("Transfer active in current\n");
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else {
|
||||
if (at91_mci_read(host, AT91_PDC_RNCR) != 0) {
|
||||
if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) {
|
||||
pr_debug("Transfer active in next\n");
|
||||
continue;
|
||||
}
|
||||
|
|
@ -234,12 +234,12 @@ static void at91mci_pre_dma_read(struct at91mci_host *host)
|
|||
pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
|
||||
|
||||
if (i == 0) {
|
||||
at91_mci_write(host, AT91_PDC_RPR, sg->dma_address);
|
||||
at91_mci_write(host, AT91_PDC_RCR, sg->length / 4);
|
||||
at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address);
|
||||
at91_mci_write(host, ATMEL_PDC_RCR, sg->length / 4);
|
||||
}
|
||||
else {
|
||||
at91_mci_write(host, AT91_PDC_RNPR, sg->dma_address);
|
||||
at91_mci_write(host, AT91_PDC_RNCR, sg->length / 4);
|
||||
at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address);
|
||||
at91_mci_write(host, ATMEL_PDC_RNCR, sg->length / 4);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -303,7 +303,7 @@ static void at91mci_post_dma_read(struct at91mci_host *host)
|
|||
at91mci_pre_dma_read(host);
|
||||
else {
|
||||
at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
|
||||
at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
|
||||
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
||||
}
|
||||
|
||||
pr_debug("post dma read done\n");
|
||||
|
|
@ -320,7 +320,7 @@ static void at91_mci_handle_transmitted(struct at91mci_host *host)
|
|||
pr_debug("Handling the transmit\n");
|
||||
|
||||
/* Disable the transfer */
|
||||
at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
|
||||
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
||||
|
||||
/* Now wait for cmd ready */
|
||||
at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
|
||||
|
|
@ -431,15 +431,15 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_
|
|||
cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
|
||||
|
||||
if (!data) {
|
||||
at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
|
||||
at91_mci_write(host, AT91_PDC_RPR, 0);
|
||||
at91_mci_write(host, AT91_PDC_RCR, 0);
|
||||
at91_mci_write(host, AT91_PDC_RNPR, 0);
|
||||
at91_mci_write(host, AT91_PDC_RNCR, 0);
|
||||
at91_mci_write(host, AT91_PDC_TPR, 0);
|
||||
at91_mci_write(host, AT91_PDC_TCR, 0);
|
||||
at91_mci_write(host, AT91_PDC_TNPR, 0);
|
||||
at91_mci_write(host, AT91_PDC_TNCR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
|
||||
at91_mci_write(host, ATMEL_PDC_RPR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_RCR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_RNPR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_RNCR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_TPR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_TCR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_TNPR, 0);
|
||||
at91_mci_write(host, ATMEL_PDC_TNCR, 0);
|
||||
|
||||
at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
|
||||
at91_mci_write(host, AT91_MCI_CMDR, cmdr);
|
||||
|
|
@ -452,7 +452,7 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_
|
|||
/*
|
||||
* Disable the PDC controller
|
||||
*/
|
||||
at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
|
||||
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
||||
|
||||
if (cmdr & AT91_MCI_TRCMD_START) {
|
||||
data->bytes_xfered = 0;
|
||||
|
|
@ -481,8 +481,8 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_
|
|||
|
||||
pr_debug("Transmitting %d bytes\n", host->total_length);
|
||||
|
||||
at91_mci_write(host, AT91_PDC_TPR, host->physical_address);
|
||||
at91_mci_write(host, AT91_PDC_TCR, host->total_length / 4);
|
||||
at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
|
||||
at91_mci_write(host, ATMEL_PDC_TCR, host->total_length / 4);
|
||||
ier = AT91_MCI_TXBUFE;
|
||||
}
|
||||
}
|
||||
|
|
@ -497,9 +497,9 @@ static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_
|
|||
|
||||
if (cmdr & AT91_MCI_TRCMD_START) {
|
||||
if (cmdr & AT91_MCI_TRDIR)
|
||||
at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTEN);
|
||||
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
|
||||
else
|
||||
at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTEN);
|
||||
at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
|
||||
}
|
||||
return ier;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -262,7 +262,8 @@ config SERIAL_AMBA_PL010
|
|||
select SERIAL_CORE
|
||||
help
|
||||
This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
|
||||
an Integrator/AP or Integrator/PP2 platform, say Y or M here.
|
||||
an Integrator/AP or Integrator/PP2 platform, or if you have a
|
||||
Cirrus Logic EP93xx CPU, say Y or M here.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
|
|
|
|||
|
|
@ -33,12 +33,13 @@
|
|||
#include <linux/sysrq.h>
|
||||
#include <linux/tty_flip.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/atmel_pdc.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/mach/serial_at91.h>
|
||||
#include <asm/arch/board.h>
|
||||
#include <asm/arch/at91_pdc.h>
|
||||
|
||||
#ifdef CONFIG_ARM
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
|
|
|
|||
|
|
@ -154,7 +154,7 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
|
|||
{
|
||||
struct circ_buf *xmit = &sport->port.info->xmit;
|
||||
|
||||
do {
|
||||
while (!(UTS((u32)sport->port.membase) & UTS_TXFULL)) {
|
||||
/* send xmit->buf[xmit->tail]
|
||||
* out the port here */
|
||||
URTX0((u32)sport->port.membase) = xmit->buf[xmit->tail];
|
||||
|
|
@ -163,7 +163,7 @@ static inline void imx_transmit_buffer(struct imx_port *sport)
|
|||
sport->port.icount.tx++;
|
||||
if (uart_circ_empty(xmit))
|
||||
break;
|
||||
} while (!(UTS((u32)sport->port.membase) & UTS_TXFULL));
|
||||
}
|
||||
|
||||
if (uart_circ_empty(xmit))
|
||||
imx_stop_tx(&sport->port);
|
||||
|
|
@ -178,8 +178,7 @@ static void imx_start_tx(struct uart_port *port)
|
|||
|
||||
UCR1((u32)sport->port.membase) |= UCR1_TXMPTYEN;
|
||||
|
||||
if(UTS((u32)sport->port.membase) & UTS_TXEMPTY)
|
||||
imx_transmit_buffer(sport);
|
||||
imx_transmit_buffer(sport);
|
||||
}
|
||||
|
||||
static irqreturn_t imx_rtsint(int irq, void *dev_id)
|
||||
|
|
@ -404,7 +403,8 @@ static int imx_startup(struct uart_port *port)
|
|||
if (retval) goto error_out2;
|
||||
|
||||
retval = request_irq(sport->rtsirq, imx_rtsint,
|
||||
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
||||
(sport->rtsirq < IMX_IRQS) ? 0 :
|
||||
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
||||
DRIVER_NAME, sport);
|
||||
if (retval) goto error_out3;
|
||||
|
||||
|
|
@ -678,7 +678,7 @@ static struct imx_port imx_ports[] = {
|
|||
.mapbase = IMX_UART1_BASE, /* FIXME */
|
||||
.irq = UART1_MINT_RX,
|
||||
.uartclk = 16000000,
|
||||
.fifosize = 8,
|
||||
.fifosize = 32,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.ops = &imx_pops,
|
||||
.line = 0,
|
||||
|
|
@ -694,7 +694,7 @@ static struct imx_port imx_ports[] = {
|
|||
.mapbase = IMX_UART2_BASE, /* FIXME */
|
||||
.irq = UART2_MINT_RX,
|
||||
.uartclk = 16000000,
|
||||
.fifosize = 8,
|
||||
.fifosize = 32,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.ops = &imx_pops,
|
||||
.line = 1,
|
||||
|
|
|
|||
|
|
@ -912,7 +912,7 @@ static void pullup(struct at91_udc *udc, int is_on)
|
|||
at91_udp_write(udc, AT91_UDP_TXVC, 0);
|
||||
if (cpu_is_at91rm9200())
|
||||
at91_set_gpio_value(udc->board.pullup_pin, 1);
|
||||
else if (cpu_is_at91sam9260()) {
|
||||
else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
|
||||
u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC);
|
||||
|
||||
txvc |= AT91_UDP_TXVC_PUON;
|
||||
|
|
@ -929,7 +929,7 @@ static void pullup(struct at91_udc *udc, int is_on)
|
|||
at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS);
|
||||
if (cpu_is_at91rm9200())
|
||||
at91_set_gpio_value(udc->board.pullup_pin, 0);
|
||||
else if (cpu_is_at91sam9260()) {
|
||||
else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
|
||||
u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC);
|
||||
|
||||
txvc &= ~AT91_UDP_TXVC_PUON;
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ static int is_vbus_present(void)
|
|||
struct pxa2xx_udc_mach_info *mach = the_controller->mach;
|
||||
|
||||
if (mach->gpio_vbus)
|
||||
return pxa_gpio_get(mach->gpio_vbus);
|
||||
return udc_gpio_get(mach->gpio_vbus);
|
||||
if (mach->udc_is_connected)
|
||||
return mach->udc_is_connected();
|
||||
return 1;
|
||||
|
|
@ -167,7 +167,7 @@ static void pullup_off(void)
|
|||
struct pxa2xx_udc_mach_info *mach = the_controller->mach;
|
||||
|
||||
if (mach->gpio_pullup)
|
||||
pxa_gpio_set(mach->gpio_pullup, 0);
|
||||
udc_gpio_set(mach->gpio_pullup, 0);
|
||||
else if (mach->udc_command)
|
||||
mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
|
||||
}
|
||||
|
|
@ -177,7 +177,7 @@ static void pullup_on(void)
|
|||
struct pxa2xx_udc_mach_info *mach = the_controller->mach;
|
||||
|
||||
if (mach->gpio_pullup)
|
||||
pxa_gpio_set(mach->gpio_pullup, 1);
|
||||
udc_gpio_set(mach->gpio_pullup, 1);
|
||||
else if (mach->udc_command)
|
||||
mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
|
||||
}
|
||||
|
|
@ -1755,7 +1755,7 @@ lubbock_vbus_irq(int irq, void *_dev)
|
|||
static irqreturn_t udc_vbus_irq(int irq, void *_dev)
|
||||
{
|
||||
struct pxa2xx_udc *dev = _dev;
|
||||
int vbus = pxa_gpio_get(dev->mach->gpio_vbus);
|
||||
int vbus = udc_gpio_get(dev->mach->gpio_vbus);
|
||||
|
||||
pxa2xx_udc_vbus_session(&dev->gadget, vbus);
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -2545,15 +2545,13 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
|
|||
dev->dev = &pdev->dev;
|
||||
dev->mach = pdev->dev.platform_data;
|
||||
if (dev->mach->gpio_vbus) {
|
||||
vbus_irq = IRQ_GPIO(dev->mach->gpio_vbus & GPIO_MD_MASK_NR);
|
||||
pxa_gpio_mode((dev->mach->gpio_vbus & GPIO_MD_MASK_NR)
|
||||
| GPIO_IN);
|
||||
udc_gpio_init_vbus(dev->mach->gpio_vbus);
|
||||
vbus_irq = udc_gpio_to_irq(dev->mach->gpio_vbus);
|
||||
set_irq_type(vbus_irq, IRQT_BOTHEDGE);
|
||||
} else
|
||||
vbus_irq = 0;
|
||||
if (dev->mach->gpio_pullup)
|
||||
pxa_gpio_mode((dev->mach->gpio_pullup & GPIO_MD_MASK_NR)
|
||||
| GPIO_OUT | GPIO_DFLT_LOW);
|
||||
udc_gpio_init_pullup(dev->mach->gpio_pullup);
|
||||
|
||||
init_timer(&dev->timer);
|
||||
dev->timer.function = udc_watchdog;
|
||||
|
|
|
|||
|
|
@ -177,21 +177,6 @@ struct pxa2xx_udc {
|
|||
|
||||
static struct pxa2xx_udc *the_controller;
|
||||
|
||||
static inline int pxa_gpio_get(unsigned gpio)
|
||||
{
|
||||
return (GPLR(gpio) & GPIO_bit(gpio)) != 0;
|
||||
}
|
||||
|
||||
static inline void pxa_gpio_set(unsigned gpio, int is_on)
|
||||
{
|
||||
int mask = GPIO_bit(gpio);
|
||||
|
||||
if (is_on)
|
||||
GPSR(gpio) = mask;
|
||||
else
|
||||
GPCR(gpio) = mask;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue