From 5a50bc191ee2e038cc9035ca241c06a4092d31c1 Mon Sep 17 00:00:00 2001 From: Jun Li Date: Mon, 19 Oct 2020 14:29:31 +0800 Subject: [PATCH] mmc: sdhci-msm: Update to enhanced SDCC5 DLL power up sequence Update the DLL power up sequence according to the latest enhanced SDCC DLL HSR document and SDCDC initialization sequence in HPG. Final sequence: Step 1 - Set PWRSAVE bit in MCI_CLK to '0' during reset Step 2 - Disable CK_OUT Setp 3 - Set CORE_DLL_CLOCK_DISABLE to '1' Step 4 - Set RST & PDN to '1' Step 5 - Set DLL_CONFIG_3 Step 6 - Set SDC4_USER_CTRL Step 7 - Set SDC4_TEST_CTRL(SW can Skip this step) Step 8 - Set DDR_CONFIG Step 9 - Set DLL_CONFIG_2 Step 10 - Set DLL_CONFIG Step 11 - Wait for 52 us Step 12 - Set RST & PDN to '0' Step 13 - Set RST to '1' Step 14 - Set RST to '0' Step 15 - Set CORE_DLL_CLOCK_DISABLE to '0' Step 16 - Wait for 8000 input clock cycles Step 17 - Enable CK_OUT Step 18 - Check for Lock Step 19 - If PWRSAVE is needed, set PWRSAVE to '1'. Change-Id: I889937a1728b3ce039a802972f9668969fe96505 Signed-off-by: Jun Li Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 97642d002ef5..203a0f3d0f3a 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -119,6 +119,7 @@ #define FINE_TUNE_MODE_EN BIT(27) #define BIAS_OK_SIGNAL BIT(29) #define DLL_CONFIG_3_POR_VAL 0x10 +#define DLL_CONFIG_POR_VAL 0x6007642C #define INVALID_TUNING_PHASE -1 @@ -857,7 +858,7 @@ static int msm_init_cm_dll(struct sdhci_host *host, else ddr_cfg_offset = msm_offset->core_ddr_config_old; - if (msm_host->dll_hsr->ddr_config) + if (msm_host->dll_hsr && msm_host->dll_hsr->ddr_config) writel_relaxed(msm_host->dll_hsr->ddr_config, host->ioaddr + ddr_cfg_offset); else @@ -896,16 +897,14 @@ static int msm_init_cm_dll(struct sdhci_host *host, udelay(5); } - /* - * Step 10 - Update the lower two bytes of DLL_CONFIG only with - * HSR values. Since these are the static settings. - */ - if (msm_host->dll_hsr) { - writel_relaxed((readl_relaxed(host->ioaddr + - msm_offset->core_dll_config) | - (msm_host->dll_hsr->dll_config & 0xffff)), - host->ioaddr + msm_offset->core_dll_config); - } + /* Step 10 - Config DLL_CONFIG with HSR values */ + if (msm_host->dll_hsr && msm_host->dll_hsr->dll_config) + writel_relaxed(msm_host->dll_hsr->dll_config | + CORE_DLL_RST | CORE_DLL_PDN, host->ioaddr + + msm_offset->core_dll_config); + else + writel_relaxed(DLL_CONFIG_POR_VAL, host->ioaddr + + msm_offset->core_dll_config); /* Step 11 - Wait for 52us */ spin_unlock_irqrestore(&host->lock, flags); @@ -942,27 +941,22 @@ static int msm_init_cm_dll(struct sdhci_host *host, msm_offset->core_dll_config_2); } - /* Step 16 - Set DLL_EN bit to 1. */ - writel_relaxed((readl_relaxed(host->ioaddr + - msm_offset->core_dll_config) | CORE_DLL_EN), - host->ioaddr + msm_offset->core_dll_config); - /* - * Step 17 - Wait for 8000 input clock. Here we calculate the + * Step 16 - Wait for 8000 input clock. Here we calculate the * delay from fixed clock freq 192MHz, which turns out 42us. */ spin_unlock_irqrestore(&host->lock, flags); usleep_range(45, 50); spin_lock_irqsave(&host->lock, flags); - /* Step 18 - Set CK_OUT_EN bit to 1. */ + /* Step 17 - Set CK_OUT_EN bit to 1. */ writel_relaxed((readl_relaxed(host->ioaddr + msm_offset->core_dll_config) | CORE_CK_OUT_EN), host->ioaddr + msm_offset->core_dll_config); /* - * Step 19 - Wait until DLL_LOCK bit of DLL_STATUS register + * Step 18 - Wait until DLL_LOCK bit of DLL_STATUS register * becomes '1'. */ while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & @@ -980,7 +974,7 @@ static int msm_init_cm_dll(struct sdhci_host *host, out: if (core_vendor_spec & CORE_CLK_PWRSAVE) { - /* Step 20 - Reenable PWRSAVE as needed */ + /* Step 19 - Reenable PWRSAVE as needed */ writel_relaxed((readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec) | CORE_CLK_PWRSAVE), host->ioaddr + @@ -1240,7 +1234,7 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) else ddr_cfg_offset = msm_offset->core_ddr_config_old; - if (msm_host->dll_hsr->ddr_config) + if (msm_host->dll_hsr && msm_host->dll_hsr->ddr_config) config = msm_host->dll_hsr->ddr_config; else config = DDR_CONFIG_POR_VAL;