mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 11:11:45 -04:00
Pin control bulk changes for the v4.11 kernel cycle:
Core changes:
- Switch the generic pin config argument from 16 to 24 bits,
only use 8 bits for the configuration type. We might need to
encode more information about a certain setting than we need
to encode different generic settings.
- Add a cross-talk API to the pin control GPIO back-end,
utilizing pinctrl_gpio_set_config() from GPIO drivers that
want to set up a certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the
GPIO chips, so that they pass a generic configuration for
things like debouncing and single ended (typically open
drain). This change has also been merged in an immutable
branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing
a pin controller before trying to get any hogs.
- For pin controllers putting all group and function definitions
into the device tree, we now have generic code to deal with
this and it is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down.
New subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in
the LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on
GPIOs. Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode.
STM32H743 MCU support.
- Allwinner sunxi: deep simplifications on how to support
subvariants of SoCs without adding to much SoC-specific data
for each subvariant, especially for sun5i variants. New driver
for V3s SoCs. New driver for the H5 SoC. Support A31/A31s
variants with the new variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction.
New subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the
SoC driver to access regmaps. Add infrastructure for pin-bank
retention control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly
in the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm
driver realtime-safe.
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Merge tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Pin control bulk changes for the v4.11 kernel cycle.
Core changes:
- Switch the generic pin config argument from 16 to 24 bits, only use
8 bits for the configuration type. We might need to encode more
information about a certain setting than we need to encode
different generic settings.
- Add a cross-talk API to the pin control GPIO back-end, utilizing
pinctrl_gpio_set_config() from GPIO drivers that want to set up a
certain pin configuration in the back-end.
This also includes the .set_config() refactoring of the GPIO chips,
so that they pass a generic configuration for things like
debouncing and single ended (typically open drain). This change has
also been merged in an immutable branch to the GPIO tree.
- Take hogs with a delayed work, so that we finalize probing a pin
controller before trying to get any hogs.
- For pin controllers putting all group and function definitions into
the device tree, we now have generic code to deal with this and it
is used in two drivers so far.
- Simplifications of the pin request conflict check.
- Make dt_free_map() optional.
Updates to drivers:
- pinctrl-single now use the generic helpers to generate dynamic
group and function tables from the device tree.
- Texas Instruments IOdelay configuration driver add-on to
pinctrl-single.
- i.MX: use radix trees to store groups and functions, use the new
generic group and function helpers to manage them.
- Intel: add support for hardware debouncing and 1K pull-down. New
subdriver for the Gemini Lake SoC.
- Renesas SH-PFC: drive strength and bias support, CAN bus muxing,
MSIOF, SDHI, HSCIF for r8a7796. Gyro-ADC supporton r8a7791.
- Aspeed: use syscon cross-dependencies to set up related bits in the
LPC host controller and display controller.
- Aspeed: finalize G4 and G5 support. Fix mux configuration on GPIOs.
Add banks Y, Z, AA, AB and AC.
- AMD: support additional GPIO.
- STM32: set this controller to strict muxing mode. STM32H743 MCU
support.
- Allwinner sunxi: deep simplifications on how to support subvariants
of SoCs without adding to much SoC-specific data for each
subvariant, especially for sun5i variants. New driver for V3s SoCs.
New driver for the H5 SoC. Support A31/A31s variants with the new
variant framework.
- Mvebu: simplifications to use a MMIO and regmap abstraction. New
subdrivers for the 98DX3236, 98DX5241 SoCs.
- Samsung Exynos: delete Exynos4415 support. Add crosstalk to the SoC
driver to access regmaps. Add infrastructure for pin-bank retention
control. Clean out the pin retention control from
arch/arm/mach-exynos and arch/arm/mach-s5p and put it properly in
the Samsung pin control driver(s).
- Meson: add HDMI HPD/DDC pins. Add pwm_ao_b pin.
- Qualcomm: use raw spinlock variants: this makes the qualcomm driver
realtime-safe"
* tag 'pinctrl-v4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (111 commits)
pinctrl: samsung: Fix return value check in samsung_pinctrl_get_soc_data()
pinctrl: intel: unlock on error in intel_config_set_pull()
pinctrl: berlin: make bool drivers explicitly non-modular
pinctrl: spear: make bool drivers explicitly non-modular
pinctrl: mvebu: make bool drivers explicitly non-modular
pinctrl: sunxi: make sun5i explicitly non-modular
pinctrl: sunxi: Remove stray printk call in sun5i driver's probe function
pinctrl: samsung: mark PM functions as __maybe_unused
pinctrl: sunxi: Remove redundant A31s pinctrl driver
pinctrl: sunxi: Support A31/A31s with pinctrl variants
pinctrl: Amend bindings for STM32 pinctrl
pinctrl: Add STM32 pinctrl driver DT bindings
pinctrl: stm32: Add STM32H743 MCU support
include: dt-bindings: Add STM32H7 pinctrl DT defines
gpio: aspeed: Remove dependence on GPIOF_* macros
pinctrl: stm32: fix bad location of gpiochip_lock_as_irq
drivers: pinctrl: add driver for Allwinner H5 SoC
pinctrl: intel: Add Intel Gemini Lake pin controller support
pinctrl: intel: Add support for 1k additional pull-down
pinctrl: intel: Add support for hardware debouncer
...
This commit is contained in:
Linus Torvalds
commit
5ab356626f
143 changed files with 14077 additions and 3931 deletions
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@ -23,6 +23,7 @@ Required properties:
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"allwinner,sun8i-h3-pinctrl"
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"allwinner,sun8i-h3-r-pinctrl"
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"allwinner,sun50i-a64-pinctrl"
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"allwinner,sun50i-h5-r-pinctrl"
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"nextthing,gr8-pinctrl"
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- reg: Should contain the register physical address and length for the
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|
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@ -19,7 +19,7 @@ iomuxc: iomuxc@30330000 {
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reg = <0x30330000 0x10000>;
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};
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Pheriparials using pads from iomuxc-lpsr support low state retention power
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Peripherals using pads from iomuxc-lpsr support low state retention power
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state, under LPSR mode GPIO's state of pads are retain.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
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|
|
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@ -0,0 +1,46 @@
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* Marvell 98dx3236 pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage
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Required properties:
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- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
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- reg: register specifier of MPP registers
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This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
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name pins functions
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================================================================================
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mpp0 0 gpo, spi0(mosi), dev(ad8)
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mpp1 1 gpio, spi0(miso), dev(ad9)
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mpp2 2 gpo, spi0(sck), dev(ad10)
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mpp3 3 gpio, spi0(cs0), dev(ad11)
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mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
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mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
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mpp6 6 gpo, sd0(clk), dev(a2)
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mpp7 7 gpio, sd0(d0), dev(ale0)
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mpp8 8 gpio, sd0(d1), dev(ale1)
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mpp9 9 gpio, sd0(d2), dev(ready0)
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mpp10 10 gpio, sd0(d3), dev(ad12)
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mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13)
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mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14)
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mpp13 13 gpio, intr(out), dev(ad15)
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mpp14 14 gpio, i2c0(sck)
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mpp15 15 gpio, i2c0(sda)
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mpp16 16 gpo, dev(oe)
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mpp17 17 gpo, dev(clkout)
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mpp18 18 gpio, uart1(txd)
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mpp19 19 gpio, uart1(rxd), dev(rb)
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mpp20 20 gpo, dev(we0)
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mpp21 21 gpo, dev(ad0)
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mpp22 22 gpo, dev(ad1)
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mpp23 23 gpo, dev(ad2)
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mpp24 24 gpo, dev(ad3)
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mpp25 25 gpo, dev(ad4)
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mpp26 26 gpo, dev(ad5)
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mpp27 27 gpo, dev(ad6)
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mpp28 28 gpo, dev(ad7)
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mpp29 29 gpo, dev(a0)
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mpp30 30 gpo, dev(a1)
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mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
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mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
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@ -44,16 +44,16 @@ mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
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mpp17 17 gpio, sdio(d3)
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mpp18 18 gpo, nand(io0)
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mpp19 19 gpo, nand(io1)
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mpp20 20 gpio, mii(rxerr)
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mpp21 21 gpio, audio(spdifi)
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mpp22 22 gpio, audio(spdifo)
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mpp23 23 gpio, audio(rmclk)
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mpp24 24 gpio, audio(bclk)
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mpp25 25 gpio, audio(sdo)
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mpp26 26 gpio, audio(lrclk)
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mpp27 27 gpio, audio(mclk)
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mpp28 28 gpio, audio(sdi)
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mpp29 29 gpio, audio(extclk)
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mpp35 35 gpio, mii(rxerr)
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mpp36 36 gpio, audio(spdifi)
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mpp37 37 gpio, audio(spdifo)
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mpp38 38 gpio, audio(rmclk)
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mpp39 39 gpio, audio(bclk)
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mpp40 40 gpio, audio(sdo)
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mpp41 41 gpio, audio(lrclk)
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mpp42 42 gpio, audio(mclk)
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mpp43 43 gpio, audio(sdi)
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mpp44 44 gpio, audio(extclk)
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* Marvell Kirkwood 88f6190
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|
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@ -1,25 +1,38 @@
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======================
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Aspeed Pin Controllers
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----------------------
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======================
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The Aspeed SoCs vary in functionality inside a generation but have a common mux
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device register layout.
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Required properties:
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- compatible : Should be any one of the following:
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"aspeed,ast2400-pinctrl"
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"aspeed,g4-pinctrl"
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"aspeed,ast2500-pinctrl"
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"aspeed,g5-pinctrl"
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Required properties for g4:
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- compatible : Should be one of the following:
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"aspeed,ast2400-pinctrl"
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"aspeed,g4-pinctrl"
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The pin controller node should be a child of a syscon node with the required
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Required properties for g5:
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- compatible : Should be one of the following:
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"aspeed,ast2500-pinctrl"
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"aspeed,g5-pinctrl"
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- aspeed,external-nodes: A cell of phandles to external controller nodes:
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0: compatible with "aspeed,ast2500-gfx", "syscon"
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1: compatible with "aspeed,ast2500-lhc", "syscon"
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The pin controller node should be the child of a syscon node with the required
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property:
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- compatible: "syscon", "simple-mfd"
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- compatible : Should be one of the following:
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"aspeed,ast2400-scu", "syscon", "simple-mfd"
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"aspeed,g4-scu", "syscon", "simple-mfd"
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"aspeed,ast2500-scu", "syscon", "simple-mfd"
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"aspeed,g5-scu", "syscon", "simple-mfd"
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Refer to the the bindings described in
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Documentation/devicetree/bindings/mfd/syscon.txt
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Subnode Format
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--------------
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==============
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The required properties of child nodes are (as defined in pinctrl-bindings):
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- function
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@ -31,26 +44,43 @@ supported:
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aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
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ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10
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I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1
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MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3
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NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16
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ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3
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TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30
|
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VPO12 VPO24
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ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
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ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
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GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
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I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
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MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
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NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
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PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
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ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
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SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
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SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
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TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
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VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
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aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
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GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
|
||||
I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
|
||||
RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
|
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TIMER7 TIMER8 VGABIOSROM
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ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
|
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ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
|
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GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
|
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I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME
|
||||
LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1
|
||||
NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2
|
||||
NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4
|
||||
PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10
|
||||
SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
|
||||
SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
|
||||
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
|
||||
SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
|
||||
TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
|
||||
|
||||
Examples
|
||||
========
|
||||
|
||||
Examples:
|
||||
g4 Example
|
||||
----------
|
||||
|
||||
syscon: scu@1e6e2000 {
|
||||
compatible = "syscon", "simple-mfd";
|
||||
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
|
||||
reg = <0x1e6e2000 0x1a8>;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
|
|
@ -63,5 +93,56 @@ syscon: scu@1e6e2000 {
|
|||
};
|
||||
};
|
||||
|
||||
g5 Example
|
||||
----------
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
syscon: scu@1e6e2000 {
|
||||
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
|
||||
reg = <0x1e6e2000 0x1a8>;
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "aspeed,g5-pinctrl";
|
||||
aspeed,external-nodes = <&gfx &lhc>;
|
||||
|
||||
pinctrl_i2c3_default: i2c3_default {
|
||||
function = "I2C3";
|
||||
groups = "I2C3";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gfx: display@1e6e6000 {
|
||||
compatible = "aspeed,ast2500-gfx", "syscon";
|
||||
reg = <0x1e6e6000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
lpc: lpc@1e789000 {
|
||||
compatible = "aspeed,ast2500-lpc", "simple-mfd";
|
||||
reg = <0x1e789000 0x1000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x1e789000 0x1000>;
|
||||
|
||||
lpc_host: lpc-host@80 {
|
||||
compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
|
||||
reg = <0x80 0x1e0>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x80 0x1e0>;
|
||||
|
||||
lhc: lhc@20 {
|
||||
compatible = "aspeed,ast2500-lhc";
|
||||
reg = <0x20 0x24 0x48 0x8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices.
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ Required Properties:
|
|||
- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
|
||||
- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
|
||||
- "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
|
||||
- "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
|
||||
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
|
||||
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
|
||||
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
|
||||
|
|
|
|||
|
|
@ -8,8 +8,9 @@ controllers onto these pads.
|
|||
Pin controller node:
|
||||
Required properies:
|
||||
- compatible: value should be one of the following:
|
||||
(a) "st,stm32f429-pinctrl"
|
||||
(b) "st,stm32f746-pinctrl"
|
||||
"st,stm32f429-pinctrl"
|
||||
"st,stm32f746-pinctrl"
|
||||
"st,stm32h743-pinctrl"
|
||||
- #address-cells: The value of this property must be 1
|
||||
- #size-cells : The value of this property must be 1
|
||||
- ranges : defines mapping between pin controller node (parent) to
|
||||
|
|
@ -37,8 +38,23 @@ Optional properties:
|
|||
- st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
|
||||
which includes IRQ mux selection register, and the offset of the IRQ mux
|
||||
selection register.
|
||||
- ngpios: Number of gpios in a bank (to use if bank gpio numbers is less
|
||||
than 16).
|
||||
- gpio-ranges: Define a dedicated mapping between a pin-controller and
|
||||
a gpio controller. Format is <&phandle a b c> with:
|
||||
-(phandle): phandle of pin-controller.
|
||||
-(a): gpio base offset in range.
|
||||
-(b): pin base offset in range.
|
||||
-(c): gpio count in range
|
||||
This entry has to be used either if there are holes inside a bank:
|
||||
GPIOB0/B1/B2/B14/B15 (see example 2)
|
||||
or if banks are not contiguous:
|
||||
GPIOA/B/C/E...
|
||||
NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
|
||||
have to use a "gpio-ranges" entry.
|
||||
More details in Documentation/devicetree/bindings/gpio/gpio.txt.
|
||||
|
||||
Example:
|
||||
Example 1:
|
||||
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
|
||||
...
|
||||
|
||||
|
|
@ -60,6 +76,43 @@ Example:
|
|||
pin-functions nodes follow...
|
||||
};
|
||||
|
||||
Example 2:
|
||||
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
|
||||
...
|
||||
|
||||
pinctrl: pin-controller {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32f429-pinctrl";
|
||||
ranges = <0 0x40020000 0x3000>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
resets = <&reset_ahb1 0>;
|
||||
st,bank-name = "GPIOA";
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
resets = <&reset_ahb1 0>;
|
||||
st,bank-name = "GPIOB";
|
||||
ngpios = 4;
|
||||
gpio-ranges = <&pinctrl 0 16 3>,
|
||||
<&pinctrl 14 30 2>;
|
||||
};
|
||||
|
||||
|
||||
...
|
||||
pin-functions nodes follow...
|
||||
};
|
||||
|
||||
|
||||
Contents of function subnode node:
|
||||
----------------------------------
|
||||
Subnode format
|
||||
|
|
|
|||
47
Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt
Normal file
47
Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
* Pin configuration for TI IODELAY controller
|
||||
|
||||
TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
|
||||
for each pin. For most part the IO delay values are programmed by the bootloader,
|
||||
but some pins need to be configured dynamically by the kernel such as the
|
||||
MMC pins.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "ti,dra7-iodelay"
|
||||
- reg: Base address and length of the memory resource used
|
||||
- #address-cells: Number of address cells
|
||||
- #size-cells: Size of cells
|
||||
- #pinctrl-cells: Number of pinctrl cells, must be 2. See also
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
In the SoC specific dtsi file:
|
||||
|
||||
dra7_iodelay_core: padconf@4844a000 {
|
||||
compatible = "ti,dra7-iodelay";
|
||||
reg = <0x4844a000 0x0d1c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#pinctrl-cells = <2>;
|
||||
};
|
||||
|
||||
In board-specific file:
|
||||
|
||||
&dra7_iodelay_core {
|
||||
mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf {
|
||||
pinctrl-pin-array = <
|
||||
0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
|
||||
0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
|
||||
0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
|
||||
0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
|
||||
0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
|
||||
0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
|
||||
0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
|
||||
0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
|
||||
0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
|
||||
0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in a new issue