From 787d287d9e9312e21d757eb1a5f0006dacadd6dd Mon Sep 17 00:00:00 2001 From: Hemant Kumar Date: Wed, 5 May 2021 13:52:20 -0700 Subject: [PATCH] PCIe: ASPM: Save/restore ASPM-L1SS controls in reverse order Commit 54fdb1e44845be ("PCIe: ASPM: Save/restore ASPM-L1SS controls for suspend/resume") restores PCI_L1SS_CTL1, then PCI_L1SS_CTL2. It should do those in the reverse order, since the Enable bits are in PCI_L1SS_CTL1. It also restores L1SS state before we restore the PCIe Capability potentially enabling ASPM as a whole. Fix the issue by changing order for both save and restore. Change-Id: I84e3db25b651b93dd4c037fa287f58edde90407a Signed-off-by: Hemant Kumar --- drivers/pci/pcie/aspm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 15bf2f310df4..e4b391b94140 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -761,8 +761,8 @@ void pci_save_aspm_l1ss_state(struct pci_dev *dev) return; cap = (u32 *)&save_state->cap.data[0]; - pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap++); pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, cap++); + pci_read_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, cap); } void pci_restore_aspm_l1ss_state(struct pci_dev *dev) @@ -780,8 +780,8 @@ void pci_restore_aspm_l1ss_state(struct pci_dev *dev) return; cap = (u32 *)&save_state->cap.data[0]; - pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap++); pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL2, *cap++); + pci_write_config_dword(dev, aspm_l1ss + PCI_L1SS_CTL1, *cap); } #endif