From 7cf108c14d9126ae47dd07adaaa6d8c21ae2db10 Mon Sep 17 00:00:00 2001
From: Konstantin Dorfman <kdorfman@qti.qualcomm.com>
Date: Sun, 17 Nov 2019 18:14:19 +0200
Subject: [PATCH] ARM: dts: qcom: Add spcom to support SPU on lahaina

spcom driver used to communicate to Secure Processor as RPMSG/glink client.
This change configures spcom platform device on lahaina.

Change-Id: I8daf9eba606abab128ae84d4248cda70ad40a90a
---
 qcom/lahaina.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index 65fb446cbd32..b8feef921a58 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -1893,6 +1893,21 @@
 		hyplog-address-offset = <0x410>;
 		hyplog-size-offset = <0x414>;
 	};
+
+	qcom,spcom {
+		compatible = "qcom,spcom";
+
+		/* predefined channels, remote side is server */
+		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
+		/* sp2soc rmb shared register physical address and bmsk */
+		qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
+		qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
+		qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
+		/* soc2sp rmb shared register physical address */
+		qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
+		qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
+		status = "ok";
+	};
 };
 
 #include "lahaina-regulators.dtsi"