mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 22:23:14 -04:00
Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (390 commits) drm/radeon/kms: disable underscan by default drm/radeon/kms: only enable hdmi features if the monitor supports audio drm: Restore the old_fb upon modeset failure drm/nouveau: fix hwmon device binding radeon: consolidate asic-specific function decls for pre-r600 vga_switcheroo: comparing too few characters in strncmp() drm/radeon/kms: add NI pci ids drm/radeon/kms: don't enable pcie gen2 on NI yet drm/radeon/kms: add radeon_asic struct for NI asics drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init drm/radeon/kms: add ucode loader for NI drm/radeon/kms: add support for DCE5 display LUTs drm/radeon/kms: add ni_reg.h drm/radeon/kms: add bo blit support for NI drm/radeon/kms: always use writeback/events for fences on NI drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5 drm/radeon/kms: add backend map workaround for barts drm/radeon/kms: fill gpu init for NI asics drm/radeon/kms: add disabled vbios accessor for NI asics drm/radeon/kms: handle NI thermal controller ...
This commit is contained in:
commit
5b2eef966c
187 changed files with 24886 additions and 10827 deletions
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@ -120,7 +120,6 @@ struct agp_bridge_driver {
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void (*agp_destroy_page)(struct page *, int flags);
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void (*agp_destroy_pages)(struct agp_memory *);
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int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
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void (*chipset_flush)(struct agp_bridge_data *);
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};
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struct agp_bridge_data {
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@ -276,7 +276,6 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
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break;
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case AGPIOC_CHIPSET_FLUSH32:
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ret_val = agpioc_chipset_flush_wrap(curr_priv);
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break;
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}
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@ -102,6 +102,5 @@ void agp_free_memory_wrap(struct agp_memory *memory);
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struct agp_memory *agp_allocate_memory_wrap(size_t pg_count, u32 type);
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struct agp_memory *agp_find_mem_by_key(int key);
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struct agp_client *agp_find_client_by_pid(pid_t id);
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int agpioc_chipset_flush_wrap(struct agp_file_private *priv);
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#endif /* _AGP_COMPAT_H */
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@ -957,13 +957,6 @@ static int agpioc_unbind_wrap(struct agp_file_private *priv, void __user *arg)
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return agp_unbind_memory(memory);
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}
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int agpioc_chipset_flush_wrap(struct agp_file_private *priv)
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{
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DBG("");
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agp_flush_chipset(agp_bridge);
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return 0;
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}
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static long agp_ioctl(struct file *file,
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unsigned int cmd, unsigned long arg)
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{
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@ -1039,7 +1032,6 @@ static long agp_ioctl(struct file *file,
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break;
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case AGPIOC_CHIPSET_FLUSH:
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ret_val = agpioc_chipset_flush_wrap(curr_priv);
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break;
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}
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@ -81,13 +81,6 @@ static int agp_get_key(void)
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return -1;
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}
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void agp_flush_chipset(struct agp_bridge_data *bridge)
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{
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if (bridge->driver->chipset_flush)
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bridge->driver->chipset_flush(bridge);
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}
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EXPORT_SYMBOL(agp_flush_chipset);
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/*
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* Use kmalloc if possible for the page list. Otherwise fall back to
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* vmalloc. This speeds things up and also saves memory for small AGP
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@ -487,26 +480,6 @@ int agp_unbind_memory(struct agp_memory *curr)
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}
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EXPORT_SYMBOL(agp_unbind_memory);
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/**
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* agp_rebind_emmory - Rewrite the entire GATT, useful on resume
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*/
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int agp_rebind_memory(void)
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{
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struct agp_memory *curr;
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int ret_val = 0;
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spin_lock(&agp_bridge->mapped_lock);
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list_for_each_entry(curr, &agp_bridge->mapped_list, mapped_list) {
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ret_val = curr->bridge->driver->insert_memory(curr,
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curr->pg_start,
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curr->type);
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if (ret_val != 0)
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break;
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}
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spin_unlock(&agp_bridge->mapped_lock);
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return ret_val;
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}
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EXPORT_SYMBOL(agp_rebind_memory);
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/* End - Routines for handling swapping of agp_memory into the GATT */
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@ -828,14 +828,9 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
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static int agp_intel_resume(struct pci_dev *pdev)
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{
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struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
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int ret_val;
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bridge->driver->configure();
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ret_val = agp_rebind_memory();
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if (ret_val != 0)
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return ret_val;
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return 0;
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}
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#endif
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@ -75,6 +75,8 @@
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#define I810_GMS_DISABLE 0x00000000
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#define I810_PGETBL_CTL 0x2020
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#define I810_PGETBL_ENABLED 0x00000001
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/* Note: PGETBL_CTL2 has a different offset on G33. */
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#define I965_PGETBL_CTL2 0x20c4
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#define I965_PGETBL_SIZE_MASK 0x0000000e
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#define I965_PGETBL_SIZE_512KB (0 << 1)
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#define I965_PGETBL_SIZE_256KB (1 << 1)
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@ -82,9 +84,15 @@
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#define I965_PGETBL_SIZE_1MB (3 << 1)
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#define I965_PGETBL_SIZE_2MB (4 << 1)
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#define I965_PGETBL_SIZE_1_5MB (5 << 1)
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#define G33_PGETBL_SIZE_MASK (3 << 8)
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#define G33_PGETBL_SIZE_1M (1 << 8)
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#define G33_PGETBL_SIZE_2M (2 << 8)
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#define G33_GMCH_SIZE_MASK (3 << 8)
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#define G33_GMCH_SIZE_1M (1 << 8)
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#define G33_GMCH_SIZE_2M (2 << 8)
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#define G4x_GMCH_SIZE_MASK (0xf << 8)
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#define G4x_GMCH_SIZE_1M (0x1 << 8)
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#define G4x_GMCH_SIZE_2M (0x3 << 8)
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#define G4x_GMCH_SIZE_VT_1M (0x9 << 8)
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#define G4x_GMCH_SIZE_VT_1_5M (0xa << 8)
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#define G4x_GMCH_SIZE_VT_2M (0xc << 8)
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#define I810_DRAM_CTL 0x3000
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#define I810_DRAM_ROW_0 0x00000001
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