mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
Merge "drivers: irqchip: qcom-pdc: Add PDC IRQ chip support for sm8150"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
5b668a4482
4 changed files with 261 additions and 7 deletions
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@ -542,7 +542,6 @@ fail:
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return ret;
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}
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#ifdef MODULE
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static int qcom_pdc_probe(struct platform_device *pdev)
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{
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@ -554,6 +553,7 @@ static int qcom_pdc_probe(struct platform_device *pdev)
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static const struct of_device_id qcom_pdc_match_table[] = {
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{ .compatible = "qcom,lahaina-pdc" },
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{ .compatible = "qcom,shima-pdc" },
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{ .compatible = "qcom,sm8150-pdc" },
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{ .compatible = "qcom,yupik-pdc" },
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{}
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};
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@ -571,6 +571,7 @@ module_platform_driver(qcom_pdc_driver);
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IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
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IRQCHIP_DECLARE(pdc_lahaina, "qcom,lahaina-pdc", qcom_pdc_init);
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IRQCHIP_DECLARE(pdc_shima, "qcom,shima-pdc", qcom_pdc_init);
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IRQCHIP_DECLARE(pdc_sm8150, "qcom,sm8150-pdc", qcom_pdc_init);
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IRQCHIP_DECLARE(pdc_yupik, "qcom,yupik-pdc", qcom_pdc_init);
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IRQCHIP_DECLARE(pdc_sdxlemur, "qcom,sdxlemur-pdc", qcom_pdc_init);
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#endif
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@ -45,6 +45,7 @@
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* @chip: gpiochip handle.
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* @restart_nb: restart notifier block.
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* @irq: parent irq for the TLMM irq_chip.
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* @n_dir_conns: The number of pins directly connected to GIC.
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* @lock: Spinlock to protect register resources as well
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* as msm_pinctrl data structures.
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* @enabled_irqs: Bitmap of currently enabled irqs.
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@ -63,6 +64,7 @@ struct msm_pinctrl {
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struct irq_chip irq_chip;
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int irq;
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int n_dir_conns;
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raw_spinlock_t lock;
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@ -713,16 +715,45 @@ static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
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val, val2);
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}
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static bool is_gpio_dual_edge(struct irq_data *d, irq_hw_number_t *irq)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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struct msm_dir_conn *dc;
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int i;
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for (i = pctrl->n_dir_conns; i > 0; i--) {
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dc = &pctrl->soc->dir_conn[i];
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if (dc->gpio == d->hwirq) {
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*irq = dc->irq;
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return true;
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}
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}
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return false;
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}
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static void msm_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct msm_pingroup *g;
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unsigned long flags;
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struct irq_data *dir_conn_data;
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irq_hw_number_t dir_conn_irq = 0;
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u32 val;
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if (d->parent_data)
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if (d->parent_data) {
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if (is_gpio_dual_edge(d, &dir_conn_irq)) {
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dir_conn_data = irq_get_irq_data(dir_conn_irq);
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if (!dir_conn_data)
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return;
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dir_conn_data->chip->irq_mask(dir_conn_data);
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}
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irq_chip_mask_parent(d);
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}
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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@ -768,11 +799,21 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct msm_pingroup *g;
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struct irq_data *dir_conn_data;
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irq_hw_number_t dir_conn_irq = 0;
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unsigned long flags;
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u32 val;
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if (d->parent_data)
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if (d->parent_data) {
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if (is_gpio_dual_edge(d, &dir_conn_irq)) {
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dir_conn_data = irq_get_irq_data(dir_conn_irq);
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if (!dir_conn_data)
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return;
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dir_conn_data->chip->irq_unmask(dir_conn_data);
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}
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irq_chip_unmask_parent(d);
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}
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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@ -806,6 +847,8 @@ static void msm_gpio_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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struct irq_data *dir_conn_data;
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irq_hw_number_t dir_conn_irq = 0;
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/*
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* Clear the interrupt that may be pending before we enable
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@ -817,6 +860,15 @@ static void msm_gpio_irq_enable(struct irq_data *d)
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* GIC needs to be cleared before enabling.
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*/
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if (d->parent_data) {
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if (is_gpio_dual_edge(d, &dir_conn_irq)) {
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dir_conn_data = irq_get_irq_data(dir_conn_irq);
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if (!dir_conn_data)
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return;
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irq_set_irqchip_state(dir_conn_irq,
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IRQCHIP_STATE_PENDING, 0);
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dir_conn_data->chip->irq_unmask(dir_conn_data);
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}
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irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
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irq_chip_enable_parent(d);
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}
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@ -831,9 +883,19 @@ static void msm_gpio_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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struct irq_data *dir_conn_data;
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irq_hw_number_t dir_conn_irq = 0;
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if (d->parent_data)
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if (d->parent_data) {
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if (is_gpio_dual_edge(d, &dir_conn_irq)) {
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dir_conn_data = irq_get_irq_data(dir_conn_irq);
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if (!dir_conn_data)
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return;
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dir_conn_data->chip->irq_mask(dir_conn_data);
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}
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irq_chip_disable_parent(d);
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}
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return;
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@ -874,16 +936,147 @@ static void msm_gpio_irq_ack(struct irq_data *d)
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void msm_dirconn_cfg_reg(struct irq_data *d, u32 offset)
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{
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u32 val;
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const struct msm_pingroup *g;
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unsigned long flags;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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g = &pctrl->soc->groups[d->hwirq];
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val = (d->hwirq) & 0xFF;
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writel_relaxed(val, pctrl->regs[g->tile] + g->dir_conn_reg
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+ (offset * 4));
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val = msm_readl_intr_cfg(pctrl, g);
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val |= BIT(g->dir_conn_en_bit);
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msm_writel_intr_cfg(val, pctrl, g);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static void msm_dirconn_uncfg_reg(struct irq_data *d, u32 offset)
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{
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u32 val = 0;
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const struct msm_pingroup *g;
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unsigned long flags;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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raw_spin_lock_irqsave(&pctrl->lock, flags);
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g = &pctrl->soc->groups[d->hwirq];
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writel_relaxed(val, pctrl->regs + g->dir_conn_reg + (offset * 4));
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val = readl_relaxed(pctrl->regs + g->intr_cfg_reg);
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val &= ~BIT(g->dir_conn_en_bit);
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writel_relaxed(val, pctrl->regs + g->intr_cfg_reg);
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raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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}
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static int select_dir_conn_mux(struct irq_data *d, irq_hw_number_t *irq,
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bool add)
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{
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struct msm_dir_conn *dc = NULL;
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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int i, n_dir_conns = pctrl->n_dir_conns;
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for (i = n_dir_conns; i > 0; i--) {
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dc = &pctrl->soc->dir_conn[i];
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if (dc->gpio == d->hwirq && !add) {
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*irq = dc->irq;
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dc->gpio = -1;
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return n_dir_conns - i;
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}
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if (dc->gpio == -1 && add) {
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dc->gpio = (int)d->hwirq;
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*irq = dc->irq;
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return n_dir_conns - i;
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}
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}
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pr_err("%s: No direct connects selected for interrupt %lu\n",
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__func__, d->hwirq);
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return -EBUSY;
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}
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static void msm_gpio_dirconn_handler(struct irq_desc *desc)
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{
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struct irq_data *irqd = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (!irqd)
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return;
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chained_irq_enter(chip, desc);
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generic_handle_irq(irqd->irq);
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chained_irq_exit(chip, desc);
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irq_set_irqchip_state(irq_desc_get_irq_data(desc)->irq,
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IRQCHIP_STATE_ACTIVE, 0);
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}
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static void add_dirconn_tlmm(struct irq_data *d, struct msm_pinctrl *pctrl)
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{
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struct irq_data *dir_conn_data = NULL;
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int offset = 0;
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irq_hw_number_t irq = 0;
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offset = select_dir_conn_mux(d, &irq, true);
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if (offset < 0)
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return;
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msm_dirconn_cfg_reg(d, offset);
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irq_set_handler_data(irq, d);
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dir_conn_data = irq_get_irq_data(irq);
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if (!dir_conn_data)
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return;
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dir_conn_data->chip->irq_unmask(dir_conn_data);
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}
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static void remove_dirconn_tlmm(struct irq_data *d, irq_hw_number_t irq)
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{
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struct irq_data *dir_conn_data = NULL;
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int offset = 0;
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offset = select_dir_conn_mux(d, &irq, false);
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if (offset < 0)
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return;
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msm_dirconn_uncfg_reg(d, offset);
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irq_set_handler_data(irq, NULL);
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dir_conn_data = irq_get_irq_data(irq);
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if (!dir_conn_data)
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return;
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dir_conn_data->chip->irq_mask(dir_conn_data);
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}
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static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
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const struct msm_pingroup *g;
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irq_hw_number_t irq = 0;
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unsigned long flags;
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u32 val;
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if (d->parent_data)
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if (d->parent_data) {
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if (pctrl->n_dir_conns > 0) {
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if (type == IRQ_TYPE_EDGE_BOTH)
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add_dirconn_tlmm(d, pctrl);
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else if (is_gpio_dual_edge(d, &irq))
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remove_dirconn_tlmm(d, irq);
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}
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irq_chip_set_type_parent(d, type);
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}
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if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
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return 0;
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@ -1309,8 +1502,7 @@ int msm_pinctrl_probe(struct platform_device *pdev,
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{
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struct msm_pinctrl *pctrl;
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struct resource *res;
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int ret;
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int i;
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int ret, i, num_irq, irq;
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msm_pinctrl_data = pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl),
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GFP_KERNEL);
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@ -1362,6 +1554,18 @@ int msm_pinctrl_probe(struct platform_device *pdev,
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if (ret)
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return ret;
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num_irq = platform_irq_count(pdev);
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for (i = 1; i < num_irq; i++) {
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struct msm_dir_conn *dc = &soc_data->dir_conn[i];
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irq = platform_get_irq(pdev, i);
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dc->irq = irq;
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__irq_set_handler(irq, msm_gpio_dirconn_handler, false, NULL);
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irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
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pctrl->n_dir_conns++;
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}
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platform_set_drvdata(pdev, pctrl);
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dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
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@ -38,6 +38,7 @@ struct msm_function {
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* @intr_status_reg: Offset of the register holding the status bits for this group.
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* @intr_target_reg: Offset of the register specifying routing of the interrupts
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* from this group.
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* @dir_conn_reg: Offset of the register hmss setup in tile.
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* @mux_bit: Offset in @ctl_reg for the pinmux function selection.
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* @pull_bit: Offset in @ctl_reg for the bias configuration.
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* @drv_bit: Offset in @ctl_reg for the drive strength configuration.
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@ -56,6 +57,7 @@ struct msm_function {
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* @intr_detection_width: Number of bits used for specifying interrupt type,
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* Should be 2 for SoCs that can detect both edges in hardware,
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* otherwise 1.
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* @dir_conn_en_bit: Offset in @intr_cfg_reg for direct connect enable bit
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* @wake_reg: Offset of the WAKEUP_INT_EN register from base tile
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* @wake_bit: Bit number for the corresponding gpio
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*/
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@ -72,6 +74,7 @@ struct msm_pingroup {
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u32 intr_cfg_reg;
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u32 intr_status_reg;
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u32 intr_target_reg;
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u32 dir_conn_reg;
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unsigned int tile:2;
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@ -96,11 +99,22 @@ struct msm_pingroup {
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unsigned intr_polarity_bit:5;
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unsigned intr_detection_bit:5;
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unsigned intr_detection_width:5;
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unsigned dir_conn_en_bit:8;
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u32 wake_reg;
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unsigned int wake_bit;
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};
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|
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/**
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* struct msm_dir_conn - TLMM Direct GPIO connect configuration
|
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* @gpio: GPIO pin number
|
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* @irq: The GIC interrupt that the pin is connected to
|
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*/
|
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struct msm_dir_conn {
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int gpio;
|
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int irq;
|
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};
|
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|
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/*
|
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* struct pinctrl_qup - Qup mode configuration
|
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* @mode: Qup i3c mode
|
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|
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@ -133,6 +147,7 @@ struct msm_gpio_wakeirq_map {
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* @pull_no_keeper: The SoC does not support keeper bias.
|
||||
* @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM
|
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* @nwakeirq_map: The number of entries in @hierarchy_map
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* @dir_conn: An array describing all the pins directly connected to GIC.
|
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*/
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struct msm_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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@ -150,6 +165,7 @@ struct msm_pinctrl_soc_data {
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unsigned int nwakeirq_map;
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struct pinctrl_qup *qup_regs;
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unsigned int nqup_regs;
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struct msm_dir_conn *dir_conn;
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};
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|
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extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
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|
|
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|||
|
|
@ -22,6 +22,11 @@ enum {
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WEST
|
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};
|
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|
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#define HMSS_WEST 0x031BB000
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#define HMSS_EAST 0x035B7000
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#define HMSS_NORTH 0x039BC000
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#define HMSS_SOUTH 0x03DBE000
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#define FUNCTION(fname) \
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[msm_mux_##fname] = { \
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.name = #fname, \
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||||
|
|
@ -53,6 +58,10 @@ enum {
|
|||
.intr_status_reg = 0x1000 * id + 0xc, \
|
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.intr_target_reg = 0x1000 * id + 0x8, \
|
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.tile = _tile, \
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.dir_conn_reg = _tile == WEST ? HMSS_WEST : \
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||||
_tile == EAST ? HMSS_EAST : \
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_tile == NORTH ? HMSS_NORTH : \
|
||||
HMSS_SOUTH, \
|
||||
.mux_bit = 2, \
|
||||
.pull_bit = 0, \
|
||||
.drv_bit = 6, \
|
||||
|
|
@ -69,6 +78,7 @@ enum {
|
|||
.intr_polarity_bit = 1, \
|
||||
.intr_detection_bit = 2, \
|
||||
.intr_detection_width = 2, \
|
||||
.dir_conn_en_bit = 8, \
|
||||
}
|
||||
|
||||
#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
|
||||
|
|
@ -1502,6 +1512,26 @@ static const struct msm_pingroup sm8150_groups[] = {
|
|||
[178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
|
||||
};
|
||||
|
||||
static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
|
||||
{ 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
|
||||
{ 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 },
|
||||
{ 37, 44 }, { 38, 30 }, { 39, 118 }, { 41, 47 }, { 42, 48 },
|
||||
{ 47, 49 }, { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 },
|
||||
{ 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 }, { 60, 60 },
|
||||
{ 68, 62 }, { 70, 63 }, { 76, 71 }, { 77, 66 }, { 81, 64 },
|
||||
{ 86, 67 }, { 87, 84 }, { 88, 117 }, { 90, 69 }, { 91, 70 },
|
||||
{ 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
|
||||
{ 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 }, { 117, 85 },
|
||||
{ 119, 87 }, { 120, 88 }, { 121, 89 }, { 122, 90 }, { 123, 91 },
|
||||
{ 125, 93 }, { 129, 94 }, { 132, 105 }, { 133, 83 }, { 134, 36 },
|
||||
{ 142, 103 }, { 144, 115 }, { 147, 102 }, { 150, 107 }, { 152, 108 },
|
||||
};
|
||||
|
||||
static struct msm_dir_conn sm8150_dir_conn[] = {
|
||||
{-1, 0}, {-1, 0}, {-1, 0}, {-1, 0}, {-1, 0},
|
||||
{-1, 0}, {-1, 0}, {-1, 0}, {-1, 0}
|
||||
};
|
||||
|
||||
static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
|
||||
.pins = sm8150_pins,
|
||||
.npins = ARRAY_SIZE(sm8150_pins),
|
||||
|
|
@ -1512,6 +1542,9 @@ static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
|
|||
.ngpios = 176,
|
||||
.tiles = sm8150_tiles,
|
||||
.ntiles = ARRAY_SIZE(sm8150_tiles),
|
||||
.wakeirq_map = sm8150_pdc_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map),
|
||||
.dir_conn = sm8150_dir_conn,
|
||||
};
|
||||
|
||||
static int sm8150_pinctrl_probe(struct platform_device *pdev)
|
||||
|
|
|
|||
Loading…
Reference in a new issue