From 5b6a3044ee38bab61c701c82dcef8037b8ad7fbc Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Tue, 3 Nov 2020 11:50:51 +0530 Subject: [PATCH] dt-bindings: interconnect: add OSM L3 bindings Add bindings for the new interconnect OSM L3 driver. Change-Id: Ib240d9e8d900539fc6f8112c9fe55d530d51ae95 --- bindings/interconnect/qcom,osm-l3.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 bindings/interconnect/qcom,osm-l3.txt diff --git a/bindings/interconnect/qcom,osm-l3.txt b/bindings/interconnect/qcom,osm-l3.txt new file mode 100644 index 000000000000..4d323fd7750b --- /dev/null +++ b/bindings/interconnect/qcom,osm-l3.txt @@ -0,0 +1,25 @@ +Qualcomm Technologies, Inc. EPSS L3 interconnect driver binding +----------------------------------------------------------- + +The EPSS L3 Interconnect provider supports the scaling of L3 cache +performance states of the CPU subsystem. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,sdm845-osm-l3", + "qcom,sm8150-osm-l3"; +- reg : Address and length of the register set for the device +- clock-names: should contain "xo", "alternate" +- clocks: list of phandle and clock specifier pairs corresponding to + entries in the clock-names property. +- #interconnect-cells : should contain 1 + +Examples: + +osm_l3: interconnect@0x18321000 { + reg = <0x18321000 0x1400>; + compatible = "qcom,sm8150-osm-l3"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; +};