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qcacld-3.0: Add SBS support in hw_mode_list

Browse source 
The enhancement is to add SBS (Single Band Simultaneous)
support in hw_mode_list.

The WMI HW Mode definitions are redefined to use only
for host purpose.

Change-Id: I8b8c966b0130964c8e7de7967766629c955209d3
CRs-Fixed: 1072234
This commit is contained in:
Nitesh Shah 2016-09-28 18:58:33 +05:30 • committed by qcabuildsw
commit 5b7bae07fc
9 changed files with 200 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

13
core/cds/inc/cds_concurrency.h
View file

@ -90,7 +90,7 @@ enum hw_mode_ss_config {
/**
* enum hw_mode_dbs_capab - DBS HW mode capability
* @HW_MODE_DBS_NONE: Non DBS capable
* @HW_MODE_DBS: DFS capable
* @HW_MODE_DBS: DBS capable
*/
enum hw_mode_dbs_capab {
HW_MODE_DBS_NONE,
@ -107,6 +107,16 @@ enum hw_mode_agile_dfs_capab {
HW_MODE_AGILE_DFS,
};
/**
* enum hw_mode_sbs_capab - SBS HW mode capability
* @HW_MODE_SBS_NONE: Non SBS capable
* @HW_MODE_SBS: SBS capable
*/
enum hw_mode_sbs_capab {
HW_MODE_SBS_NONE,
HW_MODE_SBS,
};
/**
* enum cds_pcl_group_id - Identifies the pcl groups to be used
* @CDS_PCL_GROUP_ID1_ID2: Use weights of group1 and group2
@ -780,6 +790,7 @@ QDF_STATUS cds_pdev_set_hw_mode(uint32_t session_id,
enum hw_mode_bandwidth mac1_bw,
enum hw_mode_dbs_capab dbs,
enum hw_mode_agile_dfs_capab dfs,
enum hw_mode_sbs_capab sbs,
enum sir_conn_update_reason reason);
enum cds_conc_next_action cds_need_opportunistic_upgrade(void);
QDF_STATUS cds_next_actions(uint32_t session_id,

24
core/cds/src/cds_concurrency.c
View file

@ -2485,8 +2485,8 @@ static void cds_pdev_set_hw_mode_cb(uint32_t status,
hw_mode.mac0_tx_ss, hw_mode.mac0_rx_ss, hw_mode.mac0_bw);
cds_info("MAC1: TxSS:%d, RxSS:%d, Bw:%d",
hw_mode.mac1_tx_ss, hw_mode.mac1_rx_ss, hw_mode.mac1_bw);
cds_info("DBS:%d, Agile DFS:%d",
hw_mode.dbs_cap, hw_mode.agile_dfs_cap);
cds_info("DBS:%d, Agile DFS:%d, SBS:%d",
hw_mode.dbs_cap, hw_mode.agile_dfs_cap, hw_mode.sbs_cap);
/* update conc_connection_list */
cds_update_hw_mode_conn_info(num_vdev_mac_entries,
@ -2544,8 +2544,8 @@ void cds_hw_mode_transition_cb(uint32_t old_hw_mode_index,
hw_mode.mac0_tx_ss, hw_mode.mac0_rx_ss, hw_mode.mac0_bw);
cds_info("MAC1: TxSS:%d, RxSS:%d, Bw:%d",
hw_mode.mac1_tx_ss, hw_mode.mac1_rx_ss, hw_mode.mac1_bw);
cds_info("DBS:%d, Agile DFS:%d",
hw_mode.dbs_cap, hw_mode.agile_dfs_cap);
cds_info("DBS:%d, Agile DFS:%d, SBS:%d",
hw_mode.dbs_cap, hw_mode.agile_dfs_cap, hw_mode.sbs_cap);
/* update conc_connection_list */
cds_update_hw_mode_conn_info(num_vdev_mac_entries,
@ -2564,6 +2564,7 @@ void cds_hw_mode_transition_cb(uint32_t old_hw_mode_index,
* @mac1_bw: MAC1 bandwidth configuration
* @dbs: HW DBS capability
* @dfs: HW Agile DFS capability
* @sbs: HW SBS capability
* @reason: Reason for connection update
*
* Sends the set hw mode to the SME module which will pass on
@ -2572,15 +2573,18 @@ void cds_hw_mode_transition_cb(uint32_t old_hw_mode_index,
* e.g.: To configure 2x2_80
* mac0_ss = HW_MODE_SS_2x2, mac0_bw = HW_MODE_80_MHZ
* mac1_ss = HW_MODE_SS_0x0, mac1_bw = HW_MODE_BW_NONE
* dbs = HW_MODE_DBS_NONE, dfs = HW_MODE_AGILE_DFS_NONE
* dbs = HW_MODE_DBS_NONE, dfs = HW_MODE_AGILE_DFS_NONE,
* sbs = HW_MODE_SBS_NONE
* e.g.: To configure 1x1_80_1x1_40 (DBS)
* mac0_ss = HW_MODE_SS_1x1, mac0_bw = HW_MODE_80_MHZ
* mac1_ss = HW_MODE_SS_1x1, mac1_bw = HW_MODE_40_MHZ
* dbs = HW_MODE_DBS, dfs = HW_MODE_AGILE_DFS_NONE
* dbs = HW_MODE_DBS, dfs = HW_MODE_AGILE_DFS_NONE,
* sbs = HW_MODE_SBS_NONE
* e.g.: To configure 1x1_80_1x1_40 (Agile DFS)
* mac0_ss = HW_MODE_SS_1x1, mac0_bw = HW_MODE_80_MHZ
* mac1_ss = HW_MODE_SS_1x1, mac1_bw = HW_MODE_40_MHZ
* dbs = HW_MODE_DBS, dfs = HW_MODE_AGILE_DFS
* dbs = HW_MODE_DBS, dfs = HW_MODE_AGILE_DFS,
* sbs = HW_MODE_SBS_NONE
*
* Return: Success if the message made it down to the next layer
*/
@ -2591,6 +2595,7 @@ QDF_STATUS cds_pdev_set_hw_mode(uint32_t session_id,
enum hw_mode_bandwidth mac1_bw,
enum hw_mode_dbs_capab dbs,
enum hw_mode_agile_dfs_capab dfs,
enum hw_mode_sbs_capab sbs,
enum sir_conn_update_reason reason)
{
int8_t hw_mode_index;
@ -2618,7 +2623,7 @@ QDF_STATUS cds_pdev_set_hw_mode(uint32_t session_id,
}
hw_mode_index = wma_get_hw_mode_idx_from_dbs_hw_list(mac0_ss,
mac0_bw, mac1_ss, mac1_bw, dbs, dfs);
mac0_bw, mac1_ss, mac1_bw, dbs, dfs, sbs);
if (hw_mode_index < 0) {
cds_err("Invalid HW mode index obtained");
return QDF_STATUS_E_FAILURE;
@ -6306,6 +6311,7 @@ QDF_STATUS cds_next_actions(uint32_t session_id,
HW_MODE_SS_1x1, HW_MODE_40_MHZ,
HW_MODE_DBS,
HW_MODE_AGILE_DFS_NONE,
HW_MODE_SBS_NONE,
reason);
break;
case CDS_SINGLE_MAC_UPGRADE:
@ -6318,6 +6324,7 @@ QDF_STATUS cds_next_actions(uint32_t session_id,
HW_MODE_SS_0x0, HW_MODE_BW_NONE,
HW_MODE_DBS_NONE,
HW_MODE_AGILE_DFS_NONE,
HW_MODE_SBS_NONE,
reason);
/*
* check if we have a beaconing entity that advertised 2x2
@ -6334,6 +6341,7 @@ QDF_STATUS cds_next_actions(uint32_t session_id,
HW_MODE_SS_0x0, HW_MODE_BW_NONE,
HW_MODE_DBS_NONE,
HW_MODE_AGILE_DFS_NONE,
HW_MODE_SBS_NONE,
reason);
break;
default:

2
core/hdd/src/wlan_hdd_wext.c
View file

@ -8067,6 +8067,7 @@ static int __iw_set_var_ints_getnone(struct net_device *dev,
HW_MODE_SS_0x0, HW_MODE_BW_NONE,
HW_MODE_DBS_NONE,
HW_MODE_AGILE_DFS_NONE,
HW_MODE_SBS_NONE,
SIR_UPDATE_REASON_UT);
} else if (apps_args[0] == 1) {
hdd_err("set hw mode for dual mac");
@ -8077,6 +8078,7 @@ static int __iw_set_var_ints_getnone(struct net_device *dev,
HW_MODE_SS_1x1, HW_MODE_40_MHZ,
HW_MODE_DBS,
HW_MODE_AGILE_DFS_NONE,
HW_MODE_SBS_NONE,
SIR_UPDATE_REASON_UT);
}
}

1
core/mac/inc/sir_api.h
View file

@ -3333,6 +3333,7 @@ struct sir_hw_mode_params {
uint8_t mac1_bw;
uint8_t dbs_cap;
uint8_t agile_dfs_cap;
uint8_t sbs_cap;
};
/**

88
core/wma/inc/wma.h
View file

@ -389,6 +389,94 @@ enum ds_mode {
#define WMA_DEFAULT_HW_MODE_INDEX 0xFFFF
/**
* WMA hardware mode list bit-mask definitions.
* Bits 4:0, 31:29 are unused.
*
* The below definitions are added corresponding to WMI DBS HW mode
* list to make it independent of firmware changes for WMI definitions.
* Currently these definitions have dependency with BIT positions of
* the existing WMI macros. Thus, if the BIT positions are changed for
* WMI macros, then these macros' BIT definitions are also need to be
* changed.
*/
#define WMA_HW_MODE_MAC0_TX_STREAMS_BITPOS (28)
#define WMA_HW_MODE_MAC0_RX_STREAMS_BITPOS (24)
#define WMA_HW_MODE_MAC1_TX_STREAMS_BITPOS (20)
#define WMA_HW_MODE_MAC1_RX_STREAMS_BITPOS (16)
#define WMA_HW_MODE_MAC0_BANDWIDTH_BITPOS (12)
#define WMA_HW_MODE_MAC1_BANDWIDTH_BITPOS (8)
#define WMA_HW_MODE_DBS_MODE_BITPOS (7)
#define WMA_HW_MODE_AGILE_DFS_MODE_BITPOS (6)
#define WMA_HW_MODE_SBS_MODE_BITPOS (5)
#define WMA_HW_MODE_MAC0_TX_STREAMS_MASK \
(0xf << WMA_HW_MODE_MAC0_TX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC0_RX_STREAMS_MASK \
(0xf << WMA_HW_MODE_MAC0_RX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC1_TX_STREAMS_MASK \
(0xf << WMA_HW_MODE_MAC1_TX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC1_RX_STREAMS_MASK \
(0xf << WMA_HW_MODE_MAC1_RX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC0_BANDWIDTH_MASK \
(0xf << WMA_HW_MODE_MAC0_BANDWIDTH_BITPOS)
#define WMA_HW_MODE_MAC1_BANDWIDTH_MASK \
(0xf << WMA_HW_MODE_MAC1_BANDWIDTH_BITPOS)
#define WMA_HW_MODE_DBS_MODE_MASK \
(0x1 << WMA_HW_MODE_DBS_MODE_BITPOS)
#define WMA_HW_MODE_AGILE_DFS_MODE_MASK \
(0x1 << WMA_HW_MODE_AGILE_DFS_MODE_BITPOS)
#define WMA_HW_MODE_SBS_MODE_MASK \
(0x1 << WMA_HW_MODE_SBS_MODE_BITPOS)
#define WMA_HW_MODE_MAC0_TX_STREAMS_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_MAC0_TX_STREAMS_BITPOS, 4, value)
#define WMA_HW_MODE_MAC0_RX_STREAMS_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_MAC0_RX_STREAMS_BITPOS, 4, value)
#define WMA_HW_MODE_MAC1_TX_STREAMS_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_MAC1_TX_STREAMS_BITPOS, 4, value)
#define WMA_HW_MODE_MAC1_RX_STREAMS_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_MAC1_RX_STREAMS_BITPOS, 4, value)
#define WMA_HW_MODE_MAC0_BANDWIDTH_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_MAC0_BANDWIDTH_BITPOS, 4, value)
#define WMA_HW_MODE_MAC1_BANDWIDTH_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_MAC1_BANDWIDTH_BITPOS, 4, value)
#define WMA_HW_MODE_DBS_MODE_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_DBS_MODE_BITPOS, 1, value)
#define WMA_HW_MODE_AGILE_DFS_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_AGILE_DFS_MODE_BITPOS, 1, value)
#define WMA_HW_MODE_SBS_MODE_SET(hw_mode, value) \
WMI_SET_BITS(hw_mode, WMA_HW_MODE_SBS_MODE_BITPOS, 1, value)
#define WMA_HW_MODE_MAC0_TX_STREAMS_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_MAC0_TX_STREAMS_MASK) >> \
WMA_HW_MODE_MAC0_TX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC0_RX_STREAMS_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_MAC0_RX_STREAMS_MASK) >> \
WMA_HW_MODE_MAC0_RX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC1_TX_STREAMS_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_MAC1_TX_STREAMS_MASK) >> \
WMA_HW_MODE_MAC1_TX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC1_RX_STREAMS_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_MAC1_RX_STREAMS_MASK) >> \
WMA_HW_MODE_MAC1_RX_STREAMS_BITPOS)
#define WMA_HW_MODE_MAC0_BANDWIDTH_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_MAC0_BANDWIDTH_MASK) >> \
WMA_HW_MODE_MAC0_BANDWIDTH_BITPOS)
#define WMA_HW_MODE_MAC1_BANDWIDTH_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_MAC1_BANDWIDTH_MASK) >> \
WMA_HW_MODE_MAC1_BANDWIDTH_BITPOS)
#define WMA_HW_MODE_DBS_MODE_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_DBS_MODE_MASK) >> \
WMA_HW_MODE_DBS_MODE_BITPOS)
#define WMA_HW_MODE_AGILE_DFS_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_AGILE_DFS_MODE_MASK) >> \
WMA_HW_MODE_AGILE_DFS_MODE_BITPOS)
#define WMA_HW_MODE_SBS_MODE_GET(hw_mode) \
((hw_mode & WMA_HW_MODE_SBS_MODE_MASK) >> \
WMA_HW_MODE_SBS_MODE_BITPOS)
/**
* struct probeTime_dwellTime - probe time, dwell time map
* @dwell_time: dwell time

3
core/wma/inc/wma_api.h
View file

@ -187,7 +187,8 @@ int8_t wma_get_hw_mode_idx_from_dbs_hw_list(enum hw_mode_ss_config mac0_ss,
enum hw_mode_ss_config mac1_ss,
enum hw_mode_bandwidth mac1_bw,
enum hw_mode_dbs_capab dbs,
enum hw_mode_agile_dfs_capab dfs);
enum hw_mode_agile_dfs_capab dfs,
enum hw_mode_sbs_capab sbs);
QDF_STATUS wma_get_hw_mode_from_idx(uint32_t idx,
struct sir_hw_mode_params *hw_mode);
int8_t wma_get_num_dbs_hw_modes(void);

57
core/wma/src/wma_main.c
View file

@ -4298,16 +4298,17 @@ void wma_dump_dbs_hw_mode(tp_wma_handle wma_handle)
param = wma_handle->hw_mode.hw_mode_list[i];
WMA_LOGA("%s:[%d]-MAC0: tx_ss:%d rx_ss:%d bw_idx:%d",
__func__, i,
WMI_DBS_HW_MODE_MAC0_TX_STREAMS_GET(param),
WMI_DBS_HW_MODE_MAC0_RX_STREAMS_GET(param),
WMI_DBS_HW_MODE_MAC0_BANDWIDTH_GET(param));
WMA_HW_MODE_MAC0_TX_STREAMS_GET(param),
WMA_HW_MODE_MAC0_RX_STREAMS_GET(param),
WMA_HW_MODE_MAC0_BANDWIDTH_GET(param));
WMA_LOGA("%s:[%d]-MAC1: tx_ss:%d rx_ss:%d bw_idx:%d",
__func__, i,
WMI_DBS_HW_MODE_MAC1_TX_STREAMS_GET(param),
WMI_DBS_HW_MODE_MAC1_RX_STREAMS_GET(param),
WMI_DBS_HW_MODE_MAC1_BANDWIDTH_GET(param));
WMA_LOGA("%s:[%d] DBS:%d", __func__, i,
WMI_DBS_HW_MODE_DBS_MODE_GET(param));
WMA_HW_MODE_MAC1_TX_STREAMS_GET(param),
WMA_HW_MODE_MAC1_RX_STREAMS_GET(param),
WMA_HW_MODE_MAC1_BANDWIDTH_GET(param));
WMA_LOGA("%s:[%d] DBS:%d SBS:%d", __func__, i,
WMA_HW_MODE_DBS_MODE_GET(param),
WMA_HW_MODE_SBS_MODE_GET(param));
}
}
@ -5018,6 +5019,7 @@ static void wma_get_hw_mode_params(WMI_MAC_PHY_CAPABILITIES *caps,
* @mac1_ss_bw_info: TX-RX streams, BW for MAC1
* @pos: refers to hw_mode_index
* @dbs_mode: dbs_mode for the dbs_hw_mode
* @sbs_mode: sbs_mode for the sbs_hw_mode
*
* This function sets TX-RX stream, bandwidth and DBS mode in
* hw_mode_list.
@ -5027,32 +5029,36 @@ static void wma_get_hw_mode_params(WMI_MAC_PHY_CAPABILITIES *caps,
static void wma_set_hw_mode_params(t_wma_handle *wma_handle,
struct mac_ss_bw_info mac0_ss_bw_info,
struct mac_ss_bw_info mac1_ss_bw_info,
uint32_t pos, uint32_t dbs_mode)
uint32_t pos, uint32_t dbs_mode,
uint32_t sbs_mode)
{
WMI_DBS_HW_MODE_MAC0_TX_STREAMS_SET(
WMA_HW_MODE_MAC0_TX_STREAMS_SET(
wma_handle->hw_mode.hw_mode_list[pos],
mac0_ss_bw_info.mac_tx_stream);
WMI_DBS_HW_MODE_MAC0_RX_STREAMS_SET(
WMA_HW_MODE_MAC0_RX_STREAMS_SET(
wma_handle->hw_mode.hw_mode_list[pos],
mac0_ss_bw_info.mac_rx_stream);
WMI_DBS_HW_MODE_MAC0_BANDWIDTH_SET(
WMA_HW_MODE_MAC0_BANDWIDTH_SET(
wma_handle->hw_mode.hw_mode_list[pos],
mac0_ss_bw_info.mac_bw);
WMI_DBS_HW_MODE_MAC1_TX_STREAMS_SET(
WMA_HW_MODE_MAC1_TX_STREAMS_SET(
wma_handle->hw_mode.hw_mode_list[pos],
mac1_ss_bw_info.mac_tx_stream);
WMI_DBS_HW_MODE_MAC1_RX_STREAMS_SET(
WMA_HW_MODE_MAC1_RX_STREAMS_SET(
wma_handle->hw_mode.hw_mode_list[pos],
mac1_ss_bw_info.mac_rx_stream);
WMI_DBS_HW_MODE_MAC1_BANDWIDTH_SET(
WMA_HW_MODE_MAC1_BANDWIDTH_SET(
wma_handle->hw_mode.hw_mode_list[pos],
mac1_ss_bw_info.mac_bw);
WMI_DBS_HW_MODE_DBS_MODE_SET(
WMA_HW_MODE_DBS_MODE_SET(
wma_handle->hw_mode.hw_mode_list[pos],
dbs_mode);
WMI_DBS_HW_MODE_AGILE_DFS_SET(
WMA_HW_MODE_AGILE_DFS_SET(
wma_handle->hw_mode.hw_mode_list[pos],
0);
HW_MODE_AGILE_DFS_NONE);
WMA_HW_MODE_SBS_MODE_SET(
wma_handle->hw_mode.hw_mode_list[pos],
sbs_mode);
}
/**
@ -5068,7 +5074,8 @@ static QDF_STATUS wma_update_hw_mode_list(t_wma_handle *wma_handle)
{
struct extended_caps *phy_caps;
WMI_MAC_PHY_CAPABILITIES *tmp;
uint32_t i, dbs_mode, hw_config_type, j = 0;
uint32_t i, hw_config_type, j = 0;
uint32_t dbs_mode, sbs_mode;
struct mac_ss_bw_info mac0_ss_bw_info = {0};
struct mac_ss_bw_info mac1_ss_bw_info = {0};
@ -5117,7 +5124,8 @@ static QDF_STATUS wma_update_hw_mode_list(t_wma_handle *wma_handle)
wma_get_hw_mode_params(tmp, &mac0_ss_bw_info);
hw_config_type =
phy_caps->each_hw_mode_cap[i].hw_mode_config_type;
dbs_mode = 0;
dbs_mode = HW_MODE_DBS_NONE;
sbs_mode = HW_MODE_SBS_NONE;
mac1_ss_bw_info.mac_tx_stream = 0;
mac1_ss_bw_info.mac_rx_stream = 0;
mac1_ss_bw_info.mac_bw = 0;
@ -5129,12 +5137,17 @@ static QDF_STATUS wma_update_hw_mode_list(t_wma_handle *wma_handle)
/* Update for MAC1 */
tmp = &phy_caps->each_phy_cap_per_hwmode[j++];
wma_get_hw_mode_params(tmp, &mac1_ss_bw_info);
dbs_mode = 1;
if (hw_config_type == WMI_HW_MODE_DBS)
dbs_mode = HW_MODE_DBS;
if ((hw_config_type == WMI_HW_MODE_SBS_PASSIVE) ||
(hw_config_type == WMI_HW_MODE_SBS))
sbs_mode = HW_MODE_SBS;
}
/* Updating HW mode list */
wma_set_hw_mode_params(wma_handle, mac0_ss_bw_info,
mac1_ss_bw_info, i, dbs_mode);
mac1_ss_bw_info, i, dbs_mode,
sbs_mode);
}
wma_dump_dbs_hw_mode(wma_handle);
return QDF_STATUS_SUCCESS;

76
core/wma/src/wma_utils.c
View file

@ -2534,6 +2534,7 @@ void wma_get_tx_rx_ss_from_config(enum hw_mode_ss_config mac_ss,
* @mac1_bw: Bandwidth of MAC1 of type 'hw_mode_bandwidth'
* @dbs: DBS capability of type 'hw_mode_dbs_capab'
* @dfs: Agile DFS capability of type 'hw_mode_agile_dfs_capab'
* @sbs: SBS capability of type 'hw_mode_sbs_capab'
*
* Fetches the HW mode index corresponding to the HW mode provided
*
@ -2546,12 +2547,13 @@ static int8_t wma_get_matching_hw_mode_index(tp_wma_handle wma,
uint32_t mac1_tx_ss, uint32_t mac1_rx_ss,
enum hw_mode_bandwidth mac1_bw,
enum hw_mode_dbs_capab dbs,
enum hw_mode_agile_dfs_capab dfs)
enum hw_mode_agile_dfs_capab dfs,
enum hw_mode_sbs_capab sbs)
{
uint32_t i;
uint32_t t_mac0_tx_ss, t_mac0_rx_ss, t_mac0_bw;
uint32_t t_mac1_tx_ss, t_mac1_rx_ss, t_mac1_bw;
uint32_t dbs_mode, agile_dfs_mode;
uint32_t dbs_mode, agile_dfs_mode, sbs_mode;
int8_t found = -EINVAL;
if (!wma) {
@ -2560,17 +2562,17 @@ static int8_t wma_get_matching_hw_mode_index(tp_wma_handle wma,
}
for (i = 0; i < wma->num_dbs_hw_modes; i++) {
t_mac0_tx_ss = WMI_DBS_HW_MODE_MAC0_TX_STREAMS_GET(
t_mac0_tx_ss = WMA_HW_MODE_MAC0_TX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
if (t_mac0_tx_ss != mac0_tx_ss)
continue;
t_mac0_rx_ss = WMI_DBS_HW_MODE_MAC0_RX_STREAMS_GET(
t_mac0_rx_ss = WMA_HW_MODE_MAC0_RX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
if (t_mac0_rx_ss != mac0_rx_ss)
continue;
t_mac0_bw = WMI_DBS_HW_MODE_MAC0_BANDWIDTH_GET(
t_mac0_bw = WMA_HW_MODE_MAC0_BANDWIDTH_GET(
wma->hw_mode.hw_mode_list[i]);
/*
* Firmware advertises max bw capability as CBW 80+80
@ -2580,31 +2582,36 @@ static int8_t wma_get_matching_hw_mode_index(tp_wma_handle wma,
if (t_mac0_bw < mac0_bw)
continue;
t_mac1_tx_ss = WMI_DBS_HW_MODE_MAC1_TX_STREAMS_GET(
t_mac1_tx_ss = WMA_HW_MODE_MAC1_TX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
if (t_mac1_tx_ss != mac1_tx_ss)
continue;
t_mac1_rx_ss = WMI_DBS_HW_MODE_MAC1_RX_STREAMS_GET(
t_mac1_rx_ss = WMA_HW_MODE_MAC1_RX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
if (t_mac1_rx_ss != mac1_rx_ss)
continue;
t_mac1_bw = WMI_DBS_HW_MODE_MAC1_BANDWIDTH_GET(
t_mac1_bw = WMA_HW_MODE_MAC1_BANDWIDTH_GET(
wma->hw_mode.hw_mode_list[i]);
if (t_mac1_bw < mac1_bw)
continue;
dbs_mode = WMI_DBS_HW_MODE_DBS_MODE_GET(
dbs_mode = WMA_HW_MODE_DBS_MODE_GET(
wma->hw_mode.hw_mode_list[i]);
if (dbs_mode != dbs)
continue;
agile_dfs_mode = WMI_DBS_HW_MODE_AGILE_DFS_GET(
agile_dfs_mode = WMA_HW_MODE_AGILE_DFS_GET(
wma->hw_mode.hw_mode_list[i]);
if (agile_dfs_mode != dfs)
continue;
sbs_mode = WMA_HW_MODE_SBS_MODE_GET(
wma->hw_mode.hw_mode_list[i]);
if (sbs_mode != sbs)
continue;
found = i;
WMA_LOGI("%s: hw_mode index %d found",
__func__, i);
@ -2621,9 +2628,10 @@ static int8_t wma_get_matching_hw_mode_index(tp_wma_handle wma,
* @mac1_bw: MAC1 bandwidth configuration
* @dbs: HW DBS capability
* @dfs: HW Agile DFS capability
* @sbs: HW SBS capability
*
* Get the HW mode index corresponding to the HW modes spatial stream,
* bandwidth, DBS and Agile DFS capability
* bandwidth, DBS, Agile DFS and SBS capability
*
* Return: Index number if a match is found or -negative value if not found
*/
@ -2632,7 +2640,8 @@ int8_t wma_get_hw_mode_idx_from_dbs_hw_list(enum hw_mode_ss_config mac0_ss,
enum hw_mode_ss_config mac1_ss,
enum hw_mode_bandwidth mac1_bw,
enum hw_mode_dbs_capab dbs,
enum hw_mode_agile_dfs_capab dfs)
enum hw_mode_agile_dfs_capab dfs,
enum hw_mode_sbs_capab sbs)
{
tp_wma_handle wma;
uint32_t mac0_tx_ss, mac0_rx_ss;
@ -2651,14 +2660,14 @@ int8_t wma_get_hw_mode_idx_from_dbs_hw_list(enum hw_mode_ss_config mac0_ss,
__func__, mac0_tx_ss, mac0_rx_ss, mac0_bw);
WMA_LOGI("%s: MAC1: TxSS=%d, RxSS=%d, BW=%d",
__func__, mac1_tx_ss, mac1_rx_ss, mac1_bw);
WMA_LOGI("%s: DBS capab=%d, Agile DFS capab=%d",
__func__, dbs, dfs);
WMA_LOGI("%s: DBS=%d, Agile DFS=%d, SBS=%d",
__func__, dbs, dfs, sbs);
return wma_get_matching_hw_mode_index(wma, mac0_tx_ss, mac0_rx_ss,
mac0_bw,
mac1_tx_ss, mac1_rx_ss,
mac1_bw,
dbs, dfs);
dbs, dfs, sbs);
}
/**
@ -2694,14 +2703,15 @@ QDF_STATUS wma_get_hw_mode_from_idx(uint32_t idx,
param = wma->hw_mode.hw_mode_list[idx];
hw_mode->mac0_tx_ss = WMI_DBS_HW_MODE_MAC0_TX_STREAMS_GET(param);
hw_mode->mac0_rx_ss = WMI_DBS_HW_MODE_MAC0_RX_STREAMS_GET(param);
hw_mode->mac0_bw = WMI_DBS_HW_MODE_MAC0_BANDWIDTH_GET(param);
hw_mode->mac1_tx_ss = WMI_DBS_HW_MODE_MAC1_TX_STREAMS_GET(param);
hw_mode->mac1_rx_ss = WMI_DBS_HW_MODE_MAC1_RX_STREAMS_GET(param);
hw_mode->mac1_bw = WMI_DBS_HW_MODE_MAC1_BANDWIDTH_GET(param);
hw_mode->dbs_cap = WMI_DBS_HW_MODE_DBS_MODE_GET(param);
hw_mode->agile_dfs_cap = WMI_DBS_HW_MODE_AGILE_DFS_GET(param);
hw_mode->mac0_tx_ss = WMA_HW_MODE_MAC0_TX_STREAMS_GET(param);
hw_mode->mac0_rx_ss = WMA_HW_MODE_MAC0_RX_STREAMS_GET(param);
hw_mode->mac0_bw = WMA_HW_MODE_MAC0_BANDWIDTH_GET(param);
hw_mode->mac1_tx_ss = WMA_HW_MODE_MAC1_TX_STREAMS_GET(param);
hw_mode->mac1_rx_ss = WMA_HW_MODE_MAC1_RX_STREAMS_GET(param);
hw_mode->mac1_bw = WMA_HW_MODE_MAC1_BANDWIDTH_GET(param);
hw_mode->dbs_cap = WMA_HW_MODE_DBS_MODE_GET(param);
hw_mode->agile_dfs_cap = WMA_HW_MODE_AGILE_DFS_GET(param);
hw_mode->sbs_cap = WMA_HW_MODE_SBS_MODE_GET(param);
return QDF_STATUS_SUCCESS;
}
@ -2763,7 +2773,7 @@ bool wma_is_hw_dbs_capable(void)
for (i = 0; i < wma->num_dbs_hw_modes; i++) {
param = wma->hw_mode.hw_mode_list[i];
WMA_LOGI("%s: HW param: %x", __func__, param);
if (WMI_DBS_HW_MODE_DBS_MODE_GET(param)) {
if (WMA_HW_MODE_DBS_MODE_GET(param)) {
WMA_LOGI("%s: HW (%d) is DBS capable", __func__, i);
found = 1;
break;
@ -2866,14 +2876,14 @@ void wma_update_intf_hw_mode_params(uint32_t vdev_id, uint32_t mac_id,
wma->interfaces[vdev_id].mac_id = mac_id;
if (mac_id == 0) {
wma->interfaces[vdev_id].tx_streams =
WMI_DBS_HW_MODE_MAC0_TX_STREAMS_GET(param);
WMA_HW_MODE_MAC0_TX_STREAMS_GET(param);
wma->interfaces[vdev_id].rx_streams =
WMI_DBS_HW_MODE_MAC0_RX_STREAMS_GET(param);
WMA_HW_MODE_MAC0_RX_STREAMS_GET(param);
} else {
wma->interfaces[vdev_id].tx_streams =
WMI_DBS_HW_MODE_MAC1_TX_STREAMS_GET(param);
WMA_HW_MODE_MAC1_TX_STREAMS_GET(param);
wma->interfaces[vdev_id].rx_streams =
WMI_DBS_HW_MODE_MAC1_RX_STREAMS_GET(param);
WMA_HW_MODE_MAC1_RX_STREAMS_GET(param);
}
}
@ -2929,15 +2939,15 @@ QDF_STATUS wma_get_dbs_hw_modes(bool *one_by_one_dbs, bool *two_by_two_dbs)
uint32_t t_conf1_tx_ss, t_conf1_rx_ss;
uint32_t dbs_mode;
t_conf0_tx_ss = WMI_DBS_HW_MODE_MAC0_TX_STREAMS_GET(
t_conf0_tx_ss = WMA_HW_MODE_MAC0_TX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
t_conf0_rx_ss = WMI_DBS_HW_MODE_MAC0_RX_STREAMS_GET(
t_conf0_rx_ss = WMA_HW_MODE_MAC0_RX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
t_conf1_tx_ss = WMI_DBS_HW_MODE_MAC1_TX_STREAMS_GET(
t_conf1_tx_ss = WMA_HW_MODE_MAC1_TX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
t_conf1_rx_ss = WMI_DBS_HW_MODE_MAC1_RX_STREAMS_GET(
t_conf1_rx_ss = WMA_HW_MODE_MAC1_RX_STREAMS_GET(
wma->hw_mode.hw_mode_list[i]);
dbs_mode = WMI_DBS_HW_MODE_DBS_MODE_GET(
dbs_mode = WMA_HW_MODE_DBS_MODE_GET(
wma->hw_mode.hw_mode_list[i]);
if (((((t_conf0_tx_ss == conf1_tx_ss) &&

2
core/wma/src/wma_utils_ut.c
View file

@ -73,7 +73,7 @@ void wma_set_dbs_capability_ut(uint32_t dbs)
}
for (i = 0; i < wma->num_dbs_hw_modes; i++) {
WMI_DBS_HW_MODE_DBS_MODE_SET(wma->hw_mode.hw_mode_list[i],
WMA_HW_MODE_DBS_MODE_SET(wma->hw_mode.hw_mode_list[i],
dbs);
}