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pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

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[ Upstream commit 69388e15f5078c961b9e5319e22baea4c57deff1 ]

According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4e8 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")

Fixes: 0bd50d719b ("pinctrl: cherryview: prevent concurrent access to GPIO controllers")
Signed-off-by: Grace Kao <[email protected]>
Reported-by: Brian Norris <[email protected]>
Reviewed-by: Brian Norris <[email protected]>
Acked-by: Mika Westerberg <[email protected]>
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
This commit is contained in:
Grace Kao 2020-04-17 12:11:54 +08:00 • committed by Greg Kroah-Hartman
commit 5b96668b63
1 changed files with 4 additions and 0 deletions
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4
drivers/pinctrl/intel/pinctrl-cherryview.c
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@ -1474,11 +1474,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
struct irq_chip *chip = irq_desc_get_chip(desc);
unsigned long pending;
unsigned long flags;
u32 intr_line;
chained_irq_enter(chip, desc);
raw_spin_lock_irqsave(&chv_lock, flags);
pending = readl(pctrl->regs + CHV_INTSTAT);
raw_spin_unlock_irqrestore(&chv_lock, flags);
for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
unsigned irq, offset;