pwm: Changes for v3.18-rc1

There are no new drivers here, only a couple of fixes all over the place.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJURLy0AAoJEN0jrNd/PrOhP8UP/Auwzo3Wd0cFJEnJVdyrj9sN
 l0Wwnib3edKQDNhPmnQE77fXT3oo4XhdNAzoCRfcy+e/yVq6p3og+tz6z87DahCt
 nnfKCTK8MRw1d4tniVHVhi0BDSfbjXdJCiXe/mmqfPTegIxF5ps7JnHbTZuIOx8i
 XRfxBvAqmmXGmNQANfW7/iZdDzSKQ70DjHIBFn/pa1eLQG2lJ54joo/yeA1Kk0Ly
 CSJGF7L7XLV9mWxXA1vZWGgpIV6dduObtOpRlOwPkG7tGmXInbUery0G429ah8ce
 o7LevARZ41yi7fA6nDtNDG8FWq7oavq0jWvRQuq8M5xn+aYGmYZdd/W47Xc0xUnF
 eGAmz0q78poDTZDA1EXoY/6Og+JgI8x+PpDxaRN4FIa6gpkcTQEuafpo9BLfGo4K
 PTDckq3FqOkIcX5jA4X5OP8lgnz08PZDQaE6QomuNpeKJRy/3aEKWRJ+C4XWcF9t
 7bgkBTLEOq51UXUNuPjogGtwmW8Mf6WOfRdvaRLiTH7KJlJjgwxJYrs0o2D1q7bz
 TbZeDRcRhG7ZfR/5nz7qDEA8FjgwOLCMciqBT4wBc47Er7VaURWl5aoSuTxalJ3A
 hqk8jbwKhaAO+L7N6Jzqk1TqxOKC9HbhaJO7to4gir07bEpXOHQu1jFwZEAmRbvH
 x1prpzzghUPmVv0WYh36
 =llZK
 -----END PGP SIGNATURE-----

Merge tag 'pwm/for-3.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm

Pull pwm changes from Thierry Reding:
 "There are no new drivers here, only a couple of fixes all over the
  place"

* tag 'pwm/for-3.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: Let PWM_CLPS711X depend on HAS_IOMEM
  pwm: atmel: Fix calculation of prescale value
  pwm: Fix uninitialized warnings in pwm_get()
  pwm: rockchip: Allow polarity invert on rk3288
  pwm: imx: Avoid sample FIFO overflow for i.MX PWM version2
  pwm: imx: Cleanup indentation for register definitions
  pwm: imx: Fix the macro MX3_PWMCR_PRESCALER(x) definition
  pwm: Fix possible ZERO_SIZE_PTR pointer dereferencing error.
  pwm: lpss: make it buildable only on X86
  pwm: lpss: use c99 initializers in structures
  pwm: lpss: Fix build failure on PowerPC
  pwm: lpss: pci: Move to use pcim_enable_device()
  pwm: lpss: Properly split driver to parts
  pwm: lpss: Add ACPI and PCI IDs for Intel Braswell
  pwm: fsl-ftm: Select REGMAP_MMIO
  pwm: fsl-ftm: Document 'big-endian' property
  pwm: fsl-ftm: Convert to direct regmap API usage
  pwm: fsl-ftm: Clean up the code

Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt

@@ -1,5 +1,20 @@
 Freescale FlexTimer Module (FTM) PWM controller
 
+The same FTM PWM device can have a different endianness on different SoCs. The
+device tree provides a property to describing this so that an operating system
+device driver can handle all variants of the device. Refer to the table below
+for the endianness of the FTM PWM block as integrated into the existing SoCs:
+
+	SoC     | FTM-PWM endianness
+	--------+-------------------
+	Vybrid  | LE
+	LS1     | BE
+	LS2     | LE
+
+Please see ../regmap/regmap.txt for more detail about how to specify endian
+modes in device tree.
+
+
 Required properties:
 - compatible: Should be "fsl,vf610-ftm-pwm".
 - reg: Physical base address and length of the controller's registers
@@ -16,7 +31,8 @@ Required properties:
 - pinctrl-names: Must contain a "default" entry.
 - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
   See pinctrl/pinctrl-bindings.txt for details of the property values.
-
+- big-endian: Boolean property, required if the FTM PWM registers use a big-
+  endian rather than little-endian layout.
 
 Example:
 
@@ -32,4 +48,5 @@ pwm0: pwm@40038000 {
 			<&clks VF610_CLK_FTM0_EXT_FIX_EN>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_pwm0_1>;
+		big-endian;
 };

Documentation/devicetree/bindings/pwm/pwm-rockchip.txt

@@ -7,8 +7,8 @@ Required properties:
    "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
  - reg: physical base address and length of the controller's registers
  - clocks: phandle and clock specifier of the PWM reference clock
- - #pwm-cells: should be 2. See pwm.txt in this directory for a
-   description of the cell format.
+ - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
+   for a description of the cell format.
 
 Example: