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media: camss: csiphy: Ensure clock mux config is done before the rest
Add a write memory barier after clock mux config and before the rest of the csiphy config. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hansverk@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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@ -364,6 +364,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
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val |= cfg->csid_id;
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}
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writel_relaxed(val, csiphy->base_clk_mux);
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wmb();
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writel_relaxed(0x1, csiphy->base +
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CAMSS_CSI_PHY_GLBL_T_INIT_CFG0);
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