mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
Merge 0a09ea53e5 on remote branch
Change-Id: I77220650b640d9bc3a9207d7b69c292328cf9741
This commit is contained in:
commit
5bc4610304
10 changed files with 74 additions and 41 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/debugfs.h>
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@ -56,6 +56,16 @@
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IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \
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} while (0)
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#define IPA_GSB_ERR_RL(fmt, args...) \
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do { \
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pr_err_ratelimited_ipa(IPA_GSB_DRV_NAME " %s:%d " fmt, \
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__func__, __LINE__, ## args); \
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IPA_IPC_LOGGING(ipa3_get_ipc_logbuf(), \
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IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \
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IPA_IPC_LOGGING(ipa3_get_ipc_logbuf_low(), \
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IPA_GSB_DRV_NAME " %s:%d " fmt, ## args); \
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} while (0)
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#define IPA_GSB_MAX_MSG_LEN 512
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#ifdef CONFIG_DEBUG_FS
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@ -1184,7 +1194,7 @@ static int ipa_bridge_tx_dp_internal(u32 hdl, struct sk_buff *skb,
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}
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if (unlikely(!ipa_gsb_ctx->iface[hdl]->is_resumed)) {
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IPA_GSB_ERR("iface %d was suspended\n", hdl);
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IPA_GSB_ERR_RL("iface %d was suspended\n", hdl);
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return -EFAULT;
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}
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@ -51,7 +51,7 @@
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#endif
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#define DRV_NAME "ipa"
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#define DELAY_BEFORE_FW_LOAD 500
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#define IPA_SUBSYSTEM_NAME "ipa_fws"
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#define IPA_UC_SUBSYSTEM_NAME "ipa_uc"
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@ -126,6 +126,7 @@ static int ipa3_alloc_pkt_init(void);
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static void ipa3_load_ipa_fw(struct work_struct *work);
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static DECLARE_WORK(ipa3_fw_loading_work, ipa3_load_ipa_fw);
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static DECLARE_DELAYED_WORK(ipa3_fw_load_failure_handle, ipa3_load_ipa_fw);
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static void ipa_dec_clients_disable_clks_on_wq(struct work_struct *work);
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static DECLARE_DELAYED_WORK(ipa_dec_clients_disable_clks_on_wq_work,
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@ -3566,16 +3567,18 @@ static void ipa3_q6_avoid_holb(void)
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* setting HOLB on Q6 pipes, and from APPS perspective
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* they are not valid, therefore, the above function
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* will fail.
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* Also don't reset the HOLB timer to 0 for Q6 pipes.
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*/
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ipahal_write_reg_n_fields(
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IPA_ENDP_INIT_HOL_BLOCK_TIMER_n,
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ep_idx, &ep_holb);
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ipahal_write_reg_n_fields(
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IPA_ENDP_INIT_HOL_BLOCK_EN_n,
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ep_idx, &ep_holb);
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/* IPA4.5 issue requires HOLB_EN to be written twice */
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if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)
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/* For targets > IPA_4.0 issue requires HOLB_EN to
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* be written twice.
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*/
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if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)
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ipahal_write_reg_n_fields(
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IPA_ENDP_INIT_HOL_BLOCK_EN_n,
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ep_idx, &ep_holb);
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@ -6812,12 +6815,14 @@ static void ipa3_load_ipa_fw(struct work_struct *work)
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IPADBG("Entry\n");
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IPA_ACTIVE_CLIENTS_INC_SIMPLE();
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result = ipa3_attach_to_smmu();
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if (result) {
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IPAERR("IPA attach to smmu failed %d\n", result);
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IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
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return;
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if(!ipa3_ctx->ipa_pil_load)
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{
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result = ipa3_attach_to_smmu();
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if (result) {
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IPAERR("IPA attach to smmu failed %d\n", result);
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IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
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return;
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}
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}
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if (ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_EMULATION &&
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@ -6836,13 +6841,18 @@ static void ipa3_load_ipa_fw(struct work_struct *work)
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result = ipa3_manual_load_ipa_fws();
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}
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IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
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if (result) {
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IPAERR("IPA FW loading process has failed result=%d\n",
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result);
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ipa3_ctx->ipa_pil_load++;
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IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
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IPADBG("IPA firmware loading deffered to a work queue\n");
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queue_delayed_work(ipa3_ctx->transport_power_mgmt_wq,
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&ipa3_fw_load_failure_handle,
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msecs_to_jiffies(DELAY_BEFORE_FW_LOAD));
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return;
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}
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IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
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mutex_lock(&ipa3_ctx->fw_load_data.lock);
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ipa3_ctx->fw_load_data.state = IPA_FW_LOAD_STATE_LOADED;
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mutex_unlock(&ipa3_ctx->fw_load_data.lock);
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@ -6902,7 +6912,7 @@ static void ipa_fw_load_sm_handle_event(enum ipa_fw_load_event ev)
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if (ipa3_ctx->fw_load_data.state == IPA_FW_LOAD_STATE_INIT) {
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ipa3_ctx->fw_load_data.state =
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IPA_FW_LOAD_STATE_SMMU_DONE;
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goto out;
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goto sched_fw_load;
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}
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if (ipa3_ctx->fw_load_data.state ==
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IPA_FW_LOAD_STATE_FWFILE_READY) {
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@ -67,6 +67,7 @@ int ipa3_enable_data_path(u32 clnt_hdl)
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holb_cfg.en = IPA_HOLB_TMR_EN;
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} else if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_11 &&
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(ep->client == IPA_CLIENT_WLAN1_CONS ||
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ep->client == IPA_CLIENT_WLAN2_CONS ||
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ep->client == IPA_CLIENT_USB_CONS)) {
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holb_cfg.en = IPA_HOLB_TMR_EN;
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holb_cfg.tmr_val = IPA_HOLB_TMR_VAL_4_5;
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@ -1497,8 +1498,10 @@ int ipa3_set_reset_client_cons_pipe_sus_holb(bool set_reset, u32 tmr_val,
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IPA_ENDP_INIT_HOL_BLOCK_EN_n,
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pipe_idx, &ep_holb);
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/* IPA4.5 issue requires HOLB_EN to be written twice */
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if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)
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/* For targets > IPA_4.0 issue requires HOLB_EN to be
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* written twice.
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*/
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if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)
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ipahal_write_reg_n_fields(
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IPA_ENDP_INIT_HOL_BLOCK_EN_n,
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pipe_idx, &ep_holb);
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@ -345,20 +345,22 @@ static void ipa3_send_nop_desc(struct work_struct *work)
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return;
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}
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list_add_tail(&tx_pkt->link, &sys->head_desc_list);
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sys->len++;
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sys->nop_pending = false;
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memset(&nop_xfer, 0, sizeof(nop_xfer));
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nop_xfer.type = GSI_XFER_ELEM_NOP;
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nop_xfer.flags = GSI_XFER_FLAG_EOT;
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nop_xfer.xfer_user_data = tx_pkt;
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if (gsi_queue_xfer(sys->ep->gsi_chan_hdl, 1, &nop_xfer, true)) {
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list_del(&tx_pkt->link);
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kmem_cache_free(ipa3_ctx->tx_pkt_wrapper_cache, tx_pkt);
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spin_unlock_bh(&sys->spinlock);
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IPAERR("gsi_queue_xfer for ch:%lu failed\n",
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sys->ep->gsi_chan_hdl);
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queue_work(sys->wq, &sys->work);
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return;
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}
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sys->len++;
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sys->nop_pending = false;
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spin_unlock_bh(&sys->spinlock);
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/* make sure TAG process is sent before clocks are gated */
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@ -3658,17 +3660,21 @@ static struct sk_buff *handle_page_completion(struct gsi_chan_xfer_notify
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sys->ep->client == IPA_CLIENT_APPS_LAN_CONS) {
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rx_skb = alloc_skb(0, GFP_ATOMIC);
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if (unlikely(!rx_skb)) {
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IPAERR("skb alloc failure\n");
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list_del(&rx_pkt->link);
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if (!rx_page.is_tmp_alloc) {
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init_page_count(rx_page.page);
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} else {
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dma_unmap_page(ipa3_ctx->pdev, rx_page.dma_addr,
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rx_pkt->len, DMA_FROM_DEVICE);
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__free_pages(rx_pkt->page_data.page,
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IPA_WAN_PAGE_ORDER);
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IPAERR("skb alloc failure, free all pending pages\n");
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list_for_each_entry_safe(rx_pkt, tmp, head, link) {
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rx_page = rx_pkt->page_data;
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size = rx_pkt->data_len;
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list_del_init(&rx_pkt->link);
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if (!rx_page.is_tmp_alloc) {
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init_page_count(rx_page.page);
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} else {
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dma_unmap_page(ipa3_ctx->pdev, rx_page.dma_addr,
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rx_pkt->len, DMA_FROM_DEVICE);
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__free_pages(rx_pkt->page_data.page,
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IPA_WAN_PAGE_ORDER);
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}
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rx_pkt->sys->free_rx_wrapper(rx_pkt);
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}
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rx_pkt->sys->free_rx_wrapper(rx_pkt);
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IPA_STATS_INC_CNT(ipa3_ctx->stats.rx_page_drop_cnt);
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return NULL;
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}
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@ -2155,6 +2155,8 @@ struct ipa3_context {
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bool modem_load_ipa_fw;
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bool fnr_stats_not_supported;
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bool is_device_crashed;
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int ipa_pil_load;
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};
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struct ipa3_plat_drv_res {
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@ -179,7 +179,7 @@ static int ipa3_nat_ipv6ct_mmap(
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/*
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* Check if no smmu or non dma coherent
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*/
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if (!cb->valid || !dev_is_dma_coherent(cb->dev)) {
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if (cb && cb->dev && (!cb->valid || !dev_is_dma_coherent(cb->dev))) {
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IPADBG("Either smmu valid=%u and/or DMA coherent=%u false\n",
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cb->valid, !dev_is_dma_coherent(cb->dev));
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@ -250,6 +250,7 @@ int ipa3_send_adpl_msg(unsigned long skb_data)
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list_add_tail(&msg->link, &ipa3_odl_ctx->adpl_msg_list);
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atomic_inc(&ipa3_odl_ctx->stats.numer_in_queue);
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mutex_unlock(&ipa3_odl_ctx->adpl_msg_lock);
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wake_up(&ipa3_odl_ctx->adpl_msg_waitq);
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IPA_STATS_INC_CNT(ipa3_odl_ctx->stats.odl_rx_pkt);
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return 0;
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@ -527,7 +528,9 @@ static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count,
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int ret = 0;
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char __user *start = buf;
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struct ipa3_push_msg_odl *msg;
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DEFINE_WAIT_FUNC(wait, woken_wake_function);
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add_wait_queue(&ipa3_odl_ctx->adpl_msg_waitq, &wait);
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while (1) {
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IPADBG_LOW("Writing message to adpl pipe\n");
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if (!ipa3_odl_ctx->odl_state.odl_open)
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@ -572,9 +575,6 @@ static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count,
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IPA_STATS_INC_CNT(ipa3_odl_ctx->stats.odl_tx_diag_pkt);
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kfree(msg);
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msg = NULL;
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} else {
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ret = -EAGAIN;
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break;
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}
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ret = -EAGAIN;
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@ -587,9 +587,9 @@ static ssize_t ipa_adpl_read(struct file *filp, char __user *buf, size_t count,
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if (start != buf)
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break;
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wait_woken(&wait, TASK_INTERRUPTIBLE, MAX_SCHEDULE_TIMEOUT);
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}
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remove_wait_queue(&ipa3_odl_ctx->adpl_msg_waitq, &wait);
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if (start != buf && ret != -EFAULT)
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ret = buf - start;
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@ -665,6 +665,7 @@ int ipa_odl_init(void)
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odl_cdev = ipa3_odl_ctx->odl_cdev;
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INIT_LIST_HEAD(&ipa3_odl_ctx->adpl_msg_list);
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init_waitqueue_head(&ipa3_odl_ctx->adpl_msg_waitq);
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mutex_init(&ipa3_odl_ctx->adpl_msg_lock);
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mutex_init(&ipa3_odl_ctx->pipe_lock);
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@ -58,6 +58,7 @@ struct ipa_odl_context {
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bool odl_ctl_msg_wq_flag;
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struct ipa3_odlstats stats;
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u32 odl_pm_hdl;
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wait_queue_head_t adpl_msg_waitq;
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};
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struct ipa3_push_msg_odl {
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@ -1439,7 +1439,7 @@ int ipa3_uc_debug_stats_alloc(
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result = ipa3_uc_send_cmd((u32)(cmd.phys_base),
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command,
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IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
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false, 10 * HZ);
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false, 20 * HZ);
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if (result) {
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IPAERR("fail to alloc offload stats\n");
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goto cleanup;
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@ -6332,8 +6332,8 @@ int ipa3_cfg_ep_holb(u32 clnt_hdl, const struct ipa_ep_cfg_holb *ep_holb)
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ipa3_ctx->ep[clnt_hdl].holb.en = IPA_HOLB_TMR_EN;
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ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n,
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clnt_hdl, ep_holb);
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/* IPA4.5 issue requires HOLB_EN to be written twice */
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if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5)
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/* For targets > IPA_4.0 issue requires HOLB_EN to be written twice */
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if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_0)
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ipahal_write_reg_n_fields(IPA_ENDP_INIT_HOL_BLOCK_EN_n,
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clnt_hdl, ep_holb);
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