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usb: dwc3: Enable PHY deep low power mode in L1 suspend

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Currently controller is enabling only shallow low power mode during
L1 suspend in host mode. Power savings can be improved by allowing
deep low power mode allowing PLL to be turned OFF. Configuring
the GUCTL1 register to enable this feature.

Change-Id: Iea6cfa2c9085a01f45a9f0d633c80368ad085806
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
Signed-off-by: Jack Pham <jackp@codeaurora.org>
This commit is contained in:
Elson Roy Serrao 2019-08-12 12:59:07 -07:00 • committed by Jack Pham
commit 5c3cf2427c
2 changed files with 9 additions and 0 deletions
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1
drivers/usb/dwc3/core.h
View file

@ -265,6 +265,7 @@
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
#define DWC3_GUCTL1_IP_GAP_ADD_ON(n) (n << 21)
#define DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST BIT(8)
/* Global Status Register */
#define DWC3_GSTS_OTG_IP BIT(10)

8
drivers/usb/dwc3/dwc3-msm.c
View file

@ -2436,6 +2436,10 @@ static void dwc3_en_sleep_mode(struct dwc3_msm *mdwc)
reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0));
reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), reg);
reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUCTL1);
reg |= DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST;
dwc3_msm_write_reg(mdwc->base, DWC3_GUCTL1, reg);
}
static void dwc3_dis_sleep_mode(struct dwc3_msm *mdwc)
@ -2445,6 +2449,10 @@ static void dwc3_dis_sleep_mode(struct dwc3_msm *mdwc)
reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB2PHYCFG(0));
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
dwc3_msm_write_reg(mdwc->base, DWC3_GUSB2PHYCFG(0), reg);
reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUCTL1);
reg &= ~DWC3_GUCTL1_L1_SUSP_THRLD_EN_FOR_HOST;
dwc3_msm_write_reg(mdwc->base, DWC3_GUCTL1, reg);
}
static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc)