From 5c4f146f8782eb8c4ac2b28f0d07e2ab0513dc78 Mon Sep 17 00:00:00 2001
From: Santosh Mardi <gsantosh@qti.qualcomm.com>
Date: Sat, 17 Oct 2020 23:07:39 +0530
Subject: [PATCH] ARM: dts: msm: Add L3 snoop bw device on Lahaina

Create L3 devfreq device on Lahaina to scale L3
based on snoop bandwidth.

Change-Id: I6ac8f482bde014989bb578e2f052b8d8c5f77aaa
---
 qcom/shima.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 29160b4e1cc2..82503e5d2631 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -2303,6 +2303,28 @@
 		qcom,count-unit = <0x10000>;
 	};
 
+	snoop_l3_bw: qcom,snoop-l3-bw {
+		compatible = "qcom,devfreq-icc-l3bw";
+		reg = <0x18590100 0xa0>;
+		reg-names = "ftbl-base";
+		qcom,bus-width = <32>;
+		governor = "bw_hwmon";
+		interconnects =
+			<&epss_l3_cpu MASTER_EPSS_L3_APPS
+			 &epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
+	};
+
+	snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 {
+		compatible = "qcom,bimc-bwmon4";
+		reg = <0x90b9100 0x300>, <0x90b9000 0x200>;
+		reg-names = "base", "global_base";
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,mport = <0>;
+		qcom,hw-timer-hz = <19200000>;
+		qcom,target-dev = <&snoop_l3_bw>;
+		qcom,count-unit = <0x10000>;
+	};
+
 	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
 		compatible = "qcom,devfreq-icc-l3";
 		reg = <0x18590100 0xa0>;