From 5c5dda42daa8b6a5b17367a464c1c2a7099da84e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 8 Jun 2020 18:10:20 +0530 Subject: [PATCH] ARM: dts: msm: Add bus interconnect property for cdsp Update cdsp node with interconnect property. Change-Id: I122824187dd6cfe4dc490604be3ad24b64b4414c --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 24ae0ef8f0d8..da4ec9f07137 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1510,6 +1510,8 @@ memory-region = <&pil_cdsp_mem>; qcom,complete-ramdump; + interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + /* Inputs from turing */ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, <&cdsp_smp2p_in 0 0>,