Merge "ARM: dts: msm: Add cdsp rpmsg entry in Lahaina"

bindings/soc/qcom/cdsprm.txt

@@ -0,0 +1,78 @@
+Qualcomm Technologies, Inc. CDSP Request Manager driver
+
+CDSP Request Manager driver implements an rpmsg interface with
+CDSP subsystem to serve L3 frequency and CPU QoS requests from CDSP.
+It also interacts with NPU, Camera modules for Cx iPeak mitigations and
+thermal module via CDSP/HVX cooling devices for thermal mitigation of
+CDSP core.
+
+Required properties:
+- compatible: Must be "qcom,msm-cdsprm-rpmsg"
+- qcom,glink-channels: Glink channel for communication with CDSP
+- qcom,intents: A list of <number of intents, size of each intent>
+
+- qcom,msm-cdsp-rm: A sub-device node to define CDSPM RM, Cx iPeak mitigation
+		driver and CDSP core thermal cooling device
+	Required properties:
+	- compatible: Must be "qcom,msm-cdsp-rm"
+	- qcom,qos-latency-us: pm_qos latency vote to be applied on CDSP request in
+				micro seconds
+	- qcom,qos-maxhold-ms: Maximum hold time for pm_qos latency vote from CDSP
+				in milli seconds
+	- qcom,compute-cx-limit-en: To enable CX ipeak limit management for compute
+				subsystem
+	- qcom,compute-priority-mode: when Cx iPeak mitigation is enabled,
+				this field sets desired compute priority mode
+				for AIX and HVX concurrency cases based on
+				following values, where in HVX and NPU cores,
+				if required, are throttled in concurrency based
+				on the selected priority mode
+				1 : HVX_MAX - Allows HVX to run at maximum possible
+						frequency during concurrency with NPU
+				2 : AIX_MAX - Allows NPU to run at maximum possible
+						frequency during concurrency with HVX
+				3 : HVX_OVER_AIX - Allows HVX to run at a higher
+						frequency than NPU during concurrency
+				4 : AIX_OVER_HVX - Allows NPU to run at a higher
+						frequency than HVX during concurrency
+	- #cooling-cells: Number of cooling cells for CDSP cooling device based on
+			CDSP Q6 core clock throttling
+
+- qcom,msm-hvx-rm: A sub-device node to define HVX based thermal cooling device
+	Required properties:
+	- compatible: Must be "qcom,msm-hvx-rm"
+	- #cooling-cells: Number of cooling cells for CDSP cooling device based on
+			HVX hardware throttling
+
+- qcom,cdsp-l3: A sub-device node to define CDSP L3 target device for L3
+		clock voting
+	Required properties:
+	- compatible: Must be "qcom,cdsp-l3"
+	- qcom,target-dev: The DT device that corresponds to the CDSP L3
+			devfreq-simple-dev
+
+Example:
+	qcom,msm_cdsprm_rpmsg {
+		compatible = "qcom,msm-cdsprm-rpmsg";
+		qcom,glink-channels = "cdsprmglink-apps-dsp";
+		qcom,intents = <0x14 64>;
+
+		qcom,cdsp-l3 {
+			compatible = "qcom,cdsp-l3";
+			qcom,target-dev = <&cdsp-cdsp-l3-lat>;
+		};
+
+		qcom,msm_cdsp_rm {
+			compatible = "qcom,msm-cdsp-rm";
+			qcom,qos-latency-us = <100>;
+			qcom,qos-maxhold-ms = <20>;
+			qcom,compute-cx-limit-en;
+			qcom,compute-priority-mode = <2>;
+			#cooling-cells = <2>;
+		};
+
+		 msm_hvx_rm: qcom,msm_hvx_rm {
+			compatible = "qcom,msm-hvx-rm";
+			#cooling-cells = <2>;
+		};
+	};

qcom/lahaina.dtsi

@@ -2670,6 +2670,18 @@
 						0x2000 3
 						0x4400 2>;
 			};
+
+			qcom,msm_cdsprm_rpmsg {
+				compatible = "qcom,msm-cdsprm-rpmsg";
+				qcom,glink-channels = "cdsprmglink-apps-dsp";
+				qcom,intents = <0x20 12>;
+
+				msm_cdsp_rm: qcom,msm_cdsp_rm {
+					compatible = "qcom,msm-cdsp-rm";
+					qcom,qos-latency-us = <60>;
+					qcom,qos-maxhold-ms = <20>;
+				};
+			};
 		};
 
 		glink_spss: spss {