From 5cb262db52030c4f507fa4eb671ee39df660df1b Mon Sep 17 00:00:00 2001
From: Tao Zhang <taozha@qti.qualcomm.com>
Date: Fri, 28 May 2021 15:18:36 +0800
Subject: [PATCH] ARM: dts: msm: Add apss dl cti0 for yupik

Add app dl cti0 to device tree for DCC LLCC timeout on yupik.

Change-Id: I526cba88c14458eb32a345fe707edd6e3e3f5266
---
 qcom/yupik-coresight.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/qcom/yupik-coresight.dtsi b/qcom/yupik-coresight.dtsi
index 9d0b985226b8..d2bf1745c734 100644
--- a/qcom/yupik-coresight.dtsi
+++ b/qcom/yupik-coresight.dtsi
@@ -3324,5 +3324,17 @@
 		clocks = <&aopcc QDSS_CLK>;
 		clock-names = "apb_pclk";
 	};
+
+	cti0_apss_dl: cti@7862000 {
+		compatible = "arm,primecell";
+		arm,primecell-periphid = <0x000bb966>;
+		reg = <0x7862000 0x1000>;
+		reg-names = "cti-base";
+
+		coresight-name = "coresight-cti-apss_dl_cti0";
+
+		clocks = <&aopcc QDSS_CLK>;
+		clock-names = "apb_pclk";
+	};
 };